JPH04276378A - Control signal generator for dynamic memory - Google Patents

Abstract

PURPOSE:To switch an access mode and to speed up action by judging automatically on a hardware whether or not DRAM can be operated in a fast access mode. CONSTITUTION:A row address register 18 holds once a row address value sent by a CPU 10. A comparator 20 compares the row address of a next access cycle with the previous row address value held by the row address register. The coincidence/non-coincidence of the row address value is detected and the result is sent to a timing generator 11. The timing generator generates a column address strobing signal only when the row address values are coincident with each other, an address multiplexer 22 is controlled so as to send a column address signal only and a high-speed access mode is performed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control signal generator for a dynamic memory that automatically switches between a standard access mode and a high-speed access mode on hardware. More specifically, the present invention relates to a control signal generator that automatically determines whether or not a high-speed access mode can be executed based on a sent address value, and accesses a dynamic memory with priority given to the high-speed access mode.

0002

[Prior Art] Dynamic memory (hereinafter referred to as "
(abbreviated as “DRAM”) is static RAM (SRA).
Compared to M), it has the advantage of being easier to increase capacity and being cheaper per bit, but on the other hand, it supplies duplicate address signals to reduce the number of pins on the package.
Therefore, there is a problem that the address access speed becomes slow. Therefore, DRAMs having a relatively large capacity are designed to operate not only in the standard access mode but also in a high-speed access mode in which part of the address signal is omitted to improve access speed.

A control signal generator for DRAM is DRA
Row address strobe (hereinafter "RAS") for M
) signal and column address strobe (hereinafter abbreviated as "
(abbreviated as "CAS") signal can be supplied.
It includes a generator and an address multiplexer that can duplicate row address signals and column address signals and supply them to the DRAM.

First, in the standard access mode, a row address signal is taken in at the leading edge of the falling edge of the RAS signal output from the timing generator, and a column address signal is taken in at the leading edge of the falling edge of the CAS signal. Most of the cycle time at this time is the time required to select the word line for address access and perform the sense amplifier operation, and the precharge time after the operation is completed. Next, in page mode, which is a typical example of a high-speed access mode, as long as the row address values are the same, the CAS signal is clocked in while the RAS signal is low, thereby capturing only the column address signal, and Randomly access memory cells on an address. So once the row address is set,
It is faster than the standard access mode because there is no need to access the row address each time.

By the way, as a control signal generator for DRAM, a commercially available dedicated LSI called a "DRAM controller" is often used. This controller includes address multiplexers, timing generators,
It has a built-in refresh circuit, etc., and has sufficient functions for normal DRAM control. Some DRAM controllers can control DRAM in high-speed access mode as well as standard access mode, but they have control terminals for switching access modes, and the control terminals cannot be accessed from the outside. It is controlled by sending commands for mode switching.

[0006]

[Problems to be Solved by the Invention] When using the high-speed access mode, only storage cells on the same row address can be accessed, and when accessing storage cells that are not on the same row address, standard access mode Since it is necessary to return to the mode, the address arrangement must be considered and managed in software. In this way, switching between standard access mode and high-speed access mode and managing address allocation must all be done in software, which complicates software design and increases the designer's burden and design time. was there. As mentioned above, DRAM has a high-speed access mode in addition to the standard access mode, but the high-speed access mode is not used very effectively except for special uses such as sequentially accessing consecutive addresses. The current situation is that this is not the case.

An object of the present invention is to eliminate the drawbacks of the prior art as described above, and to automatically determine on hardware whether or not it is possible to operate in high-speed access mode from a sent address value. To provide a control signal generator for a DRAM, which preferentially executes a high-speed access mode if operable, and automatically switches to a standard access mode if high-speed operation is not possible, thereby increasing the overall speed. That's true.

[0008]

[Means for Solving the Problem] In a DRAM control signal generator, a RAS signal and a CAS signal are transmitted to the DRAM.
A timing generator capable of supplying a signal, a row address signal and a column address signal are duplicated, and the DRA
and an address multiplexer that can be supplied to M. In order to achieve the above object, the present invention provides the DRAM
In the control signal generator, there is a row address register that temporarily holds the sent row address value, and a row address register that holds the next row address value sent in the next access cycle. It is characterized in that it is equipped with a comparator that compares the row address value with the previous row address value to detect whether or not the row address value matches, and sends the result to the timing generator.

[0009]

[Operation] The row address value sent to the row address register is once taken in and held. When the next row address value is fetched on the next access cycle, the address value held in the row address register is
Sent to comparator. The comparator compares the address value sent in the next access cycle with the previous row address value sent from the row address register, detects whether or not the row address values match, and sends the result to the timing generator. do. When the row address values match, the timing generator continues to keep the RAS signal active, clocks the CAS signal, and controls the output of only the column address signal to execute the high speed access mode. In the case of a mismatch, if it was operating in fast access mode, it switches to standard access mode by deactivating the RAS signal. If it was operating in standard access mode, it continues in standard access mode. In this way, the hardware automatically determines whether it is standard access mode or high-speed access mode, and the DRA is given priority to high-speed access mode.
Control M.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of a DRAM control signal generator according to the present invention. This DRAM
The control signal generator 26 for the CPU (Central
Processing Unit )10 and DRAM24
It is interposed between the DRAM and the DRAM, and performs functions such as sending and receiving various control signals, decomposing and multiplexing into row and column addresses, determining the access mode of the DRAM, and generating refresh addresses. Each circuit block will be explained below.

[0011] The timing generator 11 is a DRA
This is a circuit block that generates various timing signals necessary to actually control M24. This timing
Inside the generator 11, there is a control section 12 that receives various control signals supplied from the CPU 10, and a circuit that generates a RAS signal and a CAS signal under the control of the control section 12, that is, a RAS generation section 14 and a CAS generation section 16. . The control unit 12 also includes an operation mode register, an initial setting register, and the like. Address multiplexer 22 is CP
The address sent from U10 is divided into a row address and a column address and duplicated, and the timing generator 11
The address signal suitable for the standard access mode or the high-speed access mode is output according to the signal from the control unit 12 of the D.
It has the function of supplying to RAM. In standard access mode, addresses are duplicated and sent in the order of row address signal and column address signal. When in fast access mode, only column address signals are sent. The row address for refresh is also input to this multiplexer, and the output address is switched depending on whether memory access or refresh is performed.

DRAM control signal generator 26 of the present invention
It further includes a row address register 18 and a comparator 20, which have the function of automatically switching the DRAM 24 between a standard access mode and a high-speed access mode. A row address value from the CPU 10 is sent to the row address register 18, and the row address value is once captured and held at the trailing edge of the memory access by a control signal coming from the control section 12 of the timing generator 11. When the next row address value is fetched on the next access cycle, the row address value held in row address register 18 is sent to comparator 20 along with the next row address value. The comparator 20 compares both input row address values, detects coincidence or mismatch of the row address values, and sends the result to the RAS generation section 14 of the timing generator 11. When both row address values match, the timing generator 11 controls the address multiplexer 22 to keep the RAS signal active to the DRAM 24, clock the CAS signal, and send out only the column address signal. to run fast access mode. If there is a mismatch, the RAS signal is made inactive to switch to the standard access mode if it was operating in the fast access mode. If it was operating in standard access mode, it continues in standard access mode. In fact, D
A circuit for supplying read/write signals is also required to drive the RAM, but the description will be omitted since it will complicate the explanation and is not directly related to the access mode of the present invention.

Next, the operation of the DRAM control signal generator will be explained based on the timing chart shown in FIG. For example, in the first access cycle #1, CPU1
If a DRAM reference command from address A0 (row address value is A, column address value is 0) is issued, the timing generator 11 sequentially outputs a RAS signal and a CAS signal. Also, the address signal A output from the CPU 10
0 is input to the address multiplexer 22, and is duplicated into a row address signal A and a column address signal 0, and is sent to the DRAM.
24. In terms of timing, when the RAS signal falls, the row address value A is taken in, and then when the CAS signal falls, the column address value 0 is taken in. Then, a memory operation is performed according to the read/write signal. In this first cycle, the DRAM 24 is driven in the standard access mode, and the access speed is slow. Note that the row address value A is also set in the row address register 18 at the trailing edge of the memory access.

Address A in the next access cycle #2
1 (row address value is A, column address value is 1), the row address value A matches the row address value of the previous cycle, so the comparator 20 detects the match between the two row address values. The timing generator 11 that has received the detection signal shown in FIG. Address multiplexer 2 receives address A1 output from CPU 10
2 outputs only the column address signal 1, and the DRAM 26 takes in the column address value 1 when the CAS signal falls. Thereafter, as long as the row address value is constant at A, the high-speed access mode is executed in the same procedure until access cycle #n (addresses A2 to An) even if the column address value is random.

Next, in access cycle #n+1, the CPU
10 to address B0 (row address value is B, column address value is 0) is output. This time, since the row address value B is different from the previous row address value A, the comparator 20
A detection signal indicating a mismatch is generated from the timing generator 11, which causes the timing generator 11 to raise the RAS signal, switch to the standard access mode, and start the access cycle #.
A procedure similar to that described in processing operation 1 is executed. Then, reading/writing is performed on the memory cell located at the address taken into the DRAM 24.

[0016] In addition to the above, in DRAM, it is necessary to periodically insert a refresh cycle, but in this case, the RAS signal is forced to rise and the refresh cycle is inserted. In this case, the next time the memory is accessed, the standard access mode as shown in access cycle #1 is entered, for example. Furthermore, if a high-speed CPU is used, a wait (WAIT) is inserted in the standard access mode to extend the cycle period.

[0017]

[Effects of the Invention] As described above, the present invention determines whether or not high-speed access mode is executable on hardware, and if it is executable, automatically executes memory access in high-speed access mode. Therefore, the DRAM can be operated at high speed and efficiently as a whole. Furthermore, there is no need to design the software to support the high-speed access mode, and there is no need to consider the access mode at all, which reduces design effort and design time. The present invention is particularly effective in operating modes where memory is often accessed in an orderly manner (eg, image processing, data pattern comparison, sequential data transfer, etc.), but is also effective in other cases.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a DRAM control signal generation device according to the present invention.

FIG. 2 is a timing chart of the DRAM control signal generator of FIG. 1;

[Explanation of symbols]

10 CPU 11 Timing generator 18 Row address register 20 Comparator 22 Address multiplexer 24 DRAM 26 DRAM control signal generator

Claims (1)

[Claims] 1. A timing generator capable of supplying a row address strobe signal and a column address strobe signal to a dynamic memory, and a timing generator capable of supplying duplicated row address signals and column address signals to the memory. In a control signal generator equipped with an address multiplexer, there is a row address register that temporarily holds the sent row address value, and a row address register that temporarily holds the row address value sent in the next access cycle. The timing generator includes a comparator that compares the row address value held in the register with the previous row address value to detect whether or not the row address value matches, and sends the result to the timing generator. A control signal generating device for a dynamic memory, characterized in that when a match occurs, only a column address strobe signal is generated and the address multiplexer is controlled to send only a column address signal to execute a high speed access mode.