JPH04273529A - Parallel arithmetic circuit - Google Patents

Abstract

PURPOSE:To obtain a parallel arithmetic circuit which simultaneously supplies arithmetic commands to each of plural computing elements constituting a pipe line processing. CONSTITUTION:This circuit is equipped with plural command registers CR1, 2, and 3 which store the prescribed arithmetic commands, data register DR which stores the data necessary for the arithmetic operation by the arithmetic commands stored in the command registers CR1, 2, and 3, plural decoders DC1, 2, and 3 which decode the arithmetic commands stored in the command registers CR1, 2, and 3, plural computing elements EX-1, 2, and 3 which operates the prescribed arithmetic operation based on the decoded results of the decoders DC1, 2, and 3, and command reconstructing means 1 which simultaneously supplies the arithmetic commands to each of the plural command registers CR1, 2, and 3.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a parallel arithmetic circuit,
Specifically, the present invention relates to a parallel calculation circuit that performs numerical calculation processing at high speed and is suitable for use in fields such as image processing.

In recent years, for example in image processing and various simulations, many parallel arithmetic circuits have been developed to perform numerical arithmetic processing at high speed. For example, this involves integrating multiple arithmetic units onto the same chip and having each arithmetic unit perform calculations.If each of these arithmetic units performs parallel operations at the same time, extremely high-speed calculations are possible. .

However, in order to operate each arithmetic unit at the same time, it is necessary to simultaneously supply arithmetic instructions and input data, which are arithmetic parameters, to a plurality of arithmetic units. Therefore, it is necessary to simultaneously supply arithmetic instructions and input data to a plurality of arithmetic units.

0004

[Prior Art] Conventional parallel arithmetic circuits of this type include:
For example, there is a configuration as shown in FIG.

[0005] This parallel arithmetic circuit is roughly divided into an instruction register CR, a data register DR, a decoder DC, and a
It is composed of arithmetic units EX-1, EX-2, and EX-3. The instruction register CR temporarily holds and stores a predetermined operation instruction input from the outside, and the data register DR
is used to temporarily hold and store data that becomes parameters when performing calculations based on predetermined calculation instructions.

[0006] The decoder DC decodes the arithmetic instructions stored in the instruction register CR, and decodes the arithmetic instructions stored in the instruction register CR, and decodes each arithmetic unit EX-1, EX-2,
3. In addition, the arithmetic units EX-1, EX-2,
3 operates with three pipelines.

In the above configuration, when the arithmetic instructions stored in the instruction register CR are decoded one at a time by the decoder DC, the execution of the arithmetic operation is normally performed as shown in FIG.
This is done in the order shown in 8. Note that 3
Assume that clock timing is required.

That is, the decoder DC outputs one operation instruction from the instruction register CR every clock cycle.
~■ are read out sequentially, and the decoding results are sent to each arithmetic unit E.
Supplied to X-1, 2, and 3. And arithmetic unit EX-1
After the calculation instructions ■ and ■ are processed in the calculation unit EX-2, the calculation instructions ■ and ■ are processed in the calculation unit EX-2, and then the calculation instructions ■ and ■ are processed in the calculation unit EX-3, and the calculation instructions ■ and ■ are processed in the calculation unit EX-1. , arithmetic unit EX
At -3, the arithmetic instruction ■ is processed.

By the way, in this case, eight operation instructions
It takes 10 clock cycles to execute all of (2).

0010

[Problems to be Solved by the Invention] However, in such a conventional parallel arithmetic circuit, the decoder DC sequentially reads out one arithmetic instruction (1) to (2) from the instruction register CR every clock cycle. Since the decoding result was configured to be supplied to each arithmetic unit EX-1, EX-2, and EX-3, it was not possible to simultaneously supply the decoded result of the arithmetic instruction to multiple arithmetic units EX-1, EX-2, and EX-3. Arithmetic unit E
Although the configuration is such that three pipeline processing is possible by X-1, EX-2, and EX-3, the pipeline does not operate effectively and the arithmetic units EX-1, EX-2, and EX-3 are in an empty state. There was a problem that there were many.

The fact that the pipeline does not operate effectively means that, for example, as shown in FIGS. 9 and 10, when arithmetic instruction (2) is executed based on the output result of arithmetic instruction (2) This is even more noticeable when the address of the output data of the calculation instruction ■ by the calculation unit EX-2 matches the address of the input data of the calculation instruction ■ by the calculation unit EX-2. Because pipeline processing has stopped, 8 operation instructions
It takes 12 clock cycles to execute all of (2), and furthermore, the arithmetic units EX-1, EX-2, and EX-3 become vacant, and the calculation speed decreases.

[Objective] Therefore, it is an object of the present invention to provide a parallel arithmetic circuit that simultaneously supplies arithmetic instructions to a plurality of arithmetic units performing pipeline processing.

[0013]

[Means for Solving the Problems] In order to achieve the above object, the parallel arithmetic circuit according to the present invention includes a plurality of instruction registers CR1, 2, 3 for storing predetermined arithmetic instructions, and a plurality of instruction registers CR1, 2, 3 for storing predetermined arithmetic instructions. a data register DR that stores data necessary for the operation according to the instruction register CR1, 2, 3, a plurality of decoders DC1, 2, 3 that decode the operation instructions stored in the instruction register CR1, 2, 3; . Each of the plurality of instruction registers CR1, 2
, 3 simultaneously.

Further, the clock of the decoders DC1, 2, DC3 is CLOCK1, the number of the arithmetic units EX-1, 2, 3 is N, and the clock of the arithmetic units EX-1, 2, 3 is CLOCK1.
In the case of CK2, it is preferable to set CLOCK1 to N×CLOCK2, and the instruction registers CR1, 2, 3
If overflow occurs, the corresponding instruction register CR1,
It is effective to invalidate the decoding results of the decoders DC1, 2, 3 corresponding to the instruction registers CR1, 2, 3, and stop decoding until the instruction registers CR1, 2, 3 become empty. be.

[0015]

According to the present invention, arithmetic instructions are simultaneously supplied by the instruction reconfiguration means to a plurality of instruction registers in which predetermined arithmetic instructions are stored.

That is, the pipeline operation is efficiently performed by each of the plurality of arithmetic units, and the arithmetic speed is improved.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on the drawings. 1 to 5 are diagrams showing one embodiment of a parallel arithmetic circuit according to the present invention, and FIG. 1 is a block diagram showing the overall configuration of this embodiment.

First, the configuration will be explained. In FIG. 1, the same numbers as those given to the conventional example shown in FIG. 6 indicate the same parts.

The parallel arithmetic circuit of this embodiment can be roughly divided into instruction registers CR1, 2, 3, data registers DR, decoders DC1, 2, 3, arithmetic units EX-1, 2, 3, and instruction reconfiguration means. Dependency controller (d
It consists of instruction registers CR1, 2, 3, decoder DC
1, 2, and 3 each consist of three pieces corresponding to the arithmetic units EX-1, EX-2, and EX-3.

The dependency controller 1 handles resources and operands between arithmetic instructions.
operand), and if there is no dependency, execute the process as is, or if there is a dependency, nop
(No-operation) This is to interrupt processing by outputting an instruction. Specifically, when an arithmetic instruction is input from the outside, it decodes the arithmetic instructions one by one and combines them with the output data of the previously read arithmetic instruction. It checks whether the address of the currently read arithmetic instruction matches the input data, and outputs a nop instruction only if they match.

Next, the operation will be explained. Arithmetic unit EX-1, 2
, 3, as shown in FIGS. 2 and 3, first, the dependency controller 1 distributes arithmetic instructions input from the outside to each instruction register CR1, 2, and 3, and the instruction register CR1 , 2, 3 are decoded by decoders DC1, 2, 3, and the decoding results are sent to each computing unit EX-1, 2, 3.
are output simultaneously.

The decoders DC1, 2, 3 extract 1 from the instruction registers CR1, 2, 3 every clock cycle.
The arithmetic instructions (1), (2), and (2) are read out, respectively, and the decoded results are supplied to each of the arithmetic units EX-1, EX-2, and EX-3, respectively. Then, in the arithmetic unit EX-1, the arithmetic instructions ■, ■,
■ is processed sequentially, and in the arithmetic unit EX-2, the operation instructions ■, ■
, the arithmetic unit EX-3 processes the arithmetic instructions ■, ■, ■.

Incidentally, in this case, all eight operation instructions (1) to (2) are executed in 6 clock cycles. Next, similarly to the conventional examples shown in FIGS. 9 and 10, if this embodiment is applied to the case where the calculation instruction ■ is executed based on the output result of the calculation instruction ■, in this case, the gap between the calculation instructions ■ and ■ Because dependency occurs in , that is, the operation instruction ■
The output result of is the input of the calculation instruction ■, so the calculation instruction ■
If the execution of the operation instruction (2) is not completed, the operation instruction (2) will not be executed. In such a case, as shown in FIGS. 4 and 5, nop is transferred from the dependency controller 1 to the instruction register CR2.
The instruction is issued, and the operation of the arithmetic unit EX-2 is suspended until the arithmetic instruction (2) is completed by the arithmetic unit EX-2. Even in this case, since arithmetic processing is performed in the arithmetic units EX1 and EX3, it takes only seven clock cycles until all eight arithmetic instructions (1) to (2) are executed.

Therefore, the calculation time required in the conventional example is 10 and 12 clock cycles, respectively, but in this embodiment, it is reduced to 6 and 7 clock cycles, respectively. Here, the dependency controller 1 is the computing unit EX
If the dependency controller 1 operates with a clock three times faster than the clocks -1, 2, and 3, the dependency controller 1 can decode three operation instructions in one clock cycle. That is, a total of 9 address comparisons are required for the first instruction decode, 12 address comparisons are required for the second instruction, and 15 address comparisons are required for the third instruction decode.

As a result of address comparison, if dependency occurs, nop is written to instruction registers CR1, CR2, CR3.
An instruction is issued, but if arithmetic instructions with dependence occur consecutively, the instruction registers CR1, CR2, CR3 may overflow. In such a case, a control signal is sent from the dependency controller 1 to the instruction registers CR1, 2, CR1, 2, CR3 to invalidate the decoding result in that execution cycle and wait for decoding until the instruction registers CR1, 2, 3 become free. 3, and decoders DC1, 2, 3
is output to.

[0026] This prevents arithmetic instructions from overflowing. In this way, in this embodiment, the dependency controller 1 can simultaneously supply arithmetic instructions to the plurality of instruction registers CR1, CR2, CR3 that store predetermined arithmetic instructions, and each of the plurality of arithmetic units EX-1, 2 and 3 allow efficient pipeline operation.

Therefore, a plurality of arithmetic units EX-1, EX-2,
3 can be executed simultaneously, and the calculation speed can be improved. Note that although the above embodiment has been explained using a parallel arithmetic circuit having three arithmetic units as an example, the present invention is not limited to this.
It goes without saying that the number of computing units can be set depending on the required parallel operations.

[0028]

According to the present invention, arithmetic instructions can be simultaneously supplied to a plurality of instruction registers storing predetermined arithmetic instructions by the instruction reconfiguration means, and efficient pipeline operation can be performed by each of the plurality of arithmetic units.

Therefore, a plurality of arithmetic units can perform calculations at the same time, and the calculation speed can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of operation of an embodiment of the present invention.

FIG. 3 is a diagram showing an example of execution of arithmetic instructions according to an embodiment of the present invention.

FIG. 4 is a diagram showing another example of operation of an embodiment of the present invention.

FIG. 5 is a diagram showing another example of execution of arithmetic instructions according to an embodiment of the present invention.

FIG. 6 is a block diagram showing the overall configuration of a conventional example.

FIG. 7 is a diagram showing an operation example of a conventional example.

FIG. 8 is a diagram showing an example of execution of a conventional arithmetic instruction.

FIG. 9 is a diagram showing another operation example of the conventional example.

FIG. 10 is a diagram showing another example of execution of conventional arithmetic instructions.

[Explanation of symbols]

1 Dependency controller (instruction reconfiguration means) CR1, 2, 3 Instruction register DC1, 2, 3
Decoder DR Data register EX-1, 2, 3 Arithmetic unit

Claims (3)

[Claims] 1. A plurality of instruction registers that store predetermined arithmetic instructions, a data register that stores data necessary for an operation based on the arithmetic instructions stored in the instruction registers, and a data register that stores the arithmetic instructions stored in the instruction registers. A plurality of decoders perform decoding, a plurality of arithmetic units perform predetermined arithmetic operations based on the decoding results of the decoders, and a predetermined arithmetic instruction to be stored in the instruction register is read, and the arithmetic instruction is stored in each of the plurality of instruction registers. instruction reconfiguration means for simultaneously supplying;
A parallel arithmetic circuit comprising: [Claim 2] CLOCK the clock of the decoder.
1. The number of the arithmetic units is N, and the clock of the arithmetic units is CLO.
2. The parallel arithmetic circuit according to claim 1, wherein when CLOCK2 is used, CLOCK1 is N×CLOCK2. 3. When the instruction register overflows, the decoding result of a decoder corresponding to the instruction register is invalidated, and the decoder stops decoding until the instruction register becomes empty. Term 1 or 2 parallel computing device.