JPH04273125A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for preventing that dust particles produced at a dry pretreatment process adhere to a silicon wafer regarding a method for preventing the contamination with dust particles at the manufacturing process of a semiconductor device. CONSTITUTION:The title manufacture is constituted so as to be provided with a process to convert the surface part of a revealed silicon substrate 1 into an insulating layer 4 or a process to form a silicon oxide film on the revealed silicon substrate.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for preventing dust contamination in a semiconductor device manufacturing process. Before sputtering aluminum for wiring on silicon chips formed on a silicon wafer, there is a process in which the silicon oxide film on the wafer is usually removed using an argon ion shower. This dry pretreatment process generates dust such as carbon and insulators adhering to the inner walls of the ion shower chamber.

On the other hand, since the ion shower has a positive charge, it concentrates more on the exposed silicon portions of the silicon wafer that are at a negative potential, such as on the dicing lines that divide the silicon wafer into a plurality of chips. The dust generated during the dry pretreatment process is caught up in this ion shower and adheres to the chip.
Particularly, it accumulates on the dicing line. In chip wiring circuits, dust adheres to peripheral patterns, and this is one of the factors that reduces process yield.

0003

[Prior Art] In order to prevent the dust generated during the dry pretreatment process described above from adhering to the silicon wafer, conventionally the parts and inner walls of the ion shower chamber were frequently cleaned.

0004

[Problem to be solved by the invention] However, it is not easy to completely clean the parts and inner walls inside the chamber.
This resulted in a decrease in throughput. In addition, parts were frequently replaced with new ones, but as a result, maintenance of the ion shower equipment naturally became expensive.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for preventing dust generated in the dry pretreatment step from adhering to a silicon wafer.

[0006]

[Means for solving the problem] The above problem can be solved by converting the exposed surface portion of the silicon substrate into an insulating layer or by forming a silicon oxide film on the exposed silicon substrate portion. resolved.

FIG. 1 is a diagram explaining the principle of the present invention. Figure 1
(a) is a plan view of a portion of a wafer where dicing lines 3 and chips 2 are formed on a substrate 1. An insulating layer 4 is formed on a silicon substrate 1 along a dicing line 3 . Figure 1(b) is the XY of Figure 1(a)
FIG. As shown in FIG. 1, the surface of the substrate 1 along the dicing line 3 is covered with an insulating layer 4 and is not exposed.

[0008]

[Operation] In Figure 1, since the surface of the substrate 1 is covered with the insulating layer 4 along the dicing line 3, the ion shower does not concentrate on the dicing line 3, and therefore the ion shower that occurs during the dry pretreatment process is prevented. Dust will not be deposited on the chips and dicing lines along with the ion shower.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Two embodiments of the present invention will be described with reference to the drawings. In the figures, the same symbols represent the same parts.

First Embodiment FIG. 2 is an explanatory diagram of each step in the method of the first embodiment. FIG. 2(a) shows a process of applying a resist 5 onto a chip 2 and a dicing line 3 formed on a substrate 1. FIG. 2(b) shows a resist pattern 5 formed by patterning the resist 5.
11 shows a step of selectively implanting oxygen ions into the portion of the substrate 1 exposed above the dicing line 3 using ' as a mask. FIG. 2C shows a state in which an insulator layer 6 is formed on the dicing line 3 as a result of the oxygen ion implantation. FIG. 2D shows a step in which the resist pattern 5' is removed using reactive ion plasma etching using oxygen. here,
Preparations for the next wiring aluminum (Al) sputtering process are completed.

Second Embodiment FIG. 3 is an explanatory diagram of each step in the method of the second embodiment. Figure 3(a) shows dicing line 3.
It is a figure which shows the initial state in the process of opening. In the figure, for example, PSG (
A phosphosilicate glass film 8 is formed. Figure 3(b)
1 shows a step in which a resist pattern 7 is formed in order to open a dicing line 3 by dry etching the SiO2 film 9 and the PSG film 8.
Figure 3(c) shows that when the resist 7 is removed and dry pretreatment is performed, the SiO2 film 9 on the dicing line 3 is removed by controlling the dry etching time.
indicates a process in which a portion 9' of the SiO2 film 9 is left without being completely removed.

Here, the following wiring aluminum (Al
) Preparation for the sputtering process is completed. In the above two examples, the effect of the SiO2 film on the dicing line 3 was evaluated by actually measuring the amount of dust adhering to the chips. Table 1 shows the number of dust particles measured using Surfscan (Surfscan 4500, manufactured by TENCOR). The number of dust particles is 0.2 μ in diameter.
m or more, 0.68μm or more, 1.6
Three types of numbers are written for those larger than 4 μm. In addition, "No SiO2" means the case where the silicon substrate 1 is exposed on the dicing line, and "No SiO2" means the case where the silicon substrate 1 is exposed at the dicing line.
``With O2'' is a case where the silicon substrate 1 is covered with a SiO2 layer in the dicing line. Also, ``Dry pretreatment + transportation'' is a case where the silicon substrate 1 is covered with a SiO2 layer in the dicing line.
This is a case where the silicon wafer is transported to an ion shower chamber and subjected to dry pretreatment as usual.
"Transport only" means that the silicon wafer is simply transported to the ion shower chamber without any processing. As can be seen from Table 1, in ``dry pretreatment + transportation'', the number of dust particles larger than 0.2 μm is ``with SiO2'' and ``without SiO2''.
This is reduced to one-sixth of that in the case of . Also, “Si
In the case of ``without O2'', the number of dust particles larger than 0.2 μm increases by 10 times by performing dry pretreatment, but in the case of ``with SiO2'', the number only increases three times.

[0013]

[Table 1]

[0014]

[Effects of the Invention] According to the present invention, it is possible to sufficiently prevent dust contamination in the dry pretreatment performed prior to aluminum sputtering for wiring, and as a result, short circuits between wirings are reduced and manufacturing yields are improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is an explanatory diagram of each step in the method of the first example.

FIG. 3 is an explanatory diagram of each step in the method of the second example.

[Explanation of symbols]

1 Silicon substrate, 2 Chip 3 Dicing line 4, 6, 8, 9, 9' Insulating layer 5, 7
Resist 5' Resist pattern

Claims (3)

[Claims] Claim 1. In a method for manufacturing a semiconductor device in which a silicon wafer divided into a plurality of semiconductor chips is surface-treated by an ion shower at a scribe line, prior to the surface treatment by the ion shower, the silicon wafer is exposed at the scribe line. 1. A method for manufacturing a semiconductor device, comprising the step of providing an insulating layer on a surface portion of a silicon substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulator layer is formed by selective ion implantation of oxygen. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the insulator layer is formed by growing an oxide film.