JPH0427184Y2 - - Google Patents

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Publication number
JPH0427184Y2
JPH0427184Y2 JP4992386U JP4992386U JPH0427184Y2 JP H0427184 Y2 JPH0427184 Y2 JP H0427184Y2 JP 4992386 U JP4992386 U JP 4992386U JP 4992386 U JP4992386 U JP 4992386U JP H0427184 Y2 JPH0427184 Y2 JP H0427184Y2
Authority
JP
Japan
Prior art keywords
insulating layer
via hole
via holes
lower electrode
printing direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP4992386U
Other languages
Japanese (ja)
Other versions
JPS62162875U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4992386U priority Critical patent/JPH0427184Y2/ja
Publication of JPS62162875U publication Critical patent/JPS62162875U/ja
Application granted granted Critical
Publication of JPH0427184Y2 publication Critical patent/JPH0427184Y2/ja
Expired legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

【考案の詳細な説明】 〈産業上の利用分野〉 この考案は、各種電子機器に使用する印刷多層
基板に係り、特に絶縁層の上下に設けた下側電極
と上側電極を接続するため、絶縁層に設けたビア
ホールの構造に関するものである。
[Detailed description of the invention] <Industrial application field> This invention relates to printed multilayer boards used in various electronic devices, and in particular, in order to connect the lower electrode and upper electrode provided above and below the insulating layer, This relates to the structure of via holes provided in layers.

〈従来の技術と問題点〉 印刷多層基板の基本的構造は第3図と第4図に
示すように、アルミナ基板1の上に下側電極2を
設け、その上に絶縁層3をスクリーン印刷によつ
て設け、絶縁層3の上に上側電極4を所定のパタ
ーンに形成し、これらの上に更に絶縁層と電極を
必要なだけ順次積層していくと共に、下位の電極
と上位の電極を絶縁層3に設けたビアホール5の
部分で電気的に接続して構成されている。
<Prior art and problems> The basic structure of a printed multilayer board is as shown in Figures 3 and 4, in which a lower electrode 2 is provided on an alumina substrate 1, and an insulating layer 3 is screen printed on it. The upper electrode 4 is formed on the insulating layer 3 in a predetermined pattern, and the required number of insulating layers and electrodes are sequentially laminated on top of these. They are configured to be electrically connected through via holes 5 provided in the insulating layer 3.

上記絶縁層3は、その信頼性の観点から、スク
リーン印刷により少なくとも絶縁材を2〜3回程
度重ねる必要があり、また絶縁層3に設けるビア
ホール5は0.2〜0.5mm角程度の小さい寸法に形成
されている。
From the viewpoint of reliability, the insulating layer 3 needs to be overlaid with insulating material at least two to three times by screen printing, and the via hole 5 provided in the insulating layer 3 is formed to have a small size of about 0.2 to 0.5 mm square. has been done.

スクリーン印刷は印刷方向が一定の方向から行
なわれるため、第1絶縁層3aの上に第2絶縁層
3bを形成するとき、ビアホール5の部分におい
て、第1絶縁層3aの印刷方向手前の内周に絶縁
材のにじみ6が発生し、ビアホール5がふさがつ
たり狭くなり、上下電極の導通不良が発生すると
いう問題がある。
Since screen printing is performed from a fixed printing direction, when forming the second insulating layer 3b on the first insulating layer 3a, in the via hole 5 part, the inner periphery of the first insulating layer 3a in front of the printing direction is There is a problem in that the insulating material bleeds 6 and the via hole 5 becomes blocked or narrowed, resulting in poor conduction between the upper and lower electrodes.

上記ビアホール5のにじみ発生は、第2絶縁層
3bの形成時、スクリーン印刷法でのスキージに
よるインクの押込みが、先に形成された第1絶縁
層3aのビアホールにおける印刷方向手前側端部
の厚みによる段差によつて生じることになる。
The occurrence of bleeding in the via hole 5 is caused by the ink being pushed in with a squeegee in the screen printing method when forming the second insulating layer 3b, which causes the thickness of the front end in the printing direction of the via hole of the first insulating layer 3a to be formed earlier. This is caused by the difference in level.

この考案は上記のような問題点を解決するため
になされたものであり、絶縁層形成時におけるビ
アホールへのにじみ発生を抑えることができ、上
下電極の確実な接続状態を得ることができる印刷
多層基板を提供することを目的とする。
This idea was made in order to solve the above problems, and it is a printed multilayer that can suppress bleeding into via holes when forming an insulating layer and can obtain a reliable connection between upper and lower electrodes. The purpose is to provide a substrate.

〈問題点を解決するための手段〉 この考案は、上記のような問題点を解決するた
めになされたものであり、絶縁層に設けたビアホ
ールを、最下位絶縁層のビアホールに対し、上位
絶縁層のビアホールが印刷方向の手前側に大きく
なる形状にして形成したものである。
<Means for solving the problem> This idea was made in order to solve the above problem. The via holes in the layer are formed in such a shape that they become larger toward the front side in the printing direction.

〈作用〉 下側電極上に第1絶縁層を形成した後その上に
第2絶縁層を形成する。
<Operation> After forming a first insulating layer on the lower electrode, a second insulating layer is formed thereon.

第1絶縁層に設けるビアホールのパターンに対
し、第2絶縁層のビアホールパターンを印刷方向
の手前が大きくなるように形成し、第1絶縁層の
厚みによる第2絶縁層のビアホールにおけるにじ
みの発生を抑え、ビアホール部分での上下電極の
接続を確実にする。
With respect to the via hole pattern provided in the first insulating layer, the via hole pattern in the second insulating layer is formed so that the front side in the printing direction is larger to prevent bleeding in the via holes in the second insulating layer due to the thickness of the first insulating layer. to ensure a secure connection between the upper and lower electrodes at the via hole.

〈実施例〉 以下、この考案の実施例を添付図面の第1図と
第2図にもとづいて説明する。
<Example> Hereinafter, an example of this invention will be described based on FIGS. 1 and 2 of the accompanying drawings.

これらの各図において、第3図と第4図に示す
従来例と同じ部分は同一の符号を付けて説明を省
略する。
In each of these figures, the same parts as in the conventional example shown in FIGS. 3 and 4 are given the same reference numerals, and their explanation will be omitted.

図示のように、下側電極2と上側電極4を導通
させるために絶縁層3に設けたビアホール5にお
いて、第1絶縁層3aに設けるビアホール5aは
導通に必要な所定の形状に形成する。
As shown in the figure, in the via hole 5 provided in the insulating layer 3 to establish electrical conduction between the lower electrode 2 and the upper electrode 4, the via hole 5a provided in the first insulating layer 3a is formed in a predetermined shape necessary for electrical conduction.

これに対し、第2絶縁層3bに設けるビアホー
ル5bは、第1図の矢印Aに示す印刷方向の手前
側において、第1絶縁層3aのビアホール5aよ
りも例えば0.05〜0.2mm程度大きくなる形状に形
成する。
On the other hand, the via hole 5b provided in the second insulating layer 3b has a shape that is, for example, about 0.05 to 0.2 mm larger than the via hole 5a in the first insulating layer 3a on the front side in the printing direction shown by arrow A in FIG. Form.

これにより、第2絶縁層3bを印刷により形成
するとき、ビアホール5bの印刷方向手前側の端
縁部分は第1絶縁層3a上にとどまり、スクリー
ン印刷法でのスキージによるインクの押込みがあ
つても、先に形成された第1絶縁層3aのビアホ
ール5a内へのにじみが抑制される。
As a result, when forming the second insulating layer 3b by printing, the edge portion of the via hole 5b on the front side in the printing direction remains on the first insulating layer 3a, even if ink is pushed in with a squeegee in the screen printing method. , the bleeding of the previously formed first insulating layer 3a into the via hole 5a is suppressed.

従つてビアホール5は所定の口径が確保され、
上下電極2,4の導通が確実に行なえる。
Therefore, the via hole 5 is ensured to have a predetermined diameter,
Conductivity between the upper and lower electrodes 2 and 4 can be ensured.

〈効果〉 以上のように、この考案によると、最下位絶縁
層のビアホールに対して上位絶縁層のビアホール
を絶縁層印刷方向の手前側が大きくなる形状に形
成したので、上位絶縁層のスクリーン印刷時にお
けるビアホール部分へのインクの押込みがあつて
も、先に形成された最下位絶縁層のビアホール内
へのにじみが抑制され、従つてビアホールに所定
の口径を確保でき、上下電極の導通が確実に行な
え、接続の信頼性が大幅に向上する。
<Effects> As described above, according to this invention, the via holes in the upper insulating layer are formed in a shape such that the front side in the printing direction of the insulating layer is larger than the via hole in the lowest insulating layer. Even if the ink is forced into the via hole part, the bleeding of the lowermost insulating layer formed earlier into the via hole is suppressed, and therefore a predetermined diameter can be secured in the via hole, and conduction between the upper and lower electrodes is ensured. connection reliability is greatly improved.

また、ビアホール全体を大きくすることなく所
定の口径を確保できるので、ビアホール設計の小
型化が可能になる。
Furthermore, since a predetermined diameter can be secured without enlarging the entire via hole, it is possible to downsize the via hole design.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案に係る印刷多層基板の拡大縦
断面図、第2図は同上の要部を示す拡大斜視図、
第3図は従来の印刷多層基板を示す拡大縦断面
図、第4図は同上の要部を示す斜視図である。 2……下側電極、3……絶縁層、4……上側電
極、5……ビアホール。
FIG. 1 is an enlarged longitudinal sectional view of a printed multilayer board according to this invention, and FIG. 2 is an enlarged perspective view showing the main parts of the same.
FIG. 3 is an enlarged vertical sectional view showing a conventional printed multilayer board, and FIG. 4 is a perspective view showing the main parts of the same. 2... Lower electrode, 3... Insulating layer, 4... Upper electrode, 5... Via hole.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 下側電極上に複数層の絶縁層を印刷によつて設
け、この絶縁層上に形成した上側電極と前記下側
電極を絶縁層に設けたビアホールの部分で電気的
に接続した印刷多層基板において、絶縁層に設け
たビアホールを、最下位絶縁層のビアホールに対
し、上位絶縁層のビアホールが印刷方向の手前側
に大きくなる形状にして形成したことを特徴とす
る印刷多層基板。
In a printed multilayer board in which a plurality of insulating layers are provided on a lower electrode by printing, and the upper electrode formed on the insulating layer and the lower electrode are electrically connected through a via hole provided in the insulating layer. A printed multilayer board, characterized in that the via holes provided in the insulating layer are formed in such a shape that the via holes in the upper insulating layer are larger toward the front side in the printing direction than the via holes in the lowest insulating layer.
JP4992386U 1986-04-03 1986-04-03 Expired JPH0427184Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4992386U JPH0427184Y2 (en) 1986-04-03 1986-04-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4992386U JPH0427184Y2 (en) 1986-04-03 1986-04-03

Publications (2)

Publication Number Publication Date
JPS62162875U JPS62162875U (en) 1987-10-16
JPH0427184Y2 true JPH0427184Y2 (en) 1992-06-30

Family

ID=30872821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4992386U Expired JPH0427184Y2 (en) 1986-04-03 1986-04-03

Country Status (1)

Country Link
JP (1) JPH0427184Y2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9269593B2 (en) * 2012-05-29 2016-02-23 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Multilayer electronic structure with integral stepped stacked structures
US9161461B2 (en) * 2012-06-14 2015-10-13 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Multilayer electronic structure with stepped holes

Also Published As

Publication number Publication date
JPS62162875U (en) 1987-10-16

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