JPH04270975A - Ic testing device - Google Patents

Abstract

PURPOSE:To achieve a high-resolution and high-accuracy duty ratio measurement by prescribing a signal reading time according to a least common multiple between a period of a signal to be measured and that of a signal to be read and then reading signal by a reading count which is prescribed by this time. CONSTITUTION:A period X of a signal to be measured Pa is set to a period- setting means SET2 and a period T of a strobe pulse Pb which is given to a signal-reading circuit R is set to a reading period setting means SET1, thus enabling a timing generator TG to obtain a least common multiple. With this M as a period, a same point of the signal Pa is punched by a pulse Pb for reading. Further, a signal-reading count P within M can be obtained from a ratio P=M/T. An expectation value, for example 0 logic, is compared with the reading signal logically by a logic comparator LC, thus enabling conformity and non-conformity to be detected. A nonconformity counter FCNT counts a generation count (a count where logic 1 section of the signal Pa is punched) PF. A duty ratio D of the signal Pa can be calculated according to D=PF/P.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention is an IC with a built-in oscillator.
The present invention relates to an IC testing device having a function of testing whether the oscillation output waveform of an oscillator is normal or not.

0002

2. Description of the Related Art For example, in an IC such as a memory, a test is performed by writing a test pattern signal into the memory and checking whether the readout output is normal or not. On the other hand, an IC with a built-in microcomputer has a built-in clock oscillator to generate an operating clock. In addition to testing whether various functions including microcomputers operate normally, we also test whether the waveform of the clock pulse output by the clock oscillator, that is, the duty ratio of the clock pulse, is within an acceptable range of, for example, close to 50%. It is required to test whether it is present or not.

Conventionally, the duty ratio of a clock pulse output from an IC under test has been measured using the function of a signal acquisition circuit of an IC tester. In other words, as shown in FIG.
The output terminal of the IC under test 1 is connected to the input terminal of a signal capture circuit R that captures the response output signal of the IC under test 1. A three-state amplifier is used for the driver D, and at the timing when the signal acquisition circuit R takes in the response output of the IC under test 1, the output terminal of the driver D is controlled to a high impedance, and the driver D is substantially connected to the IC under test 1. It is in a state where it is disconnected from the load, and in this state, the signal capture circuit R captures the signal output by the IC under test 1.

The signal acquisition circuit R uses a strobe amplifier. As is well known, a strobe amplifier reads the logic state of an input signal at the timing of supply of a strobe pulse. Therefore, in the past, the supply timing of the strobe pulse was sequentially delayed by a fixed amount of time for each cycle of the signal under test, and the time from the start of the cycle of the signal under test to the logic change point was measured, and by measuring this time, I am looking for the duty ratio of the signal under test.

The situation will be explained using FIG. 4. Figure 4A
indicates the signal under measurement Pa. This signal Pa is the IC1 under test.
This is the clock pulse output from Measured signal Pa
One period X is given as a known value by, for example, the resonant frequency of the oscillation element incorporated in the IC 1 under test. Here, if the half cycle XX for one cycle X can be measured, the duty ratio D can be obtained as D=XX/X.

FIG. 4B shows strobe pulses applied to the strobe amplifier constituting the signal acquisition circuit R. The strobe pulse Pb is given to the signal acquisition circuit R by adding a delay amount of Δt sequentially from the reference timing RS every cycle of the signal under measurement Pa by a variable delay circuit. The signal acquisition circuit R reads the logic of the signal under test Pa at the timing when the strobe pulse Pb is supplied. Therefore, in the illustrated example, "1" logic is read from the beginning to the fourth strobe pulse, but "0" logic is read at the fifth strobe pulse, as shown in FIG. 4C. Therefore, the half period XX to be measured is XX=4·Δt in this example. Δt
For example, if Δt=100ps (picoseconds), then XX=
It becomes 400ps. In reality, X is 40ns (nanoseconds)
Therefore, if Δt=100 PS, the number of times the strobe pulse Pb scans one period X of the signal under measurement Pa is 40×10 −9/100×10 −12 =400 times. Therefore, the time is 400×=16000 ns.

Although there are various devices for measuring the duty ratio of a signal, since the signal to be measured is output from an IC, it is convenient if the duty ratio can be measured by an IC testing device. In other words, when using a measuring device other than an IC testing device, the IC under test must be connected to and disconnected from the measuring device. Furthermore, installation of other measuring instruments takes up space and is inconvenient, such as requiring a large room.

[0008]

[Problems to be Solved by the Invention] Conventionally, the supply timing of the strobe pulse Pb is sequentially delayed and supplied, and the phase position of the strobe pulse Pb is changed, so that the signal under measurement P
The half period XX of the signal under test Pa is determined by scanning one cycle of the signal under test a with the strobe pulse Pb and counting the number of strobe pulses supplied until the logic of the signal under test Pa changes. If one period of the signal under test Pa is 40 ns and the amount of increase in the delay time of the strobe pulse Pb Δt is 100 ps, the time to measure one period of the signal under test Pa is 16
000 ns, which has the disadvantage that the time required for the test becomes longer.

[0009] Also, if Δt = 100 ps, the half period
The resolution for measuring X is 100 ps. In other words, since the resolution is coarse, the measurement accuracy is poor. SUMMARY OF THE INVENTION An object of the present invention is to provide an IC testing device that has a fine resolution for detecting a logic reversal of a signal under test and can shorten the time required for measurement.

0010

[Means for Solving the Problems] In the present invention, the number of times the signal acquisition circuit acquires a signal is determined by the least common multiple of the period X of the signal under test and the signal acquisition period T of the signal acquisition circuit. A signal acquisition time is defined, and the logic at each timing position of the signal under test is acquired the number of times of signal acquisition defined by this signal acquisition time.

[0011] When acquiring a signal for the number of signal acquisitions determined by the ratio of the least common multiple of period Captured data can be obtained that is equivalent to sampling with a resolution equal to one of the number of signal captures. The structure is configured to compare this captured data with an expected value having a certain logic, and calculate the duty ratio of the signal under test from the ratio of the number of matches or mismatches obtained as a result of the comparison and the number of times of signal capture. We propose a new IC testing device.

According to the configuration of the present invention, by finding the least common multiple of the period to be measured and the signal acquisition period of the signal acquisition circuit, this least common multiple allows the signal to be measured to be acquired at the same timing position. The period is an integral multiple of the signal acquisition period. Therefore, the required number of signal acquisition times can be determined by dividing this integer multiple period by the signal acquisition period of the signal acquisition circuit. Therefore, by capturing each timing position of the signal under test using the signal acquisition circuit this number of times, all the data for calculating the duty ratio can be obtained, and the data for calculating the duty ratio can be obtained in a short time. can. When using this duty ratio measurement method, the period of the signal under test Pa is X, and the signal acquisition period of the signal acquisition circuit is T.
In this case, a restriction of X/2<T<X is given between the period T and X.

However, the measurement resolution is the value obtained by dividing the period of the signal under measurement by the number of times of signal acquisition. This value is a sufficiently small value, and it is possible to measure the duty ratio with high resolution. Furthermore, since the measurement accuracy is the value obtained by dividing the resolution by the period of the signal under measurement, the value is also a small value. Therefore, it is possible to measure the duty ratio with high resolution and accuracy.

[0014]

[Embodiment] FIG. 1 shows an embodiment of the present invention. In FIG. 1, 1 indicates an IC to be tested, and 10 indicates an IC testing device. IC
The test device 10 includes a timing generator TG, a pattern generator PG that generates a test pattern signal and an expected value pattern signal based on a timing signal output from the timing generator TG, and a pattern generator PG and a logic comparator L.
The test head TH is interposed between the IC 1 and the IC 1 to be tested, and electrically connects the IC 1 to the pattern generator PG and the logic comparator LC. The driver D and signal acquisition circuit R described above are mounted on the test head TH.

[0015] The IC test apparatus composed of the timing generator TG, pattern generator PG, test head TH, and logic comparator LC has the same structure as a conventional IC test apparatus. The feature of the present invention is that the timing generator TG includes an acquisition period setting means SET1 for variably setting the signal acquisition period of the signal acquisition circuit R, and a period X of the signal under measurement.
A period setting means SET2 for setting the period setting means SET2 is attached, and
The point is that a discrepancy counter FCNT is provided on the output side of the logic comparator LC to count the number of times discrepancies occur.

The period X of the signal under test is given by the standard of the oscillator built into the IC 1 under test. This period X is set in advance in the period setting means SET2, and the period T of the strobe pulse Pb (FIG. 2C) applied to the signal acquisition circuit R is set in the acquisition period setting means SET1. By setting these periods X and T in the setting means SET1 and SET2, the timing generator TG determines the least common multiple M thereof. For example, the period X is X=41.67ns (24
．． 0MHz), and the period T is T=53.0ns (18.87
MHz), the timing generator TG calculates the least common multiple M by M=X·T, and calculates M=6625 ns. This least common multiple M means the required signal acquisition time.

In other words, the least common multiple M (time) is the signal under measurement Pa at the timing of the first signal acquisition (FIG. 2A)
This means that the signal acquisition position coincides with the signal acquisition position acquired after M (time), and the strobe pulse P
It will be punched out and taken in by b. Further, from the ratio P=M/T of the least common multiple M and the signal acquisition period T, the number of times P of signal acquisition during the least common multiple M (time) can be obtained.

Therefore, by applying P strobe pulses Pb to the signal acquisition circuit R, it is possible to obtain data acquired P times from the same point of the signal under measurement Pa determined by the least common multiple to the same point. . According to the above numerical example, the number of times P of signal acquisition is P=125. Therefore, in this example, by sending out 125 strobe pulses Pb and obtaining 125 points of acquisition signals,
A captured signal substantially equivalent to sampling one period of the signal under measurement Pa at a resolution of 1/125 can be obtained.

This input signal is passed to a logic comparator LC with a certain logic, for example, "0" logic, as the expected value, and this "0"
A logical comparison is made between the expected logical value and the captured signal, and a match or mismatch is detected. For example, every time a mismatch is detected in the logical comparator LC, a mismatch counter FCNT counts the number of times a mismatch occurs. This mismatch count value indicates the number of times the "1" logic section of the signal under measurement Pa is punched out. When the number of mismatch detections is PF, the duty ratio D of the signal under measurement Pa can be determined as D=PF/P (P is the total number of times the signal is captured).

According to this method of measuring the duty ratio, the resolution U of the duty ratio D is U=X(ns)/P. Therefore, in the case of the above example, U=41.67(ns)/1
25=0.333 (ns). Furthermore, the duty ratio D
The measurement accuracy S is determined by S=U/X. According to the example, S=0.333/41.67≒0.008, and 0
．． This results in an error of 8%.

[0021]

[Effects of the Invention] As explained above, according to the present invention, signals are acquired by an integral multiple P of the period T, which is determined by dividing the least common multiple M of the period X and the period T by the signal acquisition period T. Therefore, one period X of the signal under test Pa is reduced to 1/P
It is possible to obtain captured data equivalent to sampling with a resolution of . Since P is smaller than the number of times of conventional signal acquisition, data acquisition can be completed in a short time.

Moreover, since the resolution is high and the measurement accuracy is also high, the duty ratio can be measured with high accuracy in a short time, which is an advantage. Furthermore, since the duty ratio can be measured using only the IC test device, there is no need to use any other measuring device. Therefore, in this respect, the economic burden and the occupied area can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the present invention.

FIG. 3 is a block diagram for explaining a conventional technique.

FIG. 4 is a waveform diagram for explaining the operation of the conventional technology.

[Explanation of symbols]

1 IC to be measured 10 IC test equipment TG timing generator PG pattern generator LC logic comparator TH Test head FCNT　　　　Discrepancy Counter

Claims (1)

[Claims] [Claim 1] The logic signal output from the IC under test is captured by a signal capture circuit, and the captured logic value is compared with an expected value, and by detecting a mismatch, the IC under test is determined to be defective. In the IC test equipment, the IC under test has a built-in oscillator, and the clock pulse output from this oscillator is taken out as the signal under test to the outside of the IC under test, and the period The signal acquisition time is defined by the least common multiple of the signal acquisition period T of the circuit, and the acquired data acquired within this signal acquisition time is logically compared with an expected value having a certain logical value. An IC testing device configured to determine the duty ratio of the clock pulse based on the ratio between the number of matches or mismatches obtained as a result of logical comparison and the number of data acquired within the signal acquisition time.