JPH04270527A - Packet information counter - Google Patents

Abstract

PURPOSE:To reduce the circuit scale and to improve the system expansion by storing statistic information required for network management into a memory. CONSTITUTION:Statistic information being summation of packet information such as a CRC error and a clock error for each port is stored in a dual port RAM 22. When a collision of a packet is detected by a collision detection circuit 15, a collision number data in the statistic information in the RAM 22 is revised by an adder 24. At non-collision, since a reception packet is only one, it is selected by a multiplexer 12 and fed to one packet information detector 16. The adder 24 rewrites the relevant statistic information in the RAM 22 based on the packet information such as various error information detected by the packet information detector 16.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] This invention is applicable to, for example, CSMA/C
D (Carrier Sense Multiple
Access/Collision Detection
n ) local area network (LAN)
) to connect multiple cable segments to each other.
The present invention relates to a packet information counter that is used in a multi-port repeater, etc., and accumulates statistical information of each port required for network management.

0002

[Prior Art] Multi-port repeaters used in CSMA/CD type LANs are designed to transmit packets between multiple cable segments without any problems, such as determining appropriate retransmission timing when a collision is detected. , it is necessary to accumulate the reception status of the ports to which each segment is connected as statistical information. This statistical information is
For example, number of packet collisions, number of normal packets received, CR
There is error information such as the number of C errors, the number of packet length errors, and the number of reception clock errors, and these are sequentially accumulated in a packet information counter.

FIG. 3 is a block diagram showing a schematic configuration of a conventional packet information counter 1. As shown in FIG. Each segment 21,
22,...,2N to ports P1, P2,...,P
The packets input via N are input to packet information detectors 31 , 32 , . . . , 3N , respectively, and are also input to collision detection circuit 4 . The packet information detectors 31 to 3N detect packet information such as a CRC error, a packet length error, and a reception clock error from each received packet. Further, the collision detection circuit 4 detects packet collisions at each port and controls the operations of the packet information detectors 31 to 3N. On the output side of the packet information detectors 31 to 3N, there are counter groups 51, 5 for detecting statistical information.
2,...,5N are installed. Each counter group 51
~5N are normal packet counters 61 and CR, respectively.
C error counter 62, RUNT packet counter 6
3, a clock error counter 6M, etc., each of which stores various kinds of packet information.

[0004] In the packet information counter configured as described above, when a packet is correctly received at any one of ports P1 to PN,
The normal packet counter 61 of the corresponding port number is counted up, and when data collides or some kind of error occurs in the received packet, the corresponding counter 6i of the corresponding port is counted up, and statistical information is accumulated sequentially. will be done.

[0005]

[Problems to be Solved by the Invention] However, in the conventional packet information counter described above, it is necessary to provide a plurality of counters to accumulate the necessary packet information for each port. When the number of types of statistical information to be accumulated is M, N×M counters must be provided. For this reason, when the number of ports and the number of packet information increases, the number of counters increases and the number of wiring for inputting and outputting each counter increases, resulting in a problem that the circuit scale becomes large. In addition, with conventional packet information counters, when the number of ports to be connected and the types of statistical information increase, it is necessary to add new counters, so there is also the problem that the system lacks expandability and flexibility.

The present invention has been made to solve these conventional problems, and provides a packet information counter that can reduce the circuit scale and has excellent system expandability and flexibility. With the goal.

[0007]

[Means for Solving the Problems] A packet information counter according to the present invention includes a memory for storing statistical information that accumulates packet information such as various error information of packets received from a plurality of ports, and a a collision detection means for detecting a collision of packets; a packet information detection means for detecting the packet information of the packet received from each port; and a reception port encoder for outputting a reception port number specifying the port on which the packet was received. and statistical information updating means for selectively rewriting the necessary statistical information in the memory based on the output of the collision detecting means, the detected packet information, and the receiving port number. It is characterized by

[0008]

[Operation] Various packet information is treated as valid information when there is no packet collision, so the packet information to be accumulated is always obtained when one packet is received from only one port. This is the case. Therefore, statistical information about multiple ports will not be rewritten at the same time. The present invention focuses on this point,
Statistical information for each port is stored in memory, and necessary statistical information in the memory is selectively rewritten by statistical information updating means based on the output of collision detection means, receiving port number, and packet information. . Therefore, according to the present invention, since a large number of counters are not required as in the conventional case, the circuit configuration and input/output wiring can be simplified, and the circuit scale can be reduced. Further, according to the present invention, even if the number of ports and the type of statistical information are changed, this can be handled simply by changing the address, making it easy to expand the system.

Note that since packet information is obtained only when a packet is received by one port, only one packet information detection means for each port is used at the same time. Therefore, by sharing this packet information detection means, the circuit scale can be further reduced. Furthermore, using a dual port memory as the memory has the advantage that statistical information can be read out at the required timing, making network management easier.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS A packet information counter according to an embodiment of the present invention will be described below with reference to the accompanying drawings. Figure 1
1 is a block diagram showing the configuration of a packet information counter 11 according to the present embodiment. This packet information counter 11
is a plurality of segments 21 , 22 , 23 ,...,2
It is built into a multi-port repeater that relays data on N ports to each other. Packets input from each segment 21 to 2N via ports P1, P2, P3, . The multiplexer 12 selects the port corresponding to the reception port number detected by the reception carrier detection circuit 13. The received packet of the selected port is input to the packet information detector 16. The packet information detector 16 sequentially detects packet information included in the selected received packet.

The received carrier detection circuit 13 detects that a station other than this repeater has transmitted a carrier to each segment 21 to 2N. This received carrier detection circuit 1
The detection result No. 3 is latched by the latch circuit 17. The latch circuit 17 latches the reception carrier that becomes active during one reception operation, that is, after the reception carrier of any one port becomes active until all the reception carriers become inactive. When the reception port encoder 14 detects a carrier from only one port, it encodes the port number into a port address of n1 bits (2n1≧1). The collision detection circuit 15 includes ports P1 to PN.
Detecting that a collision has occurred on at least one port. The output of the collision detection circuit 15 is input to the control circuit 18.

The multiplexer 19 sequentially switches the packet information output from the packet information detector 16 based on the output of the control circuit 18. Further, the multiplexer 20 switches the received carrier latched by the latch circuit 17 for each port. The outputs of multiplexers 19 and 20 are input to multiplexer 21. The multiplexer 21 selects the output of the multiplexer 20 when the collision detection circuit 15 detects a collision, and selects the output of the multiplexer 19 when the collision detection circuit 15 does not detect a collision.

The packet information counter 11 is also provided with a dual port RAM 22 for accumulating statistical information such as CRC errors and packet length errors. FIG. 2 is a schematic diagram showing statistical information stored in this dual port RAM 22. As shown in this figure, the storage area of the dual port RAM 22 is divided by port, and each storage area stores statistical information such as a normal packet count value, a CRC error count value, a packet length error count value, and the number of collisions. It is now possible to do so. Assuming that the number of ports is N and the type of statistical information for each port is M, N×M pieces of statistical information are stored in this dual port RAM 22.

This dual port RAM 22 can be accessed by the adder 24 and a CPU (not shown), respectively. The dual port RAM 22 is given an n2-bit address from the address generation circuit 23. Address generation circuit 23 determines an address based on the output from control circuit 18 and the output from reception port encoder 14 . n read from dual port RAM 22
The 3-bit statistical information is added to the output of the multiplexer 21 by an adder 24, and is written to the same address again. In this way, the control circuit 18
, multiplexer 21, address generation circuit 23, and adder 24 constitute statistical information updating means for updating the contents stored in dual port RAM 22.

Next, the operation of the packet information counter 11 according to this embodiment configured as described above will be explained. First, at the time of initial setting, the dual port RA is set by the CPU.
0 is written to all addresses of M22, and the statistical information is cleared. The packet information counter 11 performs a series of operations when one reception operation is completed. Here, one reception operation is an operation from when the reception carrier of any one port becomes active until the reception carriers of all ports become inactive.

If a packet collision occurs during reception, the collision detection circuit 15 detects this, switches the multiplexer 21 to the multiplexer 20 side, and updates the number of collisions. That is, the control circuit 18
is controlled to select the received carrier of each port in order, and also controls the address generation circuit 23 to sequentially read out the collision count data of each port stored in the dual port RAM 22 to the adder 24. For ports where the receiving carrier is active, the adder 24 adds 1 to the read collision count data and adds it to the dual port RA.
Write to M22. This allows the data on the number of collisions to be updated.

If no packet collision occurs during reception, the multiplexer 21 sends the multiplexer 19
Select the output of and update various statistical information of received packets. That is, the control circuit 18 controls the multiplexer 19 to sequentially search for packet information such as CRC errors and clock errors detected by the packet information detector 16, and also sends information indicating the type of statistical information to the address generation circuit 2.
Output to 3. Further, the address generation circuit 23 is supplied with the reception port number from the reception port encoder 14 . The address generation circuit 23 outputs an address determined based on the receiving port number and the type of statistical information to the dual port RAM 22. As a result, each piece of statistical information of the receiving port is sequentially read out from the RAM 22 to the adder 24. When the information bit of the relevant statistical information output from the multiplexer 19 is 1, the adder 24 increments the read statistical information and adds it to the dual port RA.
Write to M22. This rewrites the statistical information of the receiving port.

The statistical information updated in this way is sent to the CPU from the other port of the dual port RAM 22.
is read by

As described above, according to the packet information counter 11 according to the present embodiment, the statistical information of each port is stored in the dual port RAM 22, so that when a large number of counters are used as in the conventional case, Compared to the above, the circuit configuration and input/output wiring can be simplified, the circuit scale can be reduced, and the flexibility for system expansion can be improved. Furthermore, in this embodiment, since the packet information detector 16 is shared by each port based on the fact that only one packet is received during normal reception, the circuit scale can be further reduced.

Note that the memory for storing statistical information is not particularly limited to dual-port RAM, but if dual-port RAM is used as in this embodiment, access from the CPU side becomes easier. This has the advantage that the waiting time when the CPU accesses the memory can be reduced.

[0021]

As described above, according to the present invention, the statistical information of each port is stored in the memory, so the circuit configuration and input The output wiring can be simplified and the circuit scale can be significantly reduced. Furthermore, according to the present invention, by using memory to store statistical information, even when changing the number of ports, the type of statistical information, etc., it is only necessary to change the address designation, which improves system expandability and flexibility. It has the effect of improving sexual performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a packet information counter according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing data stored in a dual port RAM in the same packet information counter.

FIG. 3 is a block diagram of a conventional packet information counter.

[Explanation of symbols]

1, 11...Packet information counter, 21 ~ 2N
... Segment, 31 to 3N, 16... Packet information detector, 4, 15... Collision detection circuit, 51 to 5N... Counter group, 12, 19 to 21... Multiplexer, 13... Reception carrier detection circuit, 14... Reception port encoder, 1
7...Latch circuit, 18...Control circuit, 22...Dual port RAM, 23...Address generation circuit, 24...Adder.

Claims (3)

[Claims] 1. A memory for storing statistical information that accumulates packet information such as various error information of packets received from a plurality of ports, collision detection means for detecting a collision of packets at each of the ports, and a collision detection means for detecting a collision of packets at each of the ports, packet information detecting means for detecting the packet information of a packet received from a port; receiving port encoding means for outputting a receiving port number specifying the port on which the packet was received; and an output of the collision detecting means; and statistical information updating means for selectively rewriting the necessary statistical information in the memory based on the received packet information and the receiving port number. 2. The apparatus further comprises a selection means for selecting a port that has received a packet from among the plurality of ports, and by selecting a receiving port with the selection means, it can be determined that the packet information detection means is shared among the plurality of ports. The packet information counter according to claim 1. 3. The packet information according to claim 1, wherein the memory is a dual port memory capable of updating the statistical information and reading the statistical information from different ports. counter.