JPH0426992A - Battery circuit for semiconductor memory device - Google Patents

Battery circuit for semiconductor memory device

Info

Publication number
JPH0426992A
JPH0426992A JP2131245A JP13124590A JPH0426992A JP H0426992 A JPH0426992 A JP H0426992A JP 2131245 A JP2131245 A JP 2131245A JP 13124590 A JP13124590 A JP 13124590A JP H0426992 A JPH0426992 A JP H0426992A
Authority
JP
Japan
Prior art keywords
light emitting
current
resistor
primary battery
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2131245A
Other languages
Japanese (ja)
Inventor
Masatoshi Kimura
正俊 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2131245A priority Critical patent/JPH0426992A/en
Publication of JPH0426992A publication Critical patent/JPH0426992A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To inform it to an external device that a counter charge prevention diode of a primary battery is destroyed or short-circuited by connecting a series connection comprising a counter charge prevention diode, a current limit resistor and a backup primary battery in parallel with a semiconductor memory element and providing a light emitting element and a resistor in parallel with the current limit resistor. CONSTITUTION:When counter charge prevention diode 4 is destroyed or short- circuited, a power supply from a terminal equipment is fed to a primary battery 2 via current limit resistors 3, 6 and a light emitting diode 7 to counter-charge the battery 2. That is, the primary battery 2 is counter-charged by a current being the sum of a current Ia flowing to the current limit resistor 3 and a current Ib flowing to the current limit resistor 6 and the light emitting diode 7. Since the current Ib is enough to light up the light emitting diode 7, the light emitting diode 7 is lighted. The current flowing thereat is limited by the resistor 6. Thus, the user recognizes it that the counter charge prevention diode 4 is destroyed resulting in short-circuit.

Description

【発明の詳細な説明】 [産業上の利用分野コ この発明は、半導体配憶装置の電池回路に間し、特に使
用されている電池の保護機能を有する携帯形半導体記憶
装置の電池回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a battery circuit of a semiconductor storage device, and particularly relates to a battery circuit of a portable semiconductor storage device having a protection function for the battery used. It is.

[従来の技術] 第3図は従来の半導体記憶装置の電池回路を示す構成図
である0図において、(1)は半導体記憶素子としての
例えばスタティックRAM等からなる不揮発性メモリ、
(2)は端末機(図示せず)から入力電源がないときに
電源を不揮発性メモリ(1)に供給する例えばリチウム
電池を用いた1次電池、(3)は電流制限用抵抗器、(
4)は逆充電防止用ダイオードであって、これらの1次
電池(2)、抵抗器(3)及びダイオード(4)は直列
接続され、不揮発性メモリ(1)と並列に設けられてい
る。(5)は逆流防止用ダイオードである。
[Prior Art] FIG. 3 is a block diagram showing a battery circuit of a conventional semiconductor memory device. In FIG.
(2) is a primary battery such as a lithium battery that supplies power to the nonvolatile memory (1) when there is no input power from the terminal (not shown); (3) is a current limiting resistor;
4) is a reverse charge prevention diode, and these primary battery (2), resistor (3), and diode (4) are connected in series, and are provided in parallel with the nonvolatile memory (1). (5) is a backflow prevention diode.

次に、第3図に示した従来の半導体記憶装置の電池回路
の動作について説明する。端末機から入力電源が不揮発
性メモリ(1)に供給されると、端末機は不揮発性メモ
リ(1)とインタフェイス信号を用いてリード/ライト
動作が可能である。
Next, the operation of the battery circuit of the conventional semiconductor memory device shown in FIG. 3 will be explained. When input power is supplied from the terminal to the non-volatile memory (1), the terminal can perform read/write operations using the non-volatile memory (1) and interface signals.

一般的に端末機の電源電圧は例えば5V、1次電池(2
)の電圧は例えば3Vである。従って、このときダイオ
ード(4)の作用のため1次電池(2)の電流は流れる
ことはないので、1次電池(4)は電力を消耗しない、
今、端末機がら電源入力がないときは、1次電池(2)
の電圧が抵抗器(3)及びダイオード(4)を介して不
揮発性メモリ(1)に供給されるため、不揮発性メモリ
(1)の記憶データは保持される。
Generally, the power supply voltage of the terminal is 5V, for example, and the primary battery (2
) is, for example, 3V. Therefore, at this time, no current flows through the primary battery (2) due to the action of the diode (4), so the primary battery (4) does not consume power.
If there is no power input from the terminal, use the primary battery (2)
Since the voltage is supplied to the nonvolatile memory (1) via the resistor (3) and the diode (4), the data stored in the nonvolatile memory (1) is retained.

次に何等かの原因、例えば外来ノイズ等でダイオード(
4)がが破壊し、短絡した場合を考える。
Next, due to some reason, such as external noise, the diode (
4) Consider the case where is destroyed and short-circuited.

この状態で端末機から電源が入力されると、ダイオード
(4)が短絡しているため、抵抗器(3)を介して1次
電池(2)を逆充電する。1次電池(2)は逆充電する
と液漏れ等破壊するため、場合によっては大きな障害を
発生する恐れがあり、絶対に逆充電を避ける必要がある
。そうしないと、1次電池(2)の機能は失われ、不揮
発性メモリ(1)のバックアップ電源としての作用は出
来なくなる。
When power is input from the terminal in this state, the primary battery (2) is reversely charged via the resistor (3) because the diode (4) is short-circuited. If the primary battery (2) is reversely charged, it will be destroyed due to liquid leakage, etc., which may cause major problems depending on the case, so reverse charging must be avoided at all costs. Otherwise, the function of the primary battery (2) will be lost and the non-volatile memory (1) will no longer be able to function as a backup power source.

[発明が解決しようとする課題] 従来の半導体記憶装置の電池回路は以上のように、ダイ
オード(4)が破壊し、短絡した場合端末機からの電源
は抵抗器(3)を介し1次電池(2)を逆充電するので
、この状態が長期間続行すると1次電池(2)の液漏れ
等の悪影響を来し、もって1次電池(2)による不揮発
性メモリ(1)のバックアップは不可能になり、また、
ダイオード(4)が短絡したことが分からないという問
題点があった。
[Problems to be Solved by the Invention] As described above, in the battery circuit of a conventional semiconductor storage device, if the diode (4) breaks down and short-circuits, the power from the terminal device is transferred to the primary battery via the resistor (3). (2) is reversely charged, so if this state continues for a long period of time, there will be negative effects such as leakage of the primary battery (2), and the backup of the non-volatile memory (1) by the primary battery (2) will become permanent. It becomes possible, and
There was a problem in that it was not obvious that the diode (4) was short-circuited.

この発明は上記のような問題点を解決するためになされ
たもので、逆充電防止用ダイオードが短絡したことを表
示すると共に半導体記憶装置の外部から分かるようにす
る半導体記憶装置の電池回路を得ることを目的とする。
This invention has been made to solve the above-mentioned problems, and provides a battery circuit for a semiconductor storage device that displays a short-circuit in a reverse charge prevention diode and makes it visible from the outside of the semiconductor storage device. The purpose is to

[課題を解決するための手段] この発明に係る半導体記憶装置の電池回路は、半導体記
憶素子と並列に逆充電防止用ダイオード、電流制限用抵
抗器及びバックアップ用1次電池を直列接続し、上記電
流制限用抵抗器と並列に発光素子と抵抗器を設けたもの
である。
[Means for Solving the Problems] A battery circuit for a semiconductor memory device according to the present invention includes a semiconductor memory element, a reverse charging prevention diode, a current limiting resistor, and a backup primary battery connected in series in parallel with the semiconductor memory element. A light emitting element and a resistor are provided in parallel with a current limiting resistor.

[作用] この発明においては、電流制限用抵抗器と並列に発光素
子を設け、逆充電防止用ダイオードが破壊、短絡した場
合発光素子を発光させて外部に知らせる。
[Function] In the present invention, a light emitting element is provided in parallel with the current limiting resistor, and when the reverse charging prevention diode is broken or short-circuited, the light emitting element emits light to inform the outside.

[実施例] 第1図はこの発明の一実施例を示す構成図であり、(1
)〜(5)は前述と同様のものである。
[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention.
) to (5) are the same as described above.

本実施例では電流制限用抵抗器(3)と並列に電流制限
用抵抗器(6)及び発光素子例えば発光ダイオード(7
)を接続する。
In this embodiment, a current limiting resistor (6) and a light emitting element such as a light emitting diode (7) are connected in parallel with the current limiting resistor (3).
) to connect.

次に、第1図に示したこの発明の一実施例の動作につい
て説明する。今、端末機から電源入力がないとき、不揮
発性メモリ(1)には1次電池(2)の電圧が電流制限
用抵抗器(3)及び逆充電防止用ダイオード(4)を介
して供給される。発光ダイオード(7)は電流が流れる
方向と逆に挿入されているため、電流が流れる事はない
。したがって、発光ダイオード(7)は発光することは
なく、消灯している0次に端末機から電源が供給された
場合、逆充電防止用ダイオード(4)が正常のときは従
来と同一の作用を行う。
Next, the operation of the embodiment of the present invention shown in FIG. 1 will be explained. Now, when there is no power input from the terminal, the voltage of the primary battery (2) is supplied to the nonvolatile memory (1) via the current limiting resistor (3) and the reverse charge prevention diode (4). Ru. Since the light emitting diode (7) is inserted in the opposite direction to the current flow direction, no current flows. Therefore, the light emitting diode (7) does not emit light, and when power is supplied from the zero-order terminal that is turned off, the reverse charging prevention diode (4) functions as before when it is normal. conduct.

ここで、今、逆充電防止用ダイオード(4)が破壊し、
短絡した場合は、端末機からの電源は電流制限用抵抗器
(3)及び電流制限用抵抗器(6)、発光ダイオード(
7)を介し1次電池(2)に供給されて、これを逆充電
する。即ち、1次電池(2)は電流制限用抵抗器(3)
を流れる電流Iaと電流制限用抵抗器(6)及び発光ダ
イオード(7)を流れる電流Ibの和の電流で逆充電さ
れる。電流Ibは発光ダイオード(7)が発光するに十
分な値であるため、発光ダイオード(7)は発光する。
Now, the reverse charging prevention diode (4) is destroyed,
In the event of a short circuit, the power from the terminal device is connected to the current limiting resistor (3), the current limiting resistor (6), and the light emitting diode (
7) to the primary battery (2) to reverse charge it. That is, the primary battery (2) is connected to the current limiting resistor (3).
It is reversely charged by the sum of the current Ia flowing through the current limiting resistor (6) and the current Ib flowing through the current limiting resistor (6) and the light emitting diode (7). Since the current Ib has a value sufficient for the light emitting diode (7) to emit light, the light emitting diode (7) emits light.

このとき流れる電流は抵抗器(6)で制限される。した
がって、使用者はこの発光ダイオード(7)が点灯した
場合は逆充電防止用ダイオード(4)が破壊し、短絡し
た事を知ることが出来る。そこで使用者は直ちにこの半
導体記憶装置の使用を禁止する。
The current flowing at this time is limited by the resistor (6). Therefore, when the light emitting diode (7) lights up, the user can know that the reverse charging prevention diode (4) has been destroyed and a short circuit has occurred. Therefore, the user immediately prohibits the use of this semiconductor storage device.

第2図は発光ダイオード(7)の実装場所の例を示すも
ので、第2図(a>はその平面図、第2図(b)はその
側面図である。第2図(a)において、く8)は半導体
記憶装置、(9)は端末機に対するコネクタ部である。
Fig. 2 shows an example of the mounting location of the light emitting diode (7), Fig. 2 (a) is its plan view, and Fig. 2 (b) is its side view. In Fig. 2 (a) , 8) is a semiconductor memory device, and (9) is a connector for a terminal.

発光ダイオード(7)はコネクタ部(9)の反対側の下
部側面に第2図(b)のように設けられる。
The light emitting diode (7) is provided on the lower side opposite to the connector part (9) as shown in FIG. 2(b).

尚、上記実施例では発光ダイオード(7)の取り付は位
置を側面としたが表裏面上に実装してもよい。また、逆
充電防止用ダイオード(4)のアノード側に得られる信
号を半導体記憶装置から端末機に出し、端末機側に電流
制限用抵抗器(6)及び発光ダイオード(7)を設けて
もよく、この場合も上記実施例と同様の効果を奏する。
In the above embodiment, the light emitting diode (7) was mounted on the side surface, but it may be mounted on the front and back surfaces. Alternatively, a signal obtained from the anode side of the reverse charging prevention diode (4) may be sent from the semiconductor storage device to the terminal device, and a current limiting resistor (6) and a light emitting diode (7) may be provided on the terminal device side. In this case as well, the same effects as in the above embodiment can be achieved.

[発明の効果コ 以上のようにこの発明によれば、半導体記憶素子と主列
に逆充電防止用ダイオード、電流制限用抵抗器及びバッ
クアップ用1次電池を直列接続し、上記電流制限用抵抗
器と並列に発光素子と抵抗器を設けたので、1次電池の
逆充電防止用ダイオードが破壊し、短絡したことを容易
に外部に知らせることが出来、安全性、信頼性の高い半
導体記憶装置の電池回路が得られる効果がある。
[Effects of the Invention] As described above, according to the present invention, a reverse charging prevention diode, a current limiting resistor, and a backup primary battery are connected in series to the semiconductor memory element and the main column, and the current limiting resistor is Since a light emitting element and a resistor are installed in parallel with the primary battery, it is possible to easily notify the outside that the reverse charging prevention diode of the primary battery has been destroyed and a short circuit has occurred, resulting in a highly safe and reliable semiconductor memory device. This has the effect of providing a battery circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を示す構成図、第2図はこ
の発明の実装例を示す平面図及び側面図、第3図は従来
の半導体記憶装置の電池回路を示す構成図である。 図において、(1)は不揮発性メモリ、(2)は1次電
池、(3)、(6)は電流制限用抵抗器、(4)は逆充
電防止用ダイオード、(7)は発光ダイオードである。 尚、各図中同一符号は同−又は相当部分を示す。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a plan view and side view showing a mounting example of the present invention, and FIG. 3 is a block diagram showing a battery circuit of a conventional semiconductor memory device. . In the figure, (1) is a non-volatile memory, (2) is a primary battery, (3) and (6) are current limiting resistors, (4) is a reverse charge prevention diode, and (7) is a light emitting diode. be. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】  半導体記憶素子と並列に逆充電防止用ダイオード、電
流制限用抵抗器及びバックアップ用1次電池を直列接続
し、 上記電流制限用抵抗器と並列に発光素子と抵抗器を設け
たことを特徴とする半導体記憶装置の電池回路。
[Claims] A reverse charging prevention diode, a current limiting resistor, and a backup primary battery are connected in series in parallel with a semiconductor memory element, and a light emitting element and a resistor are provided in parallel with the current limiting resistor. A battery circuit for a semiconductor storage device, characterized in that:
JP2131245A 1990-05-23 1990-05-23 Battery circuit for semiconductor memory device Pending JPH0426992A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2131245A JPH0426992A (en) 1990-05-23 1990-05-23 Battery circuit for semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2131245A JPH0426992A (en) 1990-05-23 1990-05-23 Battery circuit for semiconductor memory device

Publications (1)

Publication Number Publication Date
JPH0426992A true JPH0426992A (en) 1992-01-30

Family

ID=15053400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2131245A Pending JPH0426992A (en) 1990-05-23 1990-05-23 Battery circuit for semiconductor memory device

Country Status (1)

Country Link
JP (1) JPH0426992A (en)

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