JPH0426825A - Thin-film transistor array and production thereof - Google Patents

Abstract

PURPOSE:To lower the resistance value of gate wirings and to lessen the delay in switching operation by forming a gate bus and a drain bus on a semiconductor film and connecting the gate bus and a gate electrode as well as a drain electrode and the drain bus via a contact hole penetrated through a gate insulating film and the semiconductor film. CONSTITUTION:The gate electrode 4 and the drain bus 2 are formed on a substrate 26 and a picture element electrode 1 is formed. The gate insulating film 10 is formed on the gate electrode 4 and the semiconductor film 9 is laminated on this gate insulating film. Further, the gate bus 3, the drain electrode 5 and the source electrode 6 are provided on this semiconductor film 9. The gate bus 3 is connected via the contact hole 8 bored in the semiconductor film 9 and the gate insulating film 10. The drain electrode 5 is connected via the contact hole 8 bored in the semiconductor film 9 and the gate insulating film 10 to the drain bus 2. The resistance of the gate wiring is lowered in this way and the delay in the switching operation of the thin-film transistor is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a thin film transistor array provided in a liquid crystal display device or the like and a method for manufacturing the same.

"Prior Art" High melting point metal materials such as Cr, Ta, Ti, and Mo have been used as gate wiring materials for liquid crystal display devices since the beginning of their development. The reason for this is that the high melting point metal material has excellent adhesion to the underlying substrate, thermal stability, chemical stability, and processability.

FIGS. 7 and 8 are diagrams showing conventional thin film transistor arrays. A gate bus 21 and a drain bus 20 made of molybdenum or the like are provided on a glass substrate 26 so as to be perpendicular to each other with an insulating layer interposed therebetween. Further, a thin film transistor is provided near the intersection of the gate bus 21 and the drain bus 20. In the thin film transistor, a gate insulating film 24 made of silicon nitride or the like is provided on the gate electrode 25, a semiconductor film 23 made of hydrogenated amorphous silicon is provided on this gate insulating film, and a drain made of aluminum or the like is further provided on this semiconductor film 23. bus 2
A drain electrode 22 and a source electrode 19 are formed at the same time. The source electrode 19 is the semiconductor film 2
3 and a contact hole 7 made in the gate insulating film 24
It is connected to the pixel electrode l via a.

In the liquid crystal display device having the above structure, pixel display is performed by switching thin film transistors provided in each pixel. This switching operation is caused by the channel conductivity due to the field effect from the gate electrode 25, that is,
It is controlled by the current flowing between the source electrode 19 and the drain electrode 22.

"Problems to be Solved by the Invention" Recently, there has been a demand for liquid crystal display devices with large screens of 10 inches or more and high definition. However, especially in large-screen liquid crystal display devices, there is a problem in that when a scanning signal is applied to a certain gate electrode 25, a delay occurs in the switching operation of the thin film transistor due to the time constant of the resistance and capacitance of the gate bus 21 itself. be.

The present invention has been made to solve the above problems, and by reducing the resistance value of the gate wiring itself, it reduces the delay in the switching operation of the thin film transistor, and also improves the adhesion with the underlying substrate, thermal stability, The present invention aims to provide a thin film transistor array that not only has excellent chemical stability and processability but also has a gate bus and a drain bus that supply sufficient gate voltage and waveform to each pixel, and a method for manufacturing the same.

"Means for Solving the Problem" In the invention according to claim 1, in order to solve the problem, a plurality of gate buses and drain buses are formed on a substrate so as to intersect with each other via an insulating layer. In a thin film transistor array in which a gate electrode and a pixel electrode are installed on the substrate near this intersection, and a gate insulating film and a semiconductor film are stacked on top of them to form a thin film transistor, the gate bus and drain bus are semiconductor A contact hole is formed on the film, and the gate bus and the gate electrode are connected through a contact hole that penetrates the gate insulating film and the semiconductor film, and the drain electrode and the drain bus are connected through a contact hole that penetrates the gate insulating film and the semiconductor film. The thin film transistor array is characterized in that the thin film transistor array is connected through the

In the invention according to claim 2, in order to solve the above problem, a plurality of gate buses and drain buses are formed on the substrate so as to intersect with each other via an insulating layer, and a plurality of gate buses and drain buses are formed on the substrate in the vicinity of this intersection. In a thin film transistor array in which a gate electrode and a pixel electrode are installed on the substrate, and a gate insulating film and a semiconductor film are stacked on top of them to form a thin film transistor, a drain bus is formed on the substrate and is located near the intersection. The divided lower drain bus and the upper drain bus formed on the semiconductor film form a two-layer structure, and the upper drain bus and the lower drain bus are connected through a contact hole penetrating the gate insulating film and the semiconductor film. The thin film transistor array is characterized in that the thin film transistor array is connected to each other.

According to a third aspect of the invention, in order to solve the above problem, there is provided a thin film transistor array according to the first aspect or the second aspect, characterized in that the film thickness of the gate bus is thicker than the film thickness of the gate electrode.

According to a fourth aspect of the invention, in order to solve the problem, in the thin film transistor array according to the first aspect, the gate bus is made of a material having electrical resistance lower than that of the gate electrode or the drain bus. This is a thin film transistor array.

In the invention described in claim 5, in order to solve the above problem, in the thin film transistor array according to claim 2, the gate bus or the upper drain bus is made of a material having electrically lower resistance than the gate electrode or the lower drain bus. This thin film transistor array is characterized by the following characteristics.

In order to solve the above problem, the invention according to claim 6 forms a gate electrode and a drain bus on a substrate, then forms a gate insulating film and a semiconductor film thereon, and then forms a gate insulating film and a semiconductor film thereon. After forming a plurality of contact holes in the semiconductor film, a gate bus connected to the gate electrode through the contact hole, a drain electrode connected to the drain bus through the contact hole, and a gate bus connected to the gate electrode through the contact hole, and a drain electrode connected to the drain bus through the contact hole are formed on the semiconductor film. This method of manufacturing a thin film transistor array is characterized in that a source electrode connected to a pixel electrode is formed using a pixel electrode.

In order to solve the above problem, the invention according to claim 7 forms a gate electrode and a lower drain bus on a substrate, and then:
A gate insulating film and a semiconductor film are formed thereon, and then a plurality of contact holes are formed in the gate insulating film and the semiconductor film, and then a gate bus is connected to the gate electrode through the contact holes on the semiconductor film; This method of manufacturing a thin film transistor array is characterized in that an upper drain bus connected to a lower drain bus through a contact hole and a source electrode connected to a pixel electrode through a contact hole are formed on a semiconductor film.

"Example 1" Figures 1 to 3 are diagrams showing Example 1 of the present invention, where Figure 1 is a plan view and Figure 2 is a line taken along line AA' in Figure 1.
The sectional view, FIG. 3, is a sectional view taken along the line B--B in FIG. 1.

In this embodiment, Cr,
A gate electrode 4 and a drain bus 2 are formed of a high melting point metal material such as Mo, Ta, and Ti, and a pixel electrode 1 is also formed.
is formed. A gate insulating film lO made of silicon nitride or the like is laminated on the gate electrode 4, and a semiconductor film 9 made of hydrogenated amorphous silicon is laminated on this gate insulating film.

Further, on this semiconductor film 9, a gate bus 3, a drain electrode 5, and a source electrode 6 are provided using a metal material with low resistance. The metal material constituting the gate bus 3 and drain electrode 5 in this embodiment may be any metal material as long as it is a conductor, but by using a metal material with low resistance, such as AI, the resistance of the gate wiring can be reduced. You can lower the value.

Furthermore, the gate bus 3 is connected to the gate electrode 4 via a contact hole 8 formed in the semiconductor film 9 and the gate insulating film 1O. Furthermore, the drain electrode 5 is a semiconductor film 9
and a contact hole 7b made in the gate insulating film 10.
The drain bus 2 is connected to the drain bus 2 via the drain bus 2. Furthermore, the source electrode 6 is connected to the pixel electrode l via a contact hole 7a formed in the semiconductor film 9 and the gate insulating film lO.

To manufacture the thin film transistor having the above-described structure, first, the gate electrode 4 and the drain bus 2 made of a high-melting point metal material and the pixel electrode 1 are formed on a substrate made of glass or the like. After that, a gate insulating film 10 is formed on the gate electrode.
Further, a semiconductor film 9 is laminated on the gate insulating film, and contact holes 7a and 7b18 are formed. Then, a gate bus 3, a drain electrode 5, and a source electrode 6 are provided on the semiconductor film 9 using a metal material with low resistance.

At this time, the gate bus 3 includes the semiconductor film 9 and the gate insulating film 10.
The gate electrode 4 is connected to the gate electrode 4 through the contact hole 8 made in the
Connect to. Drain electrode 5 is connected to drain bus 2 via contact hole 7b formed in semiconductor film 9 and gate insulating film IO.

The source electrode 6 is connected to the pixel electrode l via a contact hole 7a formed in the semiconductor film 9 and the gate insulating film 10.

By the way, the resistance R(G) of the gate wiring (gate bus) is expressed as R(G)=ρXL/(W−d). Here, ρ is the specific resistance of the gate wiring material, L
is the length of the gate wiring, W is the gate wiring width, and d is the film thickness of the gate wiring.

In order to reduce the resistance of the gate wiring, from the above formula, ρ
Alternatively, it is easy to consider reducing L or increasing W or d.

However, considering the actual configuration, L is determined by the size of the display, and W is determined by the aperture ratio. Furthermore, in the conventional example, if d is made too thick, the gate insulating film lO is formed on the gate wiring.
Furthermore, if the amount of material with low resistivity is used to reduce ρ, there will be concerns about thermal stability and chemical stability, which will naturally limit the amount of material used. Sometimes it happens.

Therefore, in this embodiment, the gate electrode 4 and the drain bus 2, which are particularly required to have good adhesion with the underlying substrate 26, thermal stability, chemical stability, and workability, meet the above-mentioned requirements. It is made of a high melting point metal material, which is an excellent material.

Furthermore, by forming the gate bus 3, drain electrode 5, and source electrode 6 from a metal material with a low resistance value, such as A1, the resistance value of the gate wiring can be lowered.

Furthermore, as in the structure of this embodiment, since the gate bus 3 is connected to the gate electrode via the contact hole 8 penetrating the gate insulating film 10 and the semiconductor film 9, the step coverage of the gate insulating film 10 is reduced. The film thickness of the gate bus 3 can be increased without making it difficult.

With the above structure and manufacturing method, it is possible to lower the specific resistance without impairing thermal stability or chemical stability, and to increase the thickness of the gate wiring.

Therefore, by increasing d in the above equation, it is possible to decrease ρ. As a result, the resistance R(
It can be realized by lowering (1;).

Furthermore, like the thin film transistor array of the present invention,
In a thin film transistor liquid crystal display device having a structure in which a pixel electrode 1 and an ITO (transparent conductive film) are first formed, it is possible to form the pixel and the gate electrode with ITO, thereby reducing the step of forming the gate electrode.

"Embodiment 2" FIGS. 4 to 6 are diagrams showing Embodiment 2 of the present invention, in which FIG. 4 is a plan view and FIG. 5 is a line AA' in FIG. 4.
The sectional view, FIG. 6, is a sectional view taken along the line B--B in FIG. 4.

In this embodiment, Cr, Mo, Ta,
The gate electrode 4 and the lower drain bus 13 are formed of a high melting point metal material such as Ti. As shown in FIG. 4, the lower drain bus 13 has a width comparable to that of the gate bus 3 and a length several times that width, and intersects with the gate bus 3 via an insulating layer. It is formed like this.

A gate insulating film 18 made of silicon nitride or the like is laminated on the gate electrode 4, and a semiconductor film 17 made of hydrogenated amorphous silicon is laminated on the gate insulating film. Further, on this semiconductor film 17, a gate 7 (substrate 3), a drain electrode 12, an upper drain bus 11, and a source electrode 6 are provided using a metal material with low resistance.

The upper drain bus 11 is similar to the lower drain bus 13 described above.
It is formed so as to overlap one end of the lower drain bus 13 on the lower right side of the pixel electrode 1 in FIG. 4 and one end of the lower drain bus 13 on the upper right side of the pixel electrode 1 in FIG. The drain electrode 12 connected to one end of the upper drain bus 11 is connected to the semiconductor film 17 and the gate insulating film 1.
It is connected to one end of the lower drain bus 13 via a contact hole 14 formed in the lower drain bus 13 . The other end of the upper drain bus II made of an electrically low resistance metal material is connected via a contact hole 15 to the lower drain bus 13 on the upper right side of FIG. 4 made of a high melting point metal material, and furthermore, The upper drain bus 11 at the lower right in the figure is connected to the lower drain bus 13 at the lower right through the contact hole 16.
connected to one end of the By repeatedly connecting the upper drain bus 11 made of a low resistance metal material and the lower drain bus 13 made of a high melting point metal material in this way, the circuits of individual pixels can be arranged in a matrix over the entire screen of the liquid crystal display device. becomes.

Furthermore, the gate bus 3 includes a semiconductor film 17 and a gate insulating film 18.
The gate electrode 4 is connected to the gate electrode 4 through the contact hole 8 made in the
It is connected to the.

Further, the source electrode 6 includes a semiconductor film 17 and a gate insulating film 1.
The pixel electrode 1 is connected to the pixel electrode 1 through a contact hole 7a formed in the pixel electrode 8.

Here, the materials of the gate bus 3, drain electrode 12, upper drain bus 11, and source electrode 6 are the same as in Example 1.
Any metal material may be used as long as it is a conductor, but the resistance value of the gate wiring can be lowered by using a metal material with low resistance, such as Al.

In order to manufacture the thin film transistor having the above structure, the gate electrode 4 and the lower drain bus 13 made of the above-mentioned high melting point metal material and the pixel electrode 1 are formed on a substrate made of glass. After that, a gate insulating film 18 is provided on the gate electrode 4, and a semiconductor film 17 is further provided on the gate insulating film.
are laminated, and contact holes 7a, 8.14 are formed.
form.

Then, the gate bus 3, the drain electrode 12, the upper drain bus 11, and the source electrode 6 are formed on the semiconductor film 17 using a metal material with low resistance. At this time, the gate bus 3 is connected to the gate electrode 4 through the contact hole 8 formed in the semiconductor film 17 and the gate insulating film 18, and the drain electrode 12 is connected to the gate electrode 4 through the contact hole 8 formed in the semiconductor film 17 and the gate insulating film 18. Lower drain bus 1 via contact hole 14
3, and the source electrode 6 is connected to the pixel electrode l via a contact hole 7a formed in the semiconductor film 17 and the gate insulating film 18. The upper drain bus 11 is connected to one end of the lower drain bus 13 at the upper right in FIG. Connected to one end of the bus 13.

As described above, since the gate electrode 4 and the lower drain bus 13 are formed of a high melting point metal material, adhesion with the underlying substrate, thermal stability, chemical stability, and workability can be ensured.

Furthermore, by forming the gate bus 3, the train electrode 12, and the source electrode 6 from a metal material with a low resistance value, such as AI, the resistance value of the gate wiring can be lowered.

Furthermore, in the structure of the present invention, since the gate bus 3 is connected to the gate electrode 4 via the contact hole 8 penetrating the gate insulating film 18 and the semiconductor film 17, it is difficult to perform step coverage of the gate insulating film 18. without doing,
The film thickness of the gate bus 3 can be increased.

"Manufacturing Example" A thin film transistor array according to Example 1 of the present invention and a conventional thin film transistor array shown in FIGS. 7 and 8 were manufactured, and the resistance R (G) of the gate wiring was measured.

The material of the drain bus 2 and gate electrode 4 of the thin film transistor array of Example 1 was Cr, and the material of the gate bus 3, drain electrode 5, and source electrode 6 was AI. In addition, the source electrode 19 of the conventional thin film transistor array
, the drain bus electrode 20, and the gate bus electrode 21 were made of Cr.

The above measurement results are shown in Table 1.

Table 1 Note that the d value of 6,000 people in the example of the present invention can be set to more than 6,000 people.

From the results in Table 1, it was confirmed that the resistance value R(G) of the gate wiring of the thin film transistor array of the example of the present invention was much smaller than the resistance value R(G) of the thin film transistor array of the conventional example.

"Effects of the Invention" As explained above, the thin film transistor array of the present invention has excellent adhesion with the underlying substrate, thermal stability, chemical stability,
It has excellent processability and can reduce the resistance value of the gate wiring, reducing the delay in switching operation of thin film transistors and supplying sufficient gate voltage and waveform to each pixel, resulting in larger displays and higher image quality. It made it possible to

[Brief explanation of the drawing]

FIG. 1 is a plan view of Example 1, FIGS. 2 and 3 are sectional views of Example 1, FIG. 4 is a plan view of Example 2, and FIGS. 5 and 6 are each of Example 2. 7 is a plan view of the conventional example, and FIG. 8 is a sectional view of the conventional example. 1...Pixel electrode, 2.20...Drain bus, 321...Gate bus, 425...Gate electrode, 5.12.22... ...Train electrode, 619...
...Source electrode, 7a, 7b, 8, 14, 15.16--Contact hole, 9.17.23...Semiconductor film, 10 18.2
4... Gate insulating film, 11... Upper drain bus, 13... Lower drain bus, 26... Substrate.

Claims (7)

[Claims] (1) A plurality of gate buses and drain buses are formed on the substrate so as to intersect with each other via an insulating layer, and a gate electrode and a pixel electrode are installed on the substrate near the intersection,
In a thin film transistor array in which a thin film transistor is formed by stacking a gate insulating film and a semiconductor film thereon, a gate bus and a drain bus are formed on the semiconductor film, and a gate bus and a gate electrode are stacked on the gate insulating film and the semiconductor film. A thin film transistor array characterized in that the thin film transistor array is connected to each other through a contact hole that penetrates the film, and further comprises a drain electrode and a drain bus that are connected to each other through a contact hole that penetrates a gate insulating film and a semiconductor film. (2) A plurality of gate buses and drain buses are formed on the substrate so as to intersect with each other via an insulating layer, and a gate electrode and a pixel electrode are installed on the substrate near the intersection,
In a thin film transistor array in which a thin film transistor is formed by laminating a gate insulating film and a semiconductor film thereon, a drain bus is formed on a substrate and is separated from a lower drain bus near the intersection, and a semiconductor film. It has a two-layer structure with an upper drain bus formed above, and is characterized in that the upper drain bus and the lower drain bus are connected via a contact hole penetrating the gate insulating film and the semiconductor film. Thin film transistor array. (3) The thin film transistor array according to claim 1 or 2, wherein the film thickness of the gate bus is thicker than the film thickness of the gate electrode. (4) The thin film transistor array according to claim 1, wherein the gate bus is made of a material having electrical resistance lower than that of the gate electrode or the drain bus. (5) The thin film transistor array according to claim 2, wherein the gate bus or the upper drain bus is made of a material having electrical resistance lower than that of the gate electrode or the lower drain bus. (6) After forming a gate electrode and a drain bus on the substrate, then forming a gate insulating film and a semiconductor film on them, and then forming a plurality of contact holes in the gate insulating film and the semiconductor film, the semiconductor A gate bus connected to the gate electrode through the contact hole, a drain electrode connected to the drain bus through the contact hole, on the film;
A method for manufacturing a thin film transistor array, comprising forming source electrodes connected to pixel electrodes through contact holes. (7) After forming a gate electrode and a lower drain bus on the substrate, then forming a gate insulating film and a semiconductor film on them, and then forming a plurality of contact holes in the gate insulating film and the semiconductor film, A gate bus connected to the gate electrode through a contact hole on the semiconductor film, an upper drain bus connected to the lower drain bus through the contact hole on the semiconductor film, and a top drain bus connected to the pixel electrode through the contact hole. 1. A method of manufacturing a thin film transistor array, comprising: forming a source electrode.