JPH0426553B2 - - Google Patents
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- Publication number
- JPH0426553B2 JPH0426553B2 JP17051085A JP17051085A JPH0426553B2 JP H0426553 B2 JPH0426553 B2 JP H0426553B2 JP 17051085 A JP17051085 A JP 17051085A JP 17051085 A JP17051085 A JP 17051085A JP H0426553 B2 JPH0426553 B2 JP H0426553B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- electrode film
- oxide film
- gate oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 30
- 230000004888 barrier function Effects 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 4
- 230000006378 damage Effects 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000011282 treatment Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に係り、特にメ
モリ、CPU（Central Processing Unit）、ゲー
ト・アレイ等の半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device such as a memory, a CPU (Central Processing Unit), a gate array, etc.
従来、電界効果型半導体装置における電界効果
トランジスタの電極を形成する場合、第５図に示
されるように、半導体基板１表面に電極絶縁膜４
を形成し（第５図ａ）、その後電気的特性を決定
するためこの電極絶縁膜４上において直接に
PEP（Photo Etching Process）、イオン注入をお
こない（第５図ｂ）、また一部領域における電極
絶縁膜４のエツチング、レジスト剥離等の種々の
処理を行ない、これらの処理の後に電極絶縁膜４
上に電極１０を形成していた（第５図ｃ，ｄ）。
Conventionally, when forming an electrode of a field effect transistor in a field effect semiconductor device, as shown in FIG.
(Fig. 5a), and then directly on this electrode insulating film 4 to determine the electrical characteristics.
PEP (Photo Etching Process), ion implantation (Fig. 5b), etching of the electrode insulating film 4 in some areas, resist peeling, etc. are performed, and after these processes, the electrode insulating film 4 is removed.
An electrode 10 was formed on top (Fig. 5c, d).
しかしながら、電極絶縁膜形成後から電極形成
までの上記のような処理により、電極絶縁膜の劣
化ないし破壊が発生する。また、半導体装置の高
集積化および微細化に伴い電極絶縁膜の膜厚は例
えば約600Å以下と薄くなつてきているため、そ
れにつれて電極絶縁膜の劣化ないし破壊の発生が
増加するという問題があつた。 However, the above-described processing after forming the electrode insulating film until forming the electrode causes deterioration or destruction of the electrode insulating film. In addition, as semiconductor devices become more highly integrated and miniaturized, the thickness of electrode insulating films has become thinner, to about 600 Å or less, for example, and this has led to the problem that the occurrence of deterioration or destruction of electrode insulating films has increased. Ta.
さらに半導体基板と電極とが直接に接触する半
導体装置においては、電極を形成する前に電極絶
縁膜を数十Åエツチングする処理があるため、電
極絶縁膜は多少とも劣化ないしは破壊されるとい
う問題があつた。 Furthermore, in semiconductor devices where the semiconductor substrate and electrodes are in direct contact, the electrode insulating film is etched by several tens of angstroms before forming the electrodes, so there is a problem that the electrode insulating film may deteriorate or be destroyed to some extent. It was hot.
本発明は上記事情を考慮してなされたもので、
電極絶縁膜形成後の種々の処理による電極絶縁膜
の劣化ないし破壊が発生しないようにした半導体
装置の製造方法を提供することを目的とする。
The present invention was made in consideration of the above circumstances, and
It is an object of the present invention to provide a method for manufacturing a semiconductor device that prevents deterioration or destruction of an electrode insulating film due to various treatments after forming the electrode insulating film.
上記目的を達成するため本発明による半導体装
置の製造方法は、半導体基板表面に電極絶縁膜を
形成する第１の工程と、前記電極絶縁膜上に前記
電極絶縁膜を保護する薄い障壁電極膜を形成する
第２の工程と、前記半導体基板に不純物を添加す
る第３の工程と、前記障壁電極膜上に電極膜を形
成する第４の工程と、前記障壁電極膜と前記電極
膜とをエツチングして電極を形成する第５の工程
とを有することを特徴とする。
In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes a first step of forming an electrode insulating film on the surface of a semiconductor substrate, and forming a thin barrier electrode film on the electrode insulating film to protect the electrode insulating film. a second step of forming the semiconductor substrate, a third step of adding impurities to the semiconductor substrate, a fourth step of forming an electrode film on the barrier electrode film, and etching the barrier electrode film and the electrode film. and a fifth step of forming an electrode.
これにより障壁電極膜が、第２の工程と第４の
工程との間に行なわれる種々の処理による電極絶
縁膜の劣化ないし破壊を防止するようにしたもの
である。 This prevents the barrier electrode film from deteriorating or breaking the electrode insulating film due to various treatments performed between the second step and the fourth step.
本発明の一実施例による半導体装置の製造方法
を第１図を用いて説明する。例えばＰ型シリコン
の半導体基板１表面にフイールド酸化膜２を形成
すると共にこのフイールド酸化膜２下の半導体基
板１表面にＰ型反転防止層３を形成することによ
り素子領域を分離し、さらに素子領域の半導体基
板１表面に膜厚約500Åのゲート酸化膜４を形成
する（第１図ａ）。続いて薬品処理、水洗処理等
のクリーニング処理をおこなうことなく直ちにこ
のゲート酸化膜４上に膜厚約200Åのポリシリコ
ンから成る障壁電極膜５を形成する（第１図ｂ）。
これにより障壁電極膜５がゲート酸化膜４の全面
を覆つて保護している点に特徴がある。
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. For example, a field oxide film 2 is formed on the surface of a P-type silicon semiconductor substrate 1, and a P-type inversion prevention layer 3 is formed on the surface of the semiconductor substrate 1 under this field oxide film 2, thereby separating device regions. A gate oxide film 4 having a thickness of approximately 500 Å is formed on the surface of the semiconductor substrate 1 (FIG. 1a). Subsequently, a barrier electrode film 5 made of polysilicon and having a thickness of about 200 Å is immediately formed on the gate oxide film 4 without performing any cleaning treatment such as chemical treatment or water washing (FIG. 1b).
This structure is characterized in that the barrier electrode film 5 covers and protects the entire surface of the gate oxide film 4.
次にPEPにより障壁電極膜５上の所定の場所
にレジスト６を形成した後、イオン注入により素
子領域の半導体基板１表面の所定の場所に電極イ
オン注入層７を形成する（第１図ｃ）。このとき
イオン注入の加速電圧は膜厚約500Åのゲート酸
化膜３と膜厚約200Åの障壁電極層４とに応じた
電圧値を設定する。 Next, a resist 6 is formed at a predetermined location on the barrier electrode film 5 by PEP, and then an electrode ion implantation layer 7 is formed at a predetermined location on the surface of the semiconductor substrate 1 in the element region by ion implantation (FIG. 1c). . At this time, the acceleration voltage for ion implantation is set to a voltage value corresponding to the gate oxide film 3 with a thickness of about 500 Å and the barrier electrode layer 4 with a thickness of about 200 Å.
次いでレジスト６を剥離した後、全面に膜厚約
4000Åのポリシリコンから成る電極膜８を形成す
る（第１図ｄ）。このとき障壁電極膜５と電極膜
８とは完全に密着して一体のものとなる。続いて
リン拡散により、障壁電極膜５および電極膜８を
導体とする（第１図ｅ）。 Next, after peeling off the resist 6, a film with a thickness of approximately
An electrode film 8 made of polysilicon with a thickness of 4000 Å is formed (FIG. 1d). At this time, the barrier electrode film 5 and the electrode film 8 are completely adhered to each other and become one body. Subsequently, the barrier electrode film 5 and the electrode film 8 are made into conductors by phosphorus diffusion (FIG. 1e).
次にPEPにより電極膜８上の所定の場所にレ
ジスト９を形成した後、エツチングにより障壁電
極膜５および電極膜８を除去し、所定の場所に障
壁電極膜５および電極膜８から成る電極１０を形
成する（第１図ｆ）。最後にレジスト９を剥離す
る（第１図ｇ）。 Next, after forming a resist 9 at a predetermined location on the electrode film 8 by PEP, the barrier electrode film 5 and the electrode film 8 are removed by etching, and an electrode 10 made of the barrier electrode film 5 and the electrode film 8 is formed at a predetermined location. (Fig. 1 f). Finally, the resist 9 is peeled off (FIG. 1g).
このように本実施例によれば、障壁電極膜５が
ゲート酸化膜４表面を覆うことにより、電極膜８
形成までのPEP、イオン注入およびレジスト剥
離の各処理におけるゲート酸化膜４へのダメージ
を防ぐことができる。このことにより、本実施例
による半導体装置のゲート耐圧特性を従来のもの
と比較して示す第３図のグラフから明らかなよう
に、従来の製造方法よりゲート耐圧特性が大幅に
改善される。 According to this embodiment, the barrier electrode film 5 covers the surface of the gate oxide film 4, so that the electrode film 8
It is possible to prevent damage to the gate oxide film 4 during the PEP, ion implantation, and resist stripping processes prior to formation. As a result, as is clear from the graph of FIG. 3, which shows the gate breakdown voltage characteristics of the semiconductor device according to this embodiment in comparison with the conventional one, the gate breakdown voltage characteristics are significantly improved compared to the conventional manufacturing method.
本発明の他の実施例による半導体装置の製造方
法を第２図を用いて説明する。上記実施例と同様
にして例えばＰ型シリコンの半導体基板１の表面
にフイールド酸化膜２、Ｐ型反転防止層３および
膜厚約500Åのゲート酸化膜４を形成し（第２図
ａ）、続いてこのゲート酸化膜４上に膜厚約200Å
のポリシリコンから成る障壁電極膜５を形成する
（第２図ｂ）。これにより障壁電極膜５がゲート酸
化膜４の全面を覆つて保護している点に特徴があ
る。 A method of manufacturing a semiconductor device according to another embodiment of the present invention will be described with reference to FIG. In the same manner as in the above embodiment, a field oxide film 2, a P-type anti-inversion layer 3, and a gate oxide film 4 having a thickness of about 500 Å are formed on the surface of a semiconductor substrate 1 made of, for example, P-type silicon (FIG. 2a), and then A film thickness of approximately 200 Å is placed on the gate oxide film 4 of the lever.
A barrier electrode film 5 made of polysilicon is formed (FIG. 2b). This structure is characterized in that the barrier electrode film 5 covers and protects the entire surface of the gate oxide film 4.
次にPEPにより障壁電極膜５上の所定の場所
にレジスト１１を形成した後、障壁電極膜５およ
びゲート酸化膜４のエツチングによりダイレク
ト・コンタクト領域１２を開口する（第２図ｃ）。 Next, a resist 11 is formed at a predetermined location on the barrier electrode film 5 by PEP, and then a direct contact region 12 is opened by etching the barrier electrode film 5 and the gate oxide film 4 (FIG. 2c).
次いでレジスト１１を剥離した後、全面に膜厚
約4000Åのポリシリコンから成る電極膜８を形成
する（第２図ｄ）。このときダイレクト・コンタ
クト領域１２の半導体基板１と電極膜８との良好
な電気的接触を徳るために、電極膜８を形成する
前にダイレクト・コンタクト領域１２上の酸化膜
を約30Åエツチングする程のスライス・エツチン
グを行なうが、障壁電極膜５があるためゲート酸
化膜４は保護されている。続いてリン拡散によ
り、障壁電極膜５および電極膜６を導電体とする
と共にダイレクト・コンタクト領域１２の半導体
基板１表面にn+不純物領域１３を形成する（第
２図ｅ）。 After removing the resist 11, an electrode film 8 made of polysilicon with a thickness of about 4000 Å is formed on the entire surface (FIG. 2d). At this time, in order to achieve good electrical contact between the semiconductor substrate 1 and the electrode film 8 in the direct contact region 12, the oxide film on the direct contact region 12 is etched by about 30 Å before forming the electrode film 8. Although slicing and etching is performed to a certain extent, the gate oxide film 4 is protected by the presence of the barrier electrode film 5. Subsequently, by phosphorus diffusion, the barrier electrode film 5 and the electrode film 6 are made into conductors, and an n + impurity region 13 is formed on the surface of the semiconductor substrate 1 in the direct contact region 12 (FIG. 2e).
最後にPEPにより電極膜８上の所定の場所に
レジスト１４を形成した後、エツチングにより所
定の場所に障壁電極膜５および電極膜８から成る
電極１０を形成し（第２図ｆ）、レジスト１４を
剥離する（第２図ｇ）。 Finally, a resist 14 is formed at a predetermined location on the electrode film 8 by PEP, and then an electrode 10 consisting of the barrier electrode film 5 and the electrode film 8 is formed at a predetermined location by etching (FIG. 2f). (Figure 2g).
このように本実施例によれば、障壁電極膜５が
ゲート酸化膜４表面を覆うことにより、電極膜８
形成までのエツチング、ダイレクト・コンタクト
領域１２を開口するエツチングおよびレジスト剥
離の各処理におけるゲート酸化膜４へのダメージ
を防ぐと共に、電極膜８形成前のダイレクト・コ
ンタクト領域１２へのスライス・エツチングによ
つてゲート酸化膜４表面がエツチングされること
も防ぐことができる。このことにより、本実施例
による半導体装置のゲート耐圧特性を従来のもの
と比較して示す第４図のグラフから明らかなよう
に、従来の製造方法よりゲート耐圧特性が大幅に
改善される。 According to this embodiment, the barrier electrode film 5 covers the surface of the gate oxide film 4, so that the electrode film 8
In addition to preventing damage to the gate oxide film 4 during each process of etching before formation, etching to open the direct contact region 12, and resist stripping, the slice etching to the direct contact region 12 before the formation of the electrode film 8 prevents damage to the gate oxide film 4. It is also possible to prevent the surface of the gate oxide film 4 from being etched. As a result, as is clear from the graph of FIG. 4, which shows the gate breakdown voltage characteristics of the semiconductor device according to this embodiment in comparison with the conventional one, the gate breakdown voltage characteristics are significantly improved compared to the conventional manufacturing method.
なお上記２つの実施例において、障壁電極膜５
と電極膜８とは共にポリシリコンから成つている
が、互いに異なる材質でもよい。 Note that in the above two embodiments, the barrier electrode film 5
Although both the electrode film 8 and the electrode film 8 are made of polysilicon, they may be made of different materials.
また上記２つの実施例において、膜厚約500Å
のゲート酸化膜４に対して膜厚約200Åの障壁電
極膜５を形成したが、ゲート酸化膜４の膜厚に応
じて障壁電極膜５の膜厚を100Åないし500Åと選
択することができる。特にゲート酸化膜４が薄い
場合に、本発明によるゲート酸化膜４の劣化ない
し破壊の防止は大きな効果を発揮する。 In addition, in the above two examples, the film thickness was approximately 500 Å.
Although the barrier electrode film 5 having a thickness of about 200 Å is formed on the gate oxide film 4, the thickness of the barrier electrode film 5 can be selected from 100 Å to 500 Å depending on the thickness of the gate oxide film 4. Particularly when the gate oxide film 4 is thin, the prevention of deterioration or destruction of the gate oxide film 4 according to the present invention is highly effective.
以上の通り本発明によれば、電極絶縁膜が電極
絶縁膜形成後の種々の処理によつて劣化ないし破
壊されないようにすることができる。
As described above, according to the present invention, the electrode insulating film can be prevented from deteriorating or being destroyed by various treatments after the electrode insulating film is formed.
第１図は本発明の一実施例による半導体装置の
製造方法を示す工程図、第２図は本発明の他の実
施例による半導体装置の製造方法を示す工程図、
第３図および第４図は本発明により製造された半
導体装置の特性を示すグラフ、第５図は従来の半
導体装置の製造方法を示す工程図である。
１……半導体基板、２……フイールド酸化膜、
３……反転防止層、４……ゲート酸化膜（電極絶
縁膜）、５……障壁電極膜、６，９，１１，１４
……レジスト、７……電極イオン注入層、８……
電極膜、１０……電極、１２……ダイレクト・コ
ンタクト領域、１３……n+不純物領域。
FIG. 1 is a process diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a process diagram showing a method for manufacturing a semiconductor device according to another embodiment of the invention,
3 and 4 are graphs showing the characteristics of a semiconductor device manufactured according to the present invention, and FIG. 5 is a process diagram showing a conventional method for manufacturing a semiconductor device. 1...Semiconductor substrate, 2...Field oxide film,
3... Inversion prevention layer, 4... Gate oxide film (electrode insulating film), 5... Barrier electrode film, 6, 9, 11, 14
...Resist, 7... Electrode ion implantation layer, 8...
Electrode film, 10...electrode, 12...direct contact region, 13...n + impurity region.
Claims (1)
の工程と、 前記電極絶縁膜上に前記電極絶縁膜を保護する
薄い障壁電極膜を形成する第２の工程と、 前記半導体基板に不純物を添加する第３の工程
と、 前記障壁電極膜上に電極膜を形成する第４の工
程と、 前記障壁電極膜と前記電極膜とをエツチングし
て電極を形成する第５の工程と を有することを特徴とする半導体装置の製造方
法。[Claims] 1. A first method for forming an electrode insulating film on the surface of a semiconductor substrate.
a second step of forming a thin barrier electrode film on the electrode insulating film to protect the electrode insulating film; a third step of adding impurities to the semiconductor substrate; A method for manufacturing a semiconductor device, comprising: a fourth step of forming an electrode film; and a fifth step of etching the barrier electrode film and the electrode film to form an electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17051085A JPS6231171A (en) | 1985-08-01 | 1985-08-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17051085A JPS6231171A (en) | 1985-08-01 | 1985-08-01 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6231171A JPS6231171A (en) | 1987-02-10 |
| JPH0426553B2 true JPH0426553B2 (en) | 1992-05-07 |
Family
ID=15906282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17051085A Granted JPS6231171A (en) | 1985-08-01 | 1985-08-01 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6231171A (en) |
-
1985
- 1985-08-01 JP JP17051085A patent/JPS6231171A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6231171A (en) | 1987-02-10 |
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