JPH04265015A - Signal level converting circuit - Google Patents

Abstract

PURPOSE:To stabilize a signal level conversion, a increase the speed of conversion, and also, to reduce the power consumption in a signal level converting circuit suitable for a Bi-CMOS circuit. CONSTITUTION:The circuit is provided with a pair of current switching transistors 31, 32 whose emitters are connected in common, and also, connected to a low potential power source VEE through a current source, collectors are connected to a high potential power source VCC through a resistor, respectively, and a signal is inputted to at least one gate, a first P conductive type field effect transistor 5 whose gate is connected to the collector of one 32 of a pair of current switching transistors, and a second and a third P conductive type field effect transistors 6, 7 whose gates are connected to the collector of the other 31 of a pair of current switching transistors, respectively and whose current lines are connected mutually in series, and the signal of an EC level is subjected to level conversion to the signal of a CMOS level through the switching operation of the three respective field effect transistors.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to a signal level conversion circuit, and more particularly, to an E-level conversion circuit in a Bi-CMOS circuit.
The present invention relates to a signal level conversion circuit suitable for signal conversion from CL level to CMOS level.

In recent years, with the demand for higher speed and lower power consumption in computer systems, ECL circuits capable of high-speed operation have been adopted for CPU sections that require particularly high-speed operation.
A so-called Bi-CMOS, which uses a CMOS circuit capable of low power consumption, is used in the peripheral section that forms the input/output section of the CPU section.
Circuits are becoming more and more popular.

A Bi-CMOS circuit requires a signal level conversion circuit as an interface device for converting a small-amplitude ECL-level logic signal to a large-amplitude CMOS-level logic signal.

0004

2. Description of the Related Art FIG. 3 shows a circuit diagram of a conventional signal level conversion circuit used in a Bi-CMOS circuit. In the same figure, this signal level conversion circuit is driven between a ground line GND which constitutes a high potential power supply and a -5.2V power supply line VEE which constitutes a low potential power supply, and inputs a logic signal of ECL level. It receives a signal IN and outputs a CMOS level output signal OUT. Note that in this circuit diagram, the voltage value of the signal level at each main node is added to the node. For example, -1.7 added to the input signal IN.
/-0.9V becomes -1.7V L level when the voltage level is logic "0", and -0.9V when it is logic "1".
It is at an H level of 0.9V, indicating that the input signal level fluctuates within this range.

The input signal IN is input to a level shift circuit Q1,
The signal level is shifted to -2.5/-1.7V via D1, and applied to a pair of current switch transistors Q2 and Q3 forming an ECL circuit, and applied to the gate of one of the current switch transistors, Q3. It is compared with reference voltage VBB2 (-2.1V). The outputs of the current switch transistors Q2 and Q3 are given as inputs to the second level shift circuits Q15 and D2,
A pair of field effect transistors, the output of which performs the switching action of the next CMOS type operation, namely a P-channel transistor Q16 and an N-channel transistor Q17.
input into the gate.

As shown in FIG. 3, between the gates of P-channel and N-channel transistors Q16 and Q17, the threshold voltage of the P-channel transistor is in the range of -0.6V to -0.8V, and the threshold voltage of the P-channel transistor is in the range of -0.6V to -0.8V. The threshold voltage of the transistor is -3.6V to -3
．． Considering that there is a difference between both threshold voltages due to manufacturing reasons, such as in the range of 7V, a level shift diode D2 is used to compensate for this.
will be arranged. Therefore, each gate has a signal voltage of a different level, that is, -3.0V/-0. 9V and -3
．． A voltage with a signal level of 8V/-0.9V is supported respectively. The outputs of the pair of field effect transistors Q16 and Q17 are applied to the CMOS circuit disposed in the next stage as the output signal OUT of this signal level conversion circuit via a pair of output NPN transistors Q18 and Q19 that perform positive feedback. It will be done.

[0007]

[Problem to be solved by the invention] The above conventional Bi-CM
In the signal level conversion circuit of the OS circuit, taking the P-channel transistor Q16 as an example, the threshold voltage (-0.6V to 0.8V), and therefore the P-channel transistor is not completely turned off. That is, level shift circuits Q15, D2
However, there is a problem in that it is difficult to completely match the signal range added to each of a pair of field effect transistors with the actual threshold voltage of each transistor, and the through current flowing through both transistors is Otherwise, the operation of both transistors is not performed at the same time and is unstable, which poses a problem in that it becomes an obstacle to increasing the speed of signal level conversion.

Furthermore, the threshold voltage of each field effect transistor is determined by the potential difference from a high potential power source for a P-channel transistor, and by the potential difference from a low potential power source for an N-channel transistor. When the field effect transistors fluctuate, only the threshold voltage of one of them fluctuates, and there is a problem in that simultaneous operation of both field effect transistors is no longer guaranteed.

In view of the problems of the conventional signal level conversion circuits employed in ECL-BiCMOS circuits, etc., the present invention provides a signal level conversion circuit that can perform high-speed and stable switching operations and reduce power consumption. The purpose is to provide

0010

[Means for Accomplishing the Object] FIG. 1 is a diagram showing the principle of the present invention. In the figure, 1 is a current source, 21 and 22 are resistors, and 3
1, 32, 8 and 9 are NPN transistors, 4 is a current source or resistor, 5 to 7 are P-conductivity type field effect transistors,
IN1 and IN2 are input signals, and n5 is an output node.

[0011] In order to achieve the above object, in the present invention, FIG.
The emitters are connected in common and connected to a low potential power source (VEE) via a current source (1) as shown in FIG.
A pair of current switch transistors (31, 32) whose collectors are each connected to a high potential power supply (VCC) via a resistor (21, 22), and a signal (IN1, IN2) is input to at least one gate. , a gate is connected to the collector of one of the current switch transistors (32),
A first field effect transistor (5) of P conductivity type, the source of which is connected to a high potential power supply (VCC) and the drain connected to a low potential power supply (VEE) via a current source or resistance element (4).
), the gate is connected to the collector of the other current switch transistor (31), and the source is connected to the high potential power supply (VCC).
), a second field effect transistor (6) of P conductivity type connected to the transistors (6) having a gate connected to the collector of the one (32) of the current switch transistor, and a second field effect transistor (6) having a source connected to the collector of the one (32) of the current switch transistor. , the drain is connected to the drain of the first field effect transistor (5),
P-conductivity type third field effect transistors connected to each other (
7), and the base is the second field effect transistor (6).
a first NPN transistor (8) whose collector is connected to the drain of the first field effect transistor (5) and whose collector is connected to the high potential power supply (VCC), whose base is connected to the drain of the first field effect transistor (5) and whose emitter is connected to the low potential power supply (VEE). ), and the collector is connected to the first NPN transistor (8
) and a second NPN transistor (9) which is connected to the emitter of the transistor and forms an output node (n5).

0012

[Operation] This will be explained with reference to FIG. The differential signal that is the output of the pair of current switch transistors 31 and 32 is
It is inputted to each gate of the first to third field effect transistors of the P conductivity type through connection nodes n1 and n2 between the collectors of both and the resistors 21 and 22. Therefore, the connection node n4 between the source of the first field effect transistor 5 and the current source or resistance element 4, and the series connection node n3 of the source-drain paths of both the second and third field effect transistors are as follows.
The voltage levels are different depending on the H level or L level of the input signal. As a result, the potential of the current path connection node n5 of the pair of NPN transistors 8 and 9 becomes H level of the high potential power supply VCC level or L level of the low potential power supply VEE level according to the logic of the input signal, and the potential of the current path connection node n5 of the pair of NPN transistors 8 and 9 becomes H level of the high potential power supply VCC level or L level of the low potential power supply VEE level, and the CM of the next stage
A sufficient amplitude level can be obtained as an input level to the OS circuit.

[0013] Each of the first to third field effect transistors is
Since both are of the same conductivity type, it is easy to manufacture them so that their threshold voltages have the same value, and therefore the connection nodes n1 and n2 forming these input parts
It is easy to match the amplitude level of to this threshold voltage.

Furthermore, since each of the threshold voltages mentioned above is determined from the high potential power supply VCC, simultaneous operation of each transistor is guaranteed, and the operating voltage of the transistor is maintained even when the other low potential power supply fluctuates. There is no problem of misalignment, and the switching operation of each field effect transistor is performed stably.

One of the input signals IN1 and IN2 can be maintained at a reference voltage and the level of the other signal can be compared with this reference voltage, and a pair of actuation signals can also be input to them. .

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be further explained based on the drawings. FIG. 2 shows an ECL-BiCMO according to an embodiment of the present invention.
FIG. 3 is a circuit diagram of a signal level conversion circuit from an ECL level to a CMOS level in an S circuit.

In the figure, Q1 and D1 are level shift circuits as explained in the conventional circuit diagram, Q2 and Q3 are a pair of current switch transistors forming an ECL circuit, and Q5 to Q7 are first to third P-conductor transistors. type field effect transistors, Q8 and Q9 are output NPN transistors, Q
4. R4 is a current source, and R5 is a resistor. Note that Q9 is configured as a transistor with a Schottky diode. The signal levels as described above are adopted for each connection node n0 to n5.

The input signal IN is at the voltage level of -1.7/-0.9V as explained in the conventional circuit, and this voltage level is passed through the level shift circuits Q1 and D1 to the connection node n.
After being shifted to a signal level of -2.5/-1.7V, which is indicated by 0, the signal is input to current switch transistors Q2 and Q3 forming a differential amplifier circuit. This signal is compared with a reference voltage level (-2.1V) input to the gate of one of the current switch transistors, transistor Q3.

Current switch transistors Q2, Q3
The signal level of the differential signal that is the output of is -0.1/-2.
2V, and signals in this amplitude range are applied to the gates of the first to third field effect transistors Q5 to Q7. Each threshold voltage Vth of the first to third field effect transistors Q5 to Q7 is all in the range of -0.6 to -0.8V, and the value of this threshold voltage is from -0.1V to -2.2V. This enables simultaneous switching operation of each transistor for signals in the amplitude range of , providing stable operation. Further, for this reason, it is possible to prevent a through current flowing through the second and third field effect transistors, and power consumption does not increase.

Furthermore, since the threshold voltage of each field effect transistor is determined from the potential of the ground line GND, which is a high potential power supply, simultaneous switching of each transistor is guaranteed, and when the low potential power supply VEE fluctuates, However, the threshold voltage Vth of the first to third field effect transistors of the P conductivity type is not affected. Therefore, it is possible to avoid instability in the operation at the input/output section of the integrated circuit, where each element is generally operated at the same time and is likely to cause fluctuations in the power supply, and the stability of operation is further improved.

One of the NPN transistors Q8 and Q9 on the output side, Q9, is configured as a transistor with a Schottky diode. Therefore, it is possible to prevent current saturation in this transistor, prevent delays in switching operation due to carrier accumulation effects, and increase the operating speed of the transistor, contributing to faster signal level conversion.

In this embodiment, a reference voltage is applied to one gate of a pair of current switch transistors, and this reference voltage and ECL input to the gate of the other transistor are
Although a configuration in which the level signals are compared is adopted, the present invention is not limited to this, and it goes without saying that the signal level of a differential signal can be converted.

It goes without saying that the resistor R5 that limits the current value of the field effect transistor can be a constant current source. Prevents an increase in power consumption when the transistor is energized.

The signal level conversion circuit of the present invention is preferably employed in an ECL-BiCMOS circuit, but is of course not limited to this; for example, it can be applied to a GaAs MESFE circuit.
It can be expanded to source-coupled FET logic composed of T, and can be employed in various semiconductor circuits.

[0025]

As explained above, according to the signal level conversion circuit of the present invention, the threshold voltages of the three P-conductivity type field effect transistors arranged on the output side of the current switch transistor can be set to the same value. Since the switching operations are easy to perform, the switching operations can be performed simultaneously, making it possible to perform highly stable and high-speed switching operations, resulting in faster signal level conversion, which greatly contributes to speeding up semiconductor devices. It is.

Furthermore, since the threshold voltage of the field effect transistor is determined only by the voltage difference with the high-potential power supply voltage, the threshold voltage of the circuit is not affected by voltage fluctuations of the low-potential power supply, and signal level conversion is possible. Stable operation of the circuit is possible.

Furthermore, if the high potential power source is set to the ground potential, then
Fluctuations in the ground side potential can be suppressed to a lower level.
The stable operation of the signal level conversion circuit is further improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a circuit diagram of a signal level conversion circuit according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional signal level conversion circuit.

[Explanation of symbols]

Q1, Q15...Level shift transistors 31, 32,
Q2, Q3...Current switch transistors 5 to 7, Q5 to Q7...P conductivity type field effect transistor 8
, 9, Q8, Q9...Output NPN transistors R1 to R
5...Resistors D1, D2...Level shift diode 1...Constant current source 4...Current source or resistance element VCC, GND...High potential power supply VEE...Low potential power supply

Claims (1)

[Claims] Claim 1: Emitters are connected in common and connected to a low potential power source (VEE) via a current source (1), and collectors are connected to a high potential power source (VEE) via resistors (21, 22), respectively.
CC) and at least one gate has a signal (I
A pair of current switch transistors (31, 32) to which input voltages (N1, IN2) are input, the gate is connected to the collector of one of the current switch transistors (32), the source is connected to a high potential power supply (VCC), and the drain is connected to the current a first field effect transistor (5) of P conductivity type connected to a low potential power source (VEE) via a source or resistive element (4);
31), a second field effect transistor (6) of P conductivity type whose source is connected to the high potential power supply (VCC), and a collector of the one of the current switch transistors (32) whose gate is connected to the collector of the current switch transistor (32); , a third field effect transistor (7) of P conductivity type whose source is connected to the drain of the second field effect transistor (6) and whose drain is connected to the drain of the first field effect transistor (5), respectively.
and a first NPN transistor (8) whose base is connected to the drain of the second field effect transistor (6) and whose collector is connected to the high potential power supply (VCC), respectively; a second NPN transistor whose drain and emitter are connected to a low potential power source (VEE), respectively, and whose collector is connected to the emitter of the first NPN transistor (8) to form an output node (n5); A signal level conversion circuit comprising a transistor (9).