JPH04264769A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To balance a read signal amount and to stabilize a reading operation of a dynamic RAM, etc., by disposing a gate of a switch MOSFET vertically in parallel with a common IO line, and arranging a contact in the same direction as that of a corresponding gate. CONSTITUTION:WIO0 and WIO1 of noninverting signal lines of writing common IO lines WIO0 and WIO1 and WIO0B, WIO1B of inverting signal lines are disposed adjacently. Complementary bit lines for constituting a memory array MARY are so disposed as to be adjacent to complementary bit lines Bp0 and Bq0, etc., connected to writing common IO line WIO0 or WIO1 of two sets of complementary bit lines for constituting each bit line group. Thus, even if a mask is deviated at the time of forming a gate, parasitic capacities of the noninverting and inverting signal lines of the complementary bit lines can similarly be varied to prevent an unbalance thereof.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, such as a dynamic RAM (random access memory) equipped with a common IO line (common data line) and a sense amplifier including a switch MOSFET for bit line selection. ) and other particularly effective techniques.

0002

2. Description of the Related Art There is a dynamic RAM whose basic configuration is a memory array including a plurality of word lines and complementary bit lines arranged orthogonally. As illustrated in FIG. 6, the dynamic RAM has a common IO line IO coupled to a write amplifier WA and a read amplifier RA (here, a non-inverted common IO line IO and an inverted common IO line IOB are connected to a common The IO line is indicated by an underline, such as IO.Also, the so-called inverted signal or inverted signal line, which is selectively set to low level when it is enabled, is indicated by adding B to the end of its name. ), and further includes multiple pairs of switches MOSFETQ2 that selectively connect this common IO line and designated complementary bit lines Bp to Bs, etc.
A sense amplifier SA including Q9 and Q30 is provided.

[0003] Regarding a dynamic RAM equipped with a common IO line and a sense amplifier, for example,
It is described in Publication No. 185291 and the like.

0004

[Problem to be Solved by the Invention] In the conventional dynamic RAM described above, common IO
For example, as shown in FIG.
are arranged in a so-called horizontal manner so as to be substantially parallel to the complementary bit lines Bp to Bs, in other words, in a direction substantially orthogonal to the common IO line IO. This dynamic RAM
Now, the gates Go~Gs and the bit line selection signal line YSp~
Contacts C63 to C67 for coupling YSs and contacts C59 to C60 and C61 for coupling the diffusion layers of two adjacent switch MOSFETs to the non-inverted common IO line IO or the inverted common IO line IOB
.about.C62 are shared, and the required layout area of the sense amplifier SA is reduced.

However, as dynamic RAMs become smaller and more highly integrated, the inventors of the present invention have discovered that the so-called horizontal arrangement described above poses the following problems. That is, in the dynamic RAM of FIG. 8, for example, a contact C53 coupled to a non-inverted bit line Bq and a contact C54 coupled to an inverted bit line BqB are arranged on the inverted side with the corresponding gate Gq interposed therebetween. Therefore, if a manufacturing mask for forming gate Gq etc. is misaligned in the manufacturing process of dynamic RAM, for example, if the diffusion layer area increases on the non-inverted bit line Bq side and its parasitic capacitance increases, the inverted bit line On the line BqB side, the area of the diffusion layer is conversely reduced and its parasitic capacitance is reduced. As a result, the balance between the read signal amounts of the non-inverted bit line Bq and the inverted bit line BqB is lost, and the read operation of the dynamic RAM becomes unstable.

An object of the present invention is to prevent unbalance between the parasitic capacitances of the non-inverting and inverting signal lines of the complementary bit line due to mask misalignment when forming the gate of a switch MOSFET that selectively connects the common IO line and the complementary bit line. The purpose is to provide a layout method. Another object of the present invention is to balance the read signal amounts of non-inverted and inverted signal lines of complementary bit lines, and to
The purpose is to stabilize read operations such as.

[0007]

[Means for solving the problem] A switch MOSFE that selectively connects a common IO line and a designated complementary bit line.
The gates of T are arranged in a so-called vertical arrangement so as to be substantially parallel to the common IO line, and the contacts connecting the diffusion layers of these switch MOSFETs and the non-inverting and inverting signal lines of the corresponding complementary bit lines are connected to the corresponding gates. in the same direction.

[0008]

[Operation] According to the above means, even if a mask misalignment occurs when forming the gate of a switch MOSFET, the parasitic capacitances of the non-inverting and inverting signal lines of the complementary bit line can be changed in the same way, and imbalance can be prevented. can. As a result, the read signal amounts of the non-inverted and inverted signal lines of the complementary bit lines can be balanced, and the read operation of a dynamic RAM or the like can be stabilized.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a block diagram of an embodiment of a dynamic RAM to which the present invention is applied. Further, FIG. 2 shows a circuit diagram of an embodiment of the sense amplifier SA included in the dynamic RAM of FIG. 1, and FIG. 3 shows a partial layout thereof. Based on these figures, an overview of the configuration and operation of the dynamic RAM of this embodiment as well as its characteristics will be described. Note that the circuit elements in FIG. 2 and the circuit elements constituting each block in FIG. 1 are formed on one semiconductor substrate such as single-crystal silicon, although not particularly limited thereto. In the circuit diagram below, M is marked with an arrow in the channel (back gate) section.
OSFET (metal oxide semiconductor field effect transistor; in this specification, MOSFET is a general term for insulated gate field effect transistor) is a P-channel type, and is shown to distinguish it from N-channel MOSFET, which is not marked with an arrow. It will be done.

In FIG. 1, the dynamic RAM is
Memory array M arranged occupying most of the semiconductor substrate surface
ARY is its basic configuration. The memory array MARY includes a plurality of word lines arranged in parallel in the vertical direction, a plurality of complementary bit lines arranged in parallel in the horizontal direction, and a grid at the intersections of these word lines and complementary bit lines. and a plurality of dynamic memory cells arranged in a shape.

The word lines constituting the memory array MARY are coupled to an X address decoder XAD and are selectively brought into a selected state. Although not particularly limited, the X address decoder XAD has i+1
Bit internal address signals X0 to Xi are supplied, and an internal control signal XDG is supplied from the timing generation circuit TG. Also, the X address buffer XAB has an external terminal A.
i+1 bits of X address signal A via X0 to AXi
X0 to AXi are supplied, and an internal control signal AL is supplied from the timing generation circuit TG.

Although not particularly limited, the X address decoder XAD is selectively activated when the internal control signal XDG is set to a high level. In this operating state, the X address decoder XAD outputs the internal address signal
0 to Xi are decoded, and the corresponding word line of the memory array MARY is selectively set to a high level selection state. X
Address buffer XAB takes in and holds X address signals AX0 to AXi supplied via external terminals AX0 to AXi according to internal control signal AL, and also generates complementary internal address signal X based on these X address signals.
0 to Xi are formed and supplied to the X address decoder XAD.

Next, complementary bit lines forming memory array MARY are coupled to corresponding unit circuits of sense amplifier SA. The sense amplifier SA is connected to the memory array MAR.
It includes a plurality of unit circuits provided corresponding to each Y complementary bit line. Sense amplifier SA is supplied with internal control signals PC and PA from timing generation circuit TG. The sense amplifier SA is coupled to the write amplifier WA via two sets of write common IO lines WIO0 and WIO1, and is connected to two sets of read common IO lines R, although this is not particularly limited.
It is coupled to read amplifier RA via IO0 and RIO1.

Here, each of the unit circuits constituting the sense amplifier SA includes, but is not particularly limited to, a P-channel MOSFET Q2, an N-channel MOSFET Q12, and a P-channel MOS, as illustrated in FIG.
A unit amplifier circuit formed by cross-connecting a pair of CMOS (complementary MOS) inverter circuits consisting of FET Q3 and N-channel MOSFET Q13, and a bit line precharge circuit consisting of three N-channel MOSFETs Q14 to Q16 in series-parallel configuration. including. Further, an N-channel MOSFET Q17 is provided corresponding to each complementary bit line of the memory array MARY, that is, the unit amplifier circuit described above.
and a writing switch MOSFET consisting of Q18 or N-channel MOSFETQ19 and Q20, and N-channel MOSFETQ21 and Q22 and Q25 and Q26 or N-channel MOSFETQ.
23 and Q24, and a readout switch MOSFET consisting of Q27 and Q28.

Among these, the commonly coupled drains of MOSFETs Q2 and Q12 constituting each unit amplifier circuit of the sense amplifier SA, that is, the commonly coupled gates of MOSFETs Q3 and Q13, are used as non-inverting input/output nodes of each unit amplifier circuit. , are coupled to non-inverted signal lines Bq0 or Bq1 of the corresponding complementary bit lines, respectively. Also, M.O.
The commonly-coupled drains of SFETQ3 and Q13, or the commonly-coupled gates of MOSFETQ2 and Q12, are used as inverting input/output nodes of each unit amplifier circuit, and are coupled to the inverting signal line Bq0B or Bq1B of the corresponding complementary bit line, respectively. Ru. P-channel MOSFETQ2
Although not particularly limited, the sources of Q3 and Q3 are commonly coupled to a common source line CSP, and are further coupled to the power supply voltage of the circuit via a P-channel drive MOSFET Q1. Similarly, N-channel MOSFETs Q12 and Q1
The three commonly coupled sources are commonly coupled to a common source line CSN, and are further connected to an N-channel drive MOSFE.
It is coupled to the ground potential of the circuit via TQ11. Drive M
The gate of OSFETQ11 is connected to the internal control signal PA.
is supplied, and the inverted signal of the internal control signal PA by the inverter circuit N1 is supplied to the gate of the drive MOSFET Q1. This allows the drive MOSFETs Q1 and Q1
1 is selectively turned on when the internal control signal PA is set to a high level, and all unit amplification circuits of the sense amplifier SA are put into operation at the same time. In this operating state, each unit amplifier circuit of the sense amplifier SA amplifies minute read signals output from a plurality of memory cells coupled to a selected word line of the memory array MARY via the corresponding complementary bit line. , a high level or low level binary readout signal.

MOSFETs Q14 to Q1 constitute the bit line precharge circuit of each unit circuit of the sense amplifier SA.
An internal control signal PC is commonly supplied to the gates of 6 and 6. Further, a predetermined precharge voltage HVC is commonly supplied to the commonly coupled sources of the MOSFETs Q15 and Q16 from a constant voltage generation circuit (not shown) of the dynamic RAM. Here, the precharge voltage HVC is
Although not particularly limited, it is set to approximately an intermediate potential between the power supply voltage of the circuit and the ground potential. As a result, MOSFETs Q14 to Q16 constituting the bit line precharge circuit are selectively turned on when the internal control signal PC is set to high level, and the corresponding complementary bit lines Bq0 and Bq1
The non-inverting and inverting signal lines such as , etc. are set to a half precharge level such as the precharge voltage HVC.

On the other hand, one of the writing switch MOSFETs Q17 and Q18 and Q19 and Q20 provided in each unit circuit of the sense amplifier SA is coupled to a non-inverting or inverting signal line such as the corresponding complementary bit line Bq0 or Bq1, respectively. , and the other are sequentially commonly coupled to the non-inverted or inverted signal line of the write common IO line WIO0 or WIO1, although this is not particularly limited. The gates of these switch MOSFETs are commonly coupled in two sets,
A corresponding bit line selection signal YWq and the like are supplied from the Y address decoder YAD. This allows the switch MOS
FETQ17 and Q18 and Q19 and Q20 are
When the corresponding bit line selection signal YWq, etc. is set to high level, it is selectively turned on, and the corresponding unit amplifier circuit, that is, the corresponding complementary bit line Bq0 or Bq1, etc. and the write common IO line WIO0 or WIO1 are switched on. Selectively connect. In other words, in the dynamic RAM of this embodiment, the complementary bit lines constituting the memory array MARY are grouped into two groups, and the write common IO line is connected to the two complementary bit lines constituting each bit line group as a unit. Connection between WIO0 and WIO1 or read common IO lines RIO0 and RIO1, which will be described later, is selectively realized.

Read switch MOSFETs Q21 and Q22 provided in each unit circuit of the sense amplifier SA
The gates of Q23 and Q24 are respectively coupled to a non-inverting or inverting signal line such as the corresponding complementary bit line Bq0 or Bq1, and their commonly coupled sources are coupled to the ground potential of the circuit. Also, these switches MOSF
The drain of ET is connected to another set of corresponding switch MOS
It is sequentially coupled to the non-inverted or inverted signal line of the read common IO line RIO0 or RIO1 via FETs Q25 and Q26 or Q27 and Q28. MOSFET
The gates of Q25 and Q26 and Q27 and Q28 are commonly connected in two sets in sequence, and are connected to the Y address decoder YA.
A corresponding bit line selection signal YRq and the like are supplied from D. This allows switch MOSFETs Q25 and Q26 to
Also, Q27 and Q28 are selectively turned on when the corresponding bit line selection signal YRq, etc. is set to high level, and select the corresponding complementary bit line Bq0 or Bq1, etc. and the read common IO line RIO0 or RIO1. connected state. At this time, MOSFETs Q21 and Q22 and Q23 and Q24 are so-called sense M
Acts as an OSFET, and the corresponding complementary bit line Bq0
The binary readout signal established as a voltage signal in Bq1 is read out as a current signal by the common IO line R.
Transfer to IO0 and RIO1. As a result, the read common IO line RIO0 is coupled with a relatively large parasitic capacitance.
The voltage amplitude of RIO1 and RIO1 is compressed, and the dynamic type R
AM read operation is sped up.

By the way, the dynamic type R of this embodiment
In AM, as shown in FIG.
Non-inverted signal line of O lines WIO0 and WIO1, that is, WI
O0 and WIO1 and the inverted signal line ie WIO0B
and WIO1B are arranged adjacent to each other, and the complementary bit lines constituting the memory array MARY are connected to one write common IO line WIO0 or WIO1 of the two sets of complementary bit lines constituting each bit line group. Complementary bit lines Bp0 and Bq0, Bq1 and Br1, etc. are arranged adjacent to each other. In addition, two pairs of write switches M of the sense amplifier SA are turned on at the same time.
OSFETQ17 and Q18 and Q19 and Q20
are arranged in a staggered manner with respect to the extending direction of the complementary bit line, and in the N-type diffusion layers N1 to N4 in which these switch MOSFETs are formed, are provided corresponding to the adjacent complementary bit line Bp0 or Br1. Write switch MOS
FETs (Q17) and (Q18) and (Q19) and (Q20) are formed, respectively. Each switch MOS
The gate of the FET is formed of polysilicon, although not particularly limited, and is arranged in a so-called vertical manner substantially parallel to the write common IO lines WIO0 and WIO1, as shown by diagonal lines in FIG. The two pairs of switch MOSFETs are grouped together and commonly connected in a staggered manner, and then connected to corresponding bit line selection signal lines YWp to YWr, etc. via contacts C13 to C15. Furthermore, in this embodiment, two switch MOSFs forming a pair
Contacts C3 and C4 or C5 and C6 for coupling ETQ17 and Q18 or Q19 and Q20 with a non-inverted or inverted signal line such as the corresponding complementary bit line Bq0 or Bq1 are both on the left or right side of the corresponding gate, that is, are placed in the same direction of the corresponding gate. Note that each complementary bit line is further connected to a read sense MOSFET Q2 on the left side of FIG.
Needless to say, it will be extended to gates 1 to Q24.

As a result, in the dynamic RAM of this embodiment, even if misalignment occurs in the mask for forming the gate of the write switch MOSFET of the sense amplifier SA during its manufacturing process, the problem can be corrected. Switch MOSFET Q17 and Q1
The diffusion layer areas of Q8, Q19, and Q20 can be similarly increased or decreased without impairing the balance of the parasitic capacitances coupled to the non-inverting and inverting signal lines of the corresponding complementary bit lines. As a result, it is possible to maintain a balance between the read signal amounts of the non-inverted and inverted signal lines of each complementary bit line, thereby stabilizing the read operation of the dynamic RAM. Also, as is clear from Figure 3,
Two corresponding pairs of switch MOSFETs Q17 and Q18
The gates of Q19 and Q20 are commonly coupled, and the contact with the corresponding bit line selection signal line is shared, and the write common IO lines WIO0 and WI
Contacts C9 to C1 for coupling the non-inverted or inverted signal line of O1 to the diffusion layers of two adjacent sets of complementary bit lines
The second class is shared in the same way, and the sense amplifier S
The required layout area of A is reduced.

Let us return to the explanation of FIG. Although not particularly limited, the Y address decoder YAD is supplied with j-bit internal address signals Y1 to Yj from the Y address buffer YAB, and receives an internal control signal YD from the timing generation circuit TG.
G is supplied. Further, the Y address buffer YAB is supplied with j+1 bit Y address signals AY0 to AYj via external terminals AY0 to AYj, and is supplied with an internal control signal AL from the timing generation circuit TG.

Although not particularly limited, the Y address decoder YAD is selectively brought into operation when the internal control signal YDG is set to a high level. In this operating state, the Y address decoder YAD outputs the internal address signal Y1.
~ Yj is decoded and the corresponding bit line selection signal Y is
Wq or YRq is alternatively set to high level. As described above, these bit line selection signals are applied to the corresponding two pairs of write switches MOSF of the sense amplifier SA.
ET or readout switch MOSFET, respectively. Y address buffer YAB is connected to external terminal AY
Y address signal AY0~ supplied via 0~AYj
AYj is taken in and held in accordance with internal control signal AL, and internal address signals Y0 to Yj are formed based on these Y address signals. Of these, although not particularly limited, the lowest bit internal address signal Y0 is supplied to the write amplifier WA and read amplifier RA, and the remaining internal address signals Y1 to Yj are supplied to the Y address decoder Y.
Supplied to AD.

Next, the writing common IO lines WIO0 and WIO1 and the reading common IO lines RIO0 and RIO1 to which two specified sets of complementary bit lines of the memory array MARY are selectively connected are not particularly limited; They are respectively coupled to corresponding unit circuits of write amplifier WA and read amplifier RA. Here, the write amplifier WA is, although not particularly limited, a write common I.
Two unit circuits are provided corresponding to O lines WIO0 and WIO1 and selectively specified according to the internal address signal Y0 of the least significant bit. These unit circuits are commonly supplied with the internal control signal WE from the timing generation circuit TG, and their input terminals are coupled to the data input/output terminal Din via the data input buffer DIB. Similarly,
Although not particularly limited, the read amplifier RA includes two unit circuits provided corresponding to the read common IO lines RIO0 and RIO1 and selectively specified according to the internal address signal Y0. These unit circuits are commonly supplied with the internal control signal RE from the timing generation circuit TG, and their output terminals are coupled to the data output terminal Dout via the data output buffer DOB.

The two unit circuits constituting the write amplifier WA are alternatively put into an operating state when the internal control signal WE is set to a high level and the internal address signal Y0 is set to a high level or a low level. In this operating state, each unit circuit of the write amplifier WA forms a predetermined write signal based on the write data input from the data input/output terminal Din via the data input buffer DIB, and outputs the corresponding write common IO. Line WIO0 or WIO
1 to two selected memory cells of the memory array MARY. Similarly, the two unit circuits constituting the read amplifier RA are alternatively put into an operating state when the internal control signal RE is set to a high level and the internal address signal Y0 is set to a high level or a low level. In this operating state, each unit circuit of read amplifier RA is
Corresponding read common IO line RIO0 or RIO from two selected memory cells of memory array MARY
1 is further amplified and sent from the data output buffer DOB via the data output terminal Dout.

The timing generation circuit TG forms the above-mentioned various internal control signals based on the row address strobe signal RASB, column address strobe signal CASB, and write enable signal WEB supplied as activation control signals from the outside, and dynamically generates the various internal control signals. It is supplied to each part of the mold RAM.

FIG. 4 shows a partial circuit diagram of a second embodiment of a sense amplifier included in a dynamic RAM to which the present invention is applied, and FIG. 5 shows a partial circuit diagram of a second embodiment of the sense amplifier. A layout diagram is shown. Note that this embodiment basically follows the embodiments shown in FIGS. 2 and 3 above, and therefore, an explanation will be added regarding the different parts.

In FIG. 4, the dynamic RAM of this embodiment includes two sets of common IO lines IO0 and IO1 which are used for both writing and reading, although this is not particularly limited. These common IO lines are connected to two pairs of switch MOSFETs Q29 and Q30 and Q3 that are selectively turned on according to a bit line selection signal YSq, etc.
1 and Q32, it is selectively connected to two specified sets of complementary bit lines Bq0 and Bq1, etc. In this embodiment, the non-inverted signal lines of the common IO lines IO0 and IO1, that is, IO0 and IO1, and the inverted signal lines, that is, IO0B and IO1B, are arranged adjacent to each other as illustrated in FIG. The constituent complementary bit lines are connected to one common IO line IO0 or I out of two sets of complementary bit lines constituting each bit line group.
Complementary bit lines Bp0 and Bq0, etc., or Bq1 and Br1, etc. connected to O1 are arranged adjacent to each other. In addition, two pairs of switches MOSF corresponding to the sense amplifier SA
ETQ29 and Q30 and Q31 and Q32 are arranged in a staggered manner with respect to the extending direction of the complementary bit line, and are connected to an N-type diffusion layer N5 in which these switch MOSFETs are formed.
~N8 includes adjacent complementary bit lines Bp0 or Br1.
Write switch MOSFE provided corresponding to etc.
T(Q29) and (Q30) and (Q31) and (
Q32) are formed respectively. Each switch MOSFE
As shown by diagonal lines in FIG. 5, the gates of T are arranged in a so-called vertical manner substantially in parallel with the common IO lines IO0 and IO1, and the gates of the corresponding two pairs of switch MOSFETs
After the ETs are commonly coupled in a staggered manner as one group, they are coupled to corresponding bit line selection signal lines YSp to YSr, etc. via contacts C28 to C30. Furthermore, two switch MOSFETs Q29 and Q30 or Q3 that form a pair
Complementary bit line Bq0 or Bq1 corresponding to 1 and Q32
A contact C1 that couples with a non-inverted or inverted signal line such as
8 and C19 or C20 and C21 are both arranged in the same direction of the corresponding gate. As a result, even in a dynamic RAM in which the common IO line is shared for writing and reading, FIGS.
It is possible to obtain the same effect as in the embodiment.

By the way, the sense amplifier SA of this embodiment
does not include a read switch MOSFET, and the non-inverting and inverting signal lines of each complementary bit line can be disconnected at the corresponding contacts C18 to C21, etc. However, in this embodiment, the non-inverting and inverting signal lines of all complementary bit lines are extended to positions close to far-end contacts C18, C22, etc. so that they are approximately the same length. As a result, the parasitic capacitances of the non-inverted and inverted signal lines of each complementary bit line are further balanced, and the read operation of the dynamic RAM is further stabilized.

FIG. 6 shows a partial circuit diagram of a third embodiment of a sense amplifier included in a dynamic RAM to which the present invention is applied, and FIG. 7 shows a partial circuit diagram of one embodiment. A layout diagram is shown. Hereinafter, explanations will be added regarding parts that are different from the embodiments shown in FIGS. 2 to 6 above.

In FIG. 6, the dynamic RAM of this embodiment includes a set of common IO lines IO that are used for both writing and reading, although this is not particularly limited. This common IO line IO selectively connects to a designated complementary bit line Bq, etc. via switch MOSFETs Q29 and Q30, which are selectively turned on when the corresponding bit line selection signal YSq, etc. is set to high level. connected to. In this embodiment, a pair of two switches M
As shown by diagonal lines in FIG. 7, the gates of OSFETs Q29 and Q30 are arranged in a so-called vertical manner substantially parallel to the common IO line IO, and are connected to the corresponding bit line selection signal lines YSp through contacts C43 to C48. It is combined with YSr etc. In addition, two switch MOSFETs forming a pair
Complementary bit line Bq corresponding to the diffusion layer of Q29 and Q30
Contacts C33 and C34 for coupling with non-inverted or inverted signal lines such as the above are both arranged in the same direction of the corresponding gate. The non-inverting and inverting signal lines of all the complementary bit lines are extended to positions close to the far-end contacts C32, C34, C36, C38, etc. so that they have approximately the same length. As a result, a set of common IO
Even in a dynamic RAM with a line, as shown in Figure 2 above,
- The same effects as the embodiment shown in FIG. 5 can be obtained.

As shown in the above embodiment, the following effects can be obtained by applying the present invention to a semiconductor memory device such as a dynamic RAM having a common IO line and a sense amplifier. That is, (1) Common I
The gates of the switch MOSFETs that selectively connect the O line and designated complementary bit lines are arranged in a so-called vertical manner substantially parallel to the common IO line, and these switch MOS
By arranging the contacts that connect the non-inverted and inverted signal lines of the FET diffusion layer and the corresponding complementary bit line in the same direction of the corresponding gate, even if mask misalignment occurs during the formation of the switch MOSFET gate, the complementary The area of the diffusion layer corresponding to the non-inverted and inverted signal lines of the bit line can be changed in the same way, and an effect can be obtained in that the parasitic capacitance thereof can be prevented from becoming unbalanced. (2) According to the above item (1), it is possible to balance the read signal amounts of the non-inverted and inverted signal lines of the complementary bit lines, thereby stabilizing the read operation of a dynamic RAM or the like. (3) In paragraphs (1) and (2) above, when multiple pairs of common IO lines are provided in a dynamic RAM, etc., the non-inverted signal line and the inverted signal line of the two corresponding sets of common IO lines are Placed adjacently and with the same common I
By arranging two sets of complementary bit lines connected to the O line adjacent to each other, and arranging two pairs of switch MOSFETs that are turned on at the same time in a staggered manner in the direction of extension of the complementary bit lines, The contacts connecting the gates of the two pairs of switch MOSFETs that are turned on at the same time and the corresponding bit line selection signal lines are shared, and each common I
An effect is obtained in that a contact for coupling the non-inverted or inverted O-line signal line and the diffusion layers of two adjacent switch MOSFETs can be shared. (4) According to the above item (3), it is possible to reduce the required layout area of the sense amplifier and reduce the chip area of the dynamic RAM. (5) In items (1) to (4) above, if the common IO line is used as a common IO line for writing and reading, the non-inverting and inverting signal lines of all complementary bit lines should be made to have approximately the same length. By extending the line as close as possible to the far end contact, the parasitic capacitance of the non-inverting and inverting signal lines of each complementary bit line can be further balanced, and the read operation of the dynamic RAM can be further stabilized. This effect can be obtained.

[0032] Above, the invention made by the present inventor has been specifically explained based on examples, but this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. It goes without saying that there is. For example, in FIG. 1, the memory array of the dynamic RAM and its peripheral circuits may be composed of a plurality of memory mats. Further, the dynamic RAM can have a so-called multi-bit configuration in which multiple bits of storage data are simultaneously input and output, and can also have a so-called address multiplex system. Dynamic type R
For example, the AM can be provided with four sets of common IO lines, and its block configuration is not limited by this embodiment. In FIGS. 2, 4, and 6, the dynamic RAM can adopt a so-called shared sense method. In this case, each switch MOSFET of the sense amplifier SA serves to selectively connect the common IO line and the complementary input/output node of the unit amplifier circuit corresponding to the designated complementary bit line. In Figures 3, 5, and 7, the common IO line and each switch MOSFET
The layout can be arranged in any manner as long as it satisfies some of the constraints mentioned above. Further, the specific circuit configuration, the polarity of the power supply voltage, the conductivity type of the MOSFET, etc. of the sense amplifier SA shown in FIGS. 2, 4, and 6 may be modified in various embodiments.

In the above explanation, the invention made by the present inventor was mainly applied to a dynamic RAM, which is the field of application that formed the background of the invention.
It is not limited to this, for example, Bi/CMO
It can also be applied to various semiconductor memory devices such as S dynamic RAM and multiport RAM. This invention provides at least a common IO line and a bit line selection switch MO.
The present invention can be widely applied to semiconductor memory devices equipped with sense amplifiers including SFETs and digital integrated circuit devices incorporating such semiconductor memory devices.

[0034]

Effects of the Invention A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, a switch MOSFET that selectively connects the common IO line and a designated complementary bit line.
The gates of the switch MOSFETs are arranged in a so-called vertical arrangement substantially parallel to the common IO line, and contacts connecting the diffusion layers of these switch MOSFETs and the non-inverting and inverting signal lines of the corresponding complementary bit lines are connected to the gates of the corresponding gates. By arranging them in the same direction, even if mask misalignment occurs when forming the gate of the switch MOSFET, the parasitic capacitance of the non-inverting and inverting signal lines of the complementary bit line can be changed in the same way, and imbalance can be prevented. . As a result, the read signal amounts of the non-inverted and inverted signal lines of the complementary bit lines can be balanced, and the read operation of a dynamic RAM or the like can be stabilized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a partial circuit diagram showing a first embodiment of a sense amplifier included in the dynamic RAM of FIG. 1;

FIG. 3 is a partial layout diagram showing one embodiment of the sense amplifier of FIG. 2;

FIG. 4 is a partial circuit diagram showing a second embodiment of a sense amplifier included in a dynamic RAM to which the present invention is applied.

FIG. 5 is a partial layout diagram showing one embodiment of the sense amplifier of FIG. 4;

FIG. 6 is a partial circuit diagram showing a third embodiment of a sense amplifier included in a dynamic RAM to which the present invention is applied.

FIG. 7 is a partial layout diagram showing one embodiment of the sense amplifier of FIG. 6;

FIG. 8 is a partial layout diagram showing an example of a sense amplifier included in a conventional dynamic RAM.

[Explanation of symbols]

MARY...Memory array, SA...Sense amplifier, XAD...X address decoder, YAD...Y address decoder, XAB...X address buffer, Y
AB...Y address buffer, WA...write amplifier, RA...read amplifier, DIB...data input buffer, DOB...data output buffer, TG...
・Timing generation circuit. Q1~Q3...N channel MOSFET, Q11~Q32...N channel MOSFET
SFET, N1...Inverter circuit. WIO0~WI
O1, RIO0~RIO1, IO0~IO1, IO...
・Common IO line, Bo~Bs, Bp0~Bp1, Bq0
~Bq1, Br0~Br1... Complementary bit line, YWp
~YWr, YRq, YSo~YSs...Bit line selection signal line, N1~N14...N type diffusion layer, Go~Gs.
...Gate, C1-C67...Contact.

Claims (7)

[Claims] 1. A memory array including a plurality of word lines and complementary bit lines arranged orthogonally, and a complementary bit line provided corresponding to the complementary bit line and designated as a common IO line. Multiple pairs of switch MOS to connect
a sense amplifier including a FET, and contacts connecting the diffusion layers of the two switch MOSFETs forming a pair with the non-inverting and inverting signal lines of the corresponding complementary bit lines are arranged in the same direction of the corresponding gates. A semiconductor memory device characterized in that: 2. The gate substantially includes the common I
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed parallel to the O-line. 3. The non-inverting and inverting signal lines of the complementary bit line are extended to the vicinity of the contact disposed at the far end so as to have substantially the same length, respectively. 2. Semiconductor storage device. 4. The common IO lines are provided in one or more pairs, and the non-inverted and inverted signal lines of the two pairs of common IO lines are arranged adjacent to each other. , two sets of complementary bit lines connected to one of the two pairs of common IO lines are arranged adjacent to each other, and the two sets of complementary bit lines designated as the two pairs of common IO lines are arranged adjacently to each other. Two pairs of the above switches M connecting with the bit line
Claim 1, wherein the OSFETs are arranged in a staggered manner with respect to the extending direction of the complementary bit line.
, a semiconductor memory device according to claim 2 or claim 3. 5. Two pairs of the above-mentioned switch MOS provided corresponding to two sets of complementary bit lines which are simultaneously selected.
A contact that connects the gate of the FET and the corresponding bit line selection signal line, and two sets of the above common IO that form a pair.
Claim 1, wherein the contacts connecting the two pairs of complementary bit lines connected to one of the lines and arranged adjacently to the corresponding common IO line are shared. A semiconductor memory device according to claim 2, claim 3, or claim 4. 6. The semiconductor memory device includes a common IO line for writing and a common IO line for reading, and the common IO line is a common IO line for writing. 1, Claim 2, Claim 3
, the semiconductor memory device according to claim 4 or claim 5. 7. Claims 1 and 2, wherein the semiconductor memory device is a dynamic RAM.
A semiconductor memory device according to claim 3, claim 4, claim 5, or claim 6.