KR0184513B1 - Semiconductor memory device - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

The present invention relates to a semiconductor memory device.

2. The technical problem the invention is trying to solve:

The present invention provides a semiconductor memory device having a pair of data lines shared for outputting or writing data of a plurality of memory array blocks simultaneously sensed without using a direct sense amplifier.

3. Summary of the Solution of the Invention:

According to the present invention, a plurality of memory arrays, a plurality of memory array blocks including the memory arrays, a plurality of bit line pairs in which the memory rows are connected in a thermal manner, and the bit line pairs are selectively selected by column addresses Each of a plurality of first data line pairs connected to each other to transmit predetermined data, and second data line pairs selectively connected to the first data line pair by a row or column block address to transmit the data; A first connection means connected to each of the plurality of memory array blocks in a row direction each to a pair of bit lines in the memory array block to connect the pair of bit lines and the pair of first data lines; The first data line pair and the second data line pair are connected to each other and the data is stored in the second data line. A second connection means for multiplexing and transferring to another line pair, and precharge means for precharging the first data line pair by being connected to a plurality of the first data line pairs, respectively. do.

4. Important uses of the invention:

The present invention is suitably used for a semiconductor memory device.

Description

Semiconductor memory device

1 is a block diagram of a data line according to the prior art.

FIG. 2 is a detailed circuit diagram illustrating a connection between a local input / output line pair and a bit line pair of FIG.

3 is a detailed circuit diagram showing the multiplexer of FIG.

4 is a block diagram of a data line according to the present invention.

FIG. 5 is a detailed circuit diagram illustrating a connection of a local input / output line pair and a bit line pair of FIG.

6 is a detailed circuit diagram showing the multiplexer of FIG.

7 is a detailed circuit diagram of the local input / output line precharge circuit of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a local input / output line pair connected to a bit line pair in each memory array block, for example, a first data line pair and a global input / output line pair connected thereto, for example, a second data write pair. The present invention relates to a semiconductor memory device capable of reducing a layout by connecting a multiplexer therebetween.

In general, as the capacity of the dynamic random access memory is increased to 64 megabits or more, the length of the data line from the memory cell to the output buffer becomes longer. As the number of data lines increases, the delay in the data lines is reduced and the layout area occupied by the data lines and the data line control circuits is one of the very important techniques in memory design. In order to reduce the delay of long data lines in recent years, conventional voltage type data sense amplifiers have been replaced by current type data sense amplifiers, and data lines in a memory cell array block are also connected to local input / output lines and globally. It has a hierarchical structure of input and output lines, one of which is published in ISSCC in 1991 by FUJISU and is shown in Figures 1 and 2. 1 is a configuration block diagram of a data line according to the prior art. Referring to FIG. 1, there are 2N memory array array blocks composed of a plurality of blocks BLKIA to BLKNA and BLKIB to BLKNB, and two hatched blocks are selected simultaneously by a row address. Sense amplifiers of unbited bit lines sense. Each array block is further divided into small segments, each segment has a local input / output line LIO, and is selected for output of column decoder 3 and read and write conditions. Column Selection Line CSL pairs (R / W) are all input to the 2N array blocks. Bit lines to which memory pins are connected are connected to a local input / output line pair LIO and LIOB through a connecting means 10, and local input / output line pair LIO LIOBs are connected to a global input / output line pair GIO and GIOB through a connecting means 20. An input / output current sense amplifier 30 is connected to the ends of the input / output line pairs GIO and GIOB to sense the selected data and output it to an output buffer.

FIG. 2 is a detailed circuit diagram illustrating a connection between a local input / output line pair and a bit line pair of FIG. Referring to FIG. 2, the direct sense amplifier 7 of the NMOS transistors MN1 to MN6 is replaced by the conventional CMOS latch type bit line sense amplifier 5 composed of the NMOS transistors MN7 to MN8, the PMOS transistors MP1 and MP2. It is additionally used. The operation of the direct sense amplifier 7 is that the column select line CSL (R) is selected by the column address at read time so that the EnMOS transistors MN2 and MN4 are turned on, and the EnMOS transistors MNI and MN3 are connected to the bit line pairs BL and BLB. If the state of the bit line is logical "high" because of the connection, the NMOS transistor MNI is turned on and the complementary local I / O line LIOB of the local I / O line pair LIO, LIOB is logical "Low", If line BL is logic “low”, that is, complementary bitline BLB is logic high, then NMOS transistor MN3 is turned on, causing local input / output line LI0 to be logic low. At the time of writing, the column select line CSL (W) is logic high, and the EnMOS transistors MN5 to 6 are turned on, and data input through the local input / output line pairs LIO and LIOB is written to the bit line pairs BL and BLB.

3 is a detailed circuit diagram showing the multiplexer of FIG. Referring to FIG. 3, the transmission module 15 is composed of a CMOS type transmission gate 15 and an inverter 25 having an input terminal connected to the NMOS side of the transmission gate 15 and an output terminal connected to the PMOS side. BLSI (I = OA to NB) is input as an input control signal to connect one of 2N local input / output line pairs LIO and LIOB to the global input / output line pair GIO and GIOB.

This conventional technique shares a global data line, for example, a global input / output line GIO with 2N blocks, but when the column select line is selected as a logic high, the data of the bit line BL in the block BLKOA and the block BLKOB is transferred to the local input / output line LIO. At the same time, the data on the selected local input / output line LIO is output through the global input / output line GIO to an input thrust current sandwich amplifier. Therefore, the voltage difference between the local I / O line pair LIO and LIOB is very small, so that the local I / O line LIO need not be precharged even if the column select line CSL changes as the column address changes, but the local I / O line pair is not selected. When the data of the bit line BL connected to the changed column selection line CSL is different from the data of the local I / O line LIO, the LIO and LIOB are changed to the data of the bit line BL, thereby causing a problem.

The above-described direct sense amplifier is added to a conventional CMOS bit line sense amplifier, and as shown in FIG. 2, the number of transistors increases, so that the layout is greatly increased, making it difficult to apply to a product. Therefore, in order to have a shared global line without using the direct sand amplifier, the aforementioned problem must be eliminated. In addition, the above-mentioned problem becomes worse due to a relatively large loading when the size of the segment is large and the length of the local input / output line LIO is long.

Accordingly, an object of the present invention is to provide a semiconductor memory device having a pair of data lines shared for outputting or writing data of a plurality of memory array blocks simultaneously sensed without using a direct sense amplifier.

According to the spirit of the present invention for achieving the above objects, a plurality of memory arrays, a plurality of memory array blocks including the memory arrays, a plurality of bit line pairs in which the memory arrays are connected in a column direction; And the plurality of bit line pairs are selectively connected to each other by a column address to selectively transmit data, and the plurality of first data line pairs are selectively connected to the first data line pair by row or column block addresses. 10. A semiconductor memory device comprising a second data line pair for transferring data, wherein each of the first data line pairs is connected with a plurality of the memory array blocks in a row direction so as to correspond to bit lines in the memory array block. A pair of the bit line pair and the first data line pair A first connection means for connecting the first data line pair, a second connection means for connecting the first data line pair and the second data line pair, and multiplexing and transferring the data to the second data line pair; And precharge means for precharging the first data line pair, one connected to each of the first data line pairs.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the drawings represent like reference numerals wherever possible.

4 is a configuration block diagram of a data line according to the present invention. Referring to FIG. 4, each memory array block BLKOA to BLKNB and a plurality of column selection line CSLs of each of the blocks are local input / output lines as many as a predetermined memory array block group connected by the first connection means 100. Pair LIO, LIOB, the local I / O line pair LIO, LIOB are connected to the global I / O line pair GIO, GIOB connected by the second connection means 200, and for each local I / O line pair LIO, LIOB to perform precharge. For precharge means 500. On the other hand, the column select line CSL, which is the output of the column decoder, is selected only by the column address regardless of lead or write, and is input to all 2N array blocks of blocks BLKOA to BLKNB. The main difference in construction compared to the prior art is that the local input / output line LIOs are connected in one long over several segments, and there is a precharge means 300 for each of the local input / output line pairs LIO and LIOB.

FIG. 5 is a detailed circuit diagram illustrating a connection of a local input / output line pair and a bit line pair of FIG. 4. Referring to FIG. 5, the first connection means 100 of FIG. 4 is shown, and a general sense composed of a type sense amplifier including PMOS transistors MP1 'and MP2' and an N type sense n composed of enMOS transistors MN3 'and MN4'. It consists of only CMOS transistor latch sense amplifier 300 and switching transistors MN1 'and MN2' which connect bit line pair BL and BLB to local input / output line pair LIO and LIOB and gate select line CSL as gate input. The direct sense amplifiers used in the package are not used.

6 is a detailed circuit diagram showing the multiplexer of FIG. Referring to FIG. 6, the same configuration as that of the multiplexer in FIG. 3 is selected, and general array block selection information BLSI (I = OA to NB) is selected.

FIG. 7 is a detailed circuit diagram of the local input / output line precharge circuit of FIG. Referring to FIG. 7, PMOS transistors MP4 ′ and MP5 ′, which are precharge transistors, are connected to each other by gates, and respective drains are connected to local input / output line pairs LIO and LIOB, respectively. The gate of the equalizing transistor, for example, the PMOS transistor MP6 'has a structure controlled by the control signal OIOPi from the block selection information BLSjB. OIOPi, which is a control signal of the equalization transistor, receives block selection information BLSj and lead and write selection signal OWRB. That is, the bit line sense amplifiers of two or more array blocks selected by the low address are sensed, and among them, the local I / O line LIO selected to read or write by the column block address operates in the same manner as the prior art, but the column block address The local I / O line LIO of the block not selected by the block is changed to a column address because the control signal OIOPi is enabled as a logic “low” to precharge the local I / O line to the external power supply voltage Vcc. Even if the line CSL is changed, the conventional problem that the data of the newly selected bit line pair is changed by the data of the local I / O lines LIO and LIOB can be solved. Accordingly, the BLSj input of the OIOPi includes not only a row block address but also a column block address. The precharge means of the local input / output line LIO, for example, the precharge circuit 500 may be used for post-write precharge. A further aspect of the present invention relates to a layout method in an array block of the connection means 200 of the bit line and the local input / output line, for example, and the local input / output line precharge means 300. As can be seen, both are located between array blocks, which is advantageous in that layout is facilitated by placing them apart rather than at the same sub-block intersection. According to the above-described technique of the present invention, even when using a conventional CMOS flat bit line sense amplifier, it is possible to use a shared global data line in two or more array blocks simultaneously sensed by bit lines, thereby enabling high-speed and data lines and the like. The layout area of the control circuit can be reduced, and the problem of the layout of the array block of the connecting means and the precharge means can be solved.

Although the present invention described above is limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the present invention.

Claims (5)

A plurality of memory cells, a plurality of memory array blocks including the memory cells, a plurality of bit line pairs in which the memory cells are connected in a column direction, and the bit line pairs are selectively connected by column addresses, respectively. A semiconductor memory device comprising a plurality of first data line pairs for transferring predetermined data, and second data line pairs selectively connected to the first data line pairs by row or column block addresses to transfer the data. And a plurality of the memory array blocks in a row direction are connected to each of the first data line pairs, respectively, to each of the bit line pairs in the memory array block. First connecting means for connecting the first data line pair and the second data; Second connection means for connecting the pairs and multiplexing the data to the second data line pair, and connected to the plurality of first data line pairs, respectively, to precharge the first data line pair. And a precharge means for arging the semiconductor memory device. The semiconductor memory device according to claim 1, wherein the first connecting means and the second connecting means are located between or on the memory array block. 2. The semiconductor memory device according to claim 1, wherein said precharge means inputs a row block address and a column block address. The semiconductor memory device according to claim 1, wherein the second connection means is located between the memory array blocks having different precharge means in the first data line pair. 2. The semiconductor memory device according to claim 1, wherein said precharge means precharges said first data line pair after said write using write information as an input.