JPH04252493A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the number of switch, to perform the layout for the sense amplifier in a small area and to miniaturize the size of whole memory chip by sharing a switch for activation in a sense amplifier to plural sense amplifiers. CONSTITUTION:When a sense activated signal SE is made to a high level voltage and nMOSFETQ1 is made 'on' state in the case of activating sense amplifiers 2, 3, the voltage in the common source terminals N1, N2 becomes low level simultaneously and the sense amplification between bit line pairs is performed. As the switch Q1 for activation in the amplifiers 2, 3 is shared to the amplifiers 2, 3 in such a manner, the number of switch used for one bit line pair is decreased and the matching of the pitch in the direction of the word line in amplifiers 2, 3 with the pitches in memory cells 4-7 is facilitated. Thus, the layout in the sense amplifier can be performed in a small area and the size of whole chip is miniaturized.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor memory device.
Particularly regarding large capacity random access memories.

0002

[Prior Art] Conventionally, one-transistor type dynamic
Random access memory (hereinafter referred to as DRAM)
transmits the charge stored in the storage capacity of the memory cell to the bit line via the switch transistor, and amplifies the signal with a highly sensitive sense amplifier to produce an output signal. A method of rewriting the signal is used. This DRAM has been developed as a high-capacity, cutting-edge memory that takes advantage of the ability to miniaturize memory cells. However, in order to increase the capacity and performance of DRAMs, improvements in sense amplifiers are being actively carried out.

An example of such a high-performance DRAM is the 1989 Symposium on VLSI Circuits held in May 1989.
ONVLSI CIRCUITS) Digest of Technical Papers (DIGEST)
OF TECHNICAL PAPERS) 1st
"AN EXPERIMENTAL 1" published on pages 13-114 (distributed simultaneously at the May 1989 conference)
6Mb DRAM WITH REDUCED
It is introduced in a paper entitled "PEAK-CURRENT NOISE".

FIG. 4 is a circuit diagram of a semiconductor memory device showing an example of such a conventional device. As shown in FIG. 4, this semiconductor memory device includes an X decoder 1, a Y decoder 8, and a bit line pair BL, BL(-) (- indicates an inverted signal. The same applies hereinafter).
and the same number and plurality of memory cells 4 and 5 connected between word lines W1 and W2, respectively, and a sense activation signal S.
nMOSFETQ1,pM controlled by E,SE(-)
A sense amplifier 2 having a flip-flop configuration connected between OSFETQ21 and bit line pair BL, BL(-), complementary input/output data lines I/O, I/O(-) and bit line pair BL, BL(-) It has switching nMOSFETs Q4 and Q5 connected between them. In addition, the sense amplifier 2 is composed of nMOSFETQ2, Q3 and pMOSFETQ.
22, Q23, and the memory cell 4 is connected to the word line W.
1, is connected to the bit line BL, and the memory cell 5 is connected to the word line W2, the bit line BL(-).

DRAM as the above-mentioned semiconductor memory device
First, at the start of memory operation, when the word line selected by the X decoder 1, for example W1, becomes a high level voltage, the information of the selected memory cell 4 is read out to the bit line BL. Note that at this time, the other bit line BL(-) maintains the precharge voltage. As a result, bit line pair BL, BL
(-), a minute potential difference determined by the capacitance division between the memory cell capacitance (Cs) and the bit line capacitance (Cb) is generated, so the sense amplifier 2 is activated and the minute potential difference is amplified.

After that, the column selection line Y1 selected by the Y decoder 8 rises to a high level, so that the information in the memory cell 4 is transferred from the bit lines BL, BL(-) to the input/output data lines I/O, I/O. (-), and reading is completed. Here, in order to activate the sense amplifier 2, the sense activation signal SE is set to a high level voltage, and the nMOSFETQ
1 should be made conductive. That is, nMOSFET
Lower the voltage of the common source terminal N1 of Q2 and Q3, and set the sense activation signal SE (-) to a low level voltage, pMOSFET.
Q21 is made conductive and pMOS pair FETQ22,Q
This is done by increasing the voltage at the common source terminal N3 of 23. At this time, sense activation signals SE, SE(-)
By arranging the drive sources for the word lines W1 and W2 in the same direction as the drive sources for the word lines W1 and W2, even if there is a signal propagation delay time on the word lines W1 and W2, the signal reading from the memory cells 4 and 5 and the sense amplifier 2 can be easily read out. Activation is performed with the same time delay. Therefore, the operating margin is wide and high-speed signal reading can be performed.

[0007]

In the above-mentioned conventional semiconductor memory devices, especially large-capacity DRAMs, memory cells are laid out at a high density in order to maximize the degree of integration. At the same time, it is necessary to reduce the layout pitch of the sense amplifier in the word line direction in order to match the layout pitch with the memory cell.

However, in the conventional example shown in FIG.
Sense amplifier 2 and nMOSFETQ1 and pMOSF
It is very difficult to arrange the ETQ21 at the same layout pitch as the memory cells. If you are forced to layout them at the same pitch, you will have to make the layout length of the sense amplifier 2 in the bit line direction longer than usual, or you will have to arrange the sense amplifier 2 separately on the left and right for each adjacent bit line pair. However, it has the disadvantage of increasing the overall size of the DRAM chip.

An object of the present invention is to provide a semiconductor memory device in which the layout pitch of the sense amplifiers can be relaxed even if the sense amplifier circuits become complicated.

0010

[Means for Solving the Problems] A semiconductor memory device of the present invention includes a plurality of memory cells arranged in a matrix,
a decoder, a plurality of word lines connected to the X decoder and vertically connecting switch gates of the memory cells, a plurality of bit line pairs horizontally connecting bit terminals of the memory cells; One of the bit line pairs of
a Y decoder for selecting a pair; a plurality of sense amplifiers each connected to the plurality of bit line pairs and each including a flip-flop configured with pair transistors; The device includes one sense source terminal line and a second sense source terminal line in which the common source terminals of the pair of transistors constituting the flip-flop are commonly connected to the plurality of adjacent sense amplifiers.

[0011]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic circuit diagram of a semiconductor memory device according to the present invention. As shown in FIG. 1, the semiconductor memory device of the present invention omits input/output data lines and Y decoders, and includes an , BL2(-) and the bit line pair BL1,
BL1(-), BL2, BL2(-) and word line W
The same number of memory cells 4 to 7 are connected between nodes N1 and W2, and nMOSFEs are connected between nodes N1 and N2 and GND and are controlled by a sense activation signal SE.
TQ1 is shown. Note that the memory cells 4 and 5 mentioned above
are word lines W1, W2 and bit line pair BL1, BL1
(-), and memory cells 6 and 7 are connected to word lines W1 and W2 and bit lines BL2 and BL2 (-), respectively. In this DRAM, sense amplifiers 2 and 3 are constructed from the same flip-flop circuit as the sense amplifier 2 in the conventional DRAM (FIG. 4) described above. In this sense amplifier 2, n
The common source terminal of the MOS pair FET is N1, and similarly the common source terminal of the later-described nMOS pair FET of the sense amplifier 3 is N2. They are commonly connected to each other and n
It is connected to ground voltage GND via MOSFET Q1.

The operation of the DRAM described above is basically the same as that of the conventional example, but when activating the sense amplifiers 2 and 3, the sense activation signal SE is set to a high level voltage and nM
The difference is that when OSFET Q1 is made conductive, the voltages at the common source terminals N1 and N2 of sense amplifiers 2 and 3 go low at the same time, and sense amplification between the bit line pair is performed. Furthermore, the operating margin and read speed of memory operations are almost the same as in the conventional example.

However, in the DRAM of the present invention, since the activation switch FET Q1 of the sense amplifiers 2 and 3 is shared by the sense amplifiers 2 and 3, the switch FET for the sense amplifier used per one bit line pair is The number of sense amplifiers 2 and 3 is reduced, and the layout design of the sense amplifiers 2 and 3 becomes easier. As a result, it becomes easy to match the layout pitch of the sense amplifiers 2 and 3 in the word line direction to the layout pitch of the memory cells 4 to 7, and the layout of the sense amplifiers 2 and 3 can be done in a small area. ,D
The overall size of the RAM chip can be reduced.

FIG. 2 is a circuit diagram of a semiconductor memory device showing a first embodiment of the present invention. As shown in FIG. 2, this embodiment shows the circuit of FIG. 1 in more detail, and further includes a decoder 8,
Complementary input/output data lines I/O, I/O(-) and nMOS
FETQ4, Q5, Q8, Q9 and nMOS switch F
ETQ1 and pMOSFETQ21 are added, and sense amplifiers 2 and 3 are shown in a flip-flop configuration. In the DRAM of this embodiment, the common source terminals N1 and N2 of the nMOS pair FETQ2, Q3 and Q6, Q7 of the sense amplifiers 2 and 3 are commonly connected, and the nMOS switch FETQ
1 to the ground voltage GND. Similarly, the common source terminals N3, N4 of the pMOS pairs FETQ22, Q23 and Q24, Q25 of the sense amplifiers 2, 3 are also commonly connected and connected to the power supply voltage VCC via the pMOS switch FETQ21.

The operation of such a DRAM is basically the same as that of the conventional example (FIG. 4) described above, and in this embodiment, the pMOS pair FETQ of the sense amplifiers 2 and 3 is added to the schematic circuit of FIG.
A circuit for commonly connecting the common source terminals of Q22 to Q25 is shown. That is, in the DRAM of this embodiment, the activation switches FETQ1 and Q21 of the sense amplifiers 2 and 3 are shared by the sense amplifiers 2 and 3, so the number of sense amplifier switches used per one bit line pair is also reduced. The sense amplifiers 2 and 3 can be laid out in a small area.

FIG. 3 is a circuit diagram of a semiconductor memory device showing a second embodiment of the present invention. As shown in FIG. 3, this embodiment includes an X decoder 1 and a Y decoder 8 that constitute part of a DRAM, and bit line pairs BL1, BL1(-) and B
L2, BL2(-), sense amplifiers 2, 3, input/output data lines I/O1, I/O1(-) and I/O2, I
/O2(-) and nMOSFETQ4,Q5,Q8,Q
9, nMOS switch FETQ1, Q10, sense activation nMOSFETQ31 and pMOSFETQ3
2. nMOS of these sense amplifiers 2 and 3
The common source terminals N1, N2 of the pair FETs Q2, Q3 and Q6, Q7 are commonly connected, and the nMOSFETQ
1 to the first sense source terminal line SAN, and also to the second sense source terminal line, ie, GND, via the nMOS switch FETQ10. In addition, pMOS pair FETQ2 of sense amplifiers 2 and 3
2, common source terminal N3 of Q23 and Q24, Q25
and N4 are connected to the third sense source terminal line SAP. These first and third sense source terminal lines SAN
, SAP are nMOS switch FETQ11, p, respectively.
It is connected to ground voltage GND and power supply voltage VCC via MOS switch FETQ26.

The memory operation of the DRAM configured as described above is as follows:
This is done as follows. First, when the word line selected by the decoder 1, for example W1, becomes a high level voltage, the information of the selected memory cells 4 and 6 is transferred to the bit lines BL1 and B.
Read out to L2. Note that the other bit line BL1(-),
BL2(-) maintains precharge. As a result, bit line pairs BL1, BL1(-) and BL2, BL2(-)
A minute potential difference is generated between them and activates the sense amplifiers 2 and 3, so that this minute potential difference is amplified. After that, Y
The column selection line Y1 selected by the decoder 8 becomes high level, and the memory cell information is transferred to the bit line pair BL1, BL.
1(-) and BL2, BL2(-) to input/output data lines I/O1, I/O1(-) and I/O2, I/O2
(-), reading is completed. Here, in order to activate the sense amplifiers 2 and 3, first, the sense activation signal SE is set to a high level voltage to make the nMOSFETQ11 conductive, and the nMOS pair FETQ2, Q3 and Q6
, Q7's common source terminals N1 and N2 are connected to the nMOSFETQ1 whose gate is connected to the power supply voltage VCC, the first sense source terminal line SAN, and the nMOSFETQ11.
lower to a low level through. On the other hand, sense activation signal S
E(-) is set to a low level voltage and pMOSFET Q26 is made conductive, thereby raising the voltage of common source terminals N3 and N4 of pMOS pair FETs Q22 to Q25 to a high level via third sense source terminal line SAP and pMOSFET Q26. As a result, sense amplifiers 2 and 3 are activated. Further, the Y decoder 8 selects the column selection line Y.
1 rises to a high level voltage, the nMOS switch FETQ10 also becomes conductive in order to transmit signals from the bit line to the input/output data lines I/O and I/O(-) at high speed, and the common source terminal N1 , N2 quickly drop to a low level, so the sense amplification operation is performed at high speed.

Also in the DRAM of this embodiment, since the activation FETs Q1 and Q10 of the sense amplifiers 2 and 3 are shared by the sense amplifiers 2 and 3, the sense amplifiers 2 and 3 used for each bit line pair are There is an advantage that the number of transistor switches 3 can be reduced, and the layout of the sense amplifiers 2 and 3 can be made in a small area.

In the above two embodiments, the common source terminals of the nMOS pair FETs are commonly connected as the common source terminals of the sense amplifiers, but the common source terminals of the pMOS pair FETs may be commonly connected. , connect both separately and in common, and use nMOS switch FET or pMO
Ground voltage GND or power supply voltage V using S switch FET
The same is possible when connecting to CC. Further, in the above-described embodiment, the case where there are two sense amplifiers whose common source terminals are connected in common has been shown, but it goes without saying that the same can be realized in the case where there are three or more sense amplifiers.

[0021]

As explained above, the semiconductor memory device of the present invention reduces the number of switch transistors in the sense amplifier while maintaining operational performance, allows the sense amplifier to be laid out in a small area, and improves memory efficiency. This has the effect of reducing the overall size of the chip.

[Brief explanation of the drawing]

FIG. 1 is a schematic circuit diagram of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram of a semiconductor memory device showing a first embodiment of the present invention.

FIG. 3 is a circuit diagram of a semiconductor memory device showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a semiconductor memory device showing a conventional example.

[Explanation of symbols]

1
L1(-), BL2, BL2(-)) Bit lines W1, W2 Word lines Q1 to Q11 nMOS transistor (FET)
Q21~Q26 pMOS transistor (FET
) I/O, I/O(-) Input/output data line SE,
SE(-) Sense activation signal SAN, SAP
Sense source lines Y1, Y2 Column selection line VCC Power supply voltage GND Ground voltage

Claims (1)

[Claims] 1. A plurality of memory cells arranged in a matrix, an X decoder, a plurality of word lines connected to the X decoder and vertically connecting switch gates of the memory cells, A plurality of bit line pairs connecting bit terminals in the horizontal direction, a Y decoder for selecting one of the plurality of bit line pairs, and a pair of transistors each connected to the plurality of bit line pairs. a plurality of sense amplifiers including flip-flops; a first sense source terminal line arranged in parallel to the word line via a transistor; A semiconductor memory device comprising a second sense source terminal line commonly connected to the amplifier.