JPH04263345A - Memory access controller - Google Patents

Abstract

PURPOSE:To carry out the access timing at a high speed to a memory at the time of data writing/reading for a memory access controller by performing the data writing/reading to a memory address via a buffer having the access width larger than that of a CPU. CONSTITUTION:A control part 17 stores the memory addresses receiving the access requests from a memory access part 3 very (n) bytes into the memories 8-11 up to (m) pieces of addresses from a CPU 5 included in an access instruction part 2 from a CPU 5 via a system bus 4. Then the part 17 performs the data writing/reading to (m) pieces of memory addresses via the buffers 12-15 having the data access width equivalent to (m) pieces of addresses.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control device, and more particularly to a memory access control device that speeds up access timing when writing and reading data to a memory address.

0002

2. Description of the Related Art Memory access control devices that are applied to conventional computers and the like to speed up memory access are configured, for example, by using high-speed devices that speed up access timing or by using a memory cache system.

0003

[Problems to be Solved by the Invention] However, with such conventional memory access control devices, there is a problem that the use of high-speed devices and memory cache systems increases the cost of the equipment and complicates control. was there. Therefore, an object of the present invention is to speed up access to memory by writing and reading data to and from memory addresses via a buffer.

0004

[Means for solving the problem] The invention according to claim 1 includes:
In a memory access control device that accesses a memory address via a system bus to control data writing and reading, the memory access control device accesses a memory address with an access width of n bytes and controls data reading and writing to the address. It has an access means for instructing and a data access width m times the access width, and stores up to m memory addresses when writing and reading data to and from n-byte memory addresses requested to be accessed by the access means. A storage means constituted by a RAM or the like, a temporary storage means for temporarily storing data written to a memory address stored in the storage means and data read from the memory address, and a memory to which access is requested every n bytes from an access means. 3. A control means for storing up to m addresses in the storage means, and for writing and reading data to and from the m memory addresses via the temporary storage means. The invention relates to a memory access control device that accesses a memory address via a system bus to control writing and reading of data. It has an access means for instructing writing and a data access width m times the access width, and when writing and reading data to and from an n-byte memory address requested to be accessed by the access means, the memory address can be accessed up to m times. A storage means constituted by a RAM or the like for storing data, a temporary storage means for temporarily storing data read from a memory address stored in the storage means, and a storage means for storing a memory address requested to be accessed every n bytes from an access means. The invention according to claim 3 is characterized in that it is characterized by comprising: a control means for storing up to m memory addresses in a system bus, and reading data for the m memory addresses through a temporary storage means. In a memory access control device that controls data writing and reading by accessing a memory address via a memory address, an access means accesses a memory address with an access width of n bytes and instructs reading and writing of data to the address. and a RAM, etc., which has a data access width m times the access width and stores up to m memory addresses when writing and reading data to and from n-byte memory addresses requested by the access means. a temporary storage means for temporarily storing data to be written to the memory addresses stored in the storage means; and a storage means for storing up to m memory addresses to which an access request is made every n bytes from the access means; The invention according to claim 4 is characterized by comprising: a control means for writing data to the m memory addresses via a temporary storage means; A memory access control device that controls writing and reading of data by using an access means that accesses a memory address with an access width of n bytes and instructs reading and writing of data to the address; A storage unit configured with a ROM or the like, which has a double data access width and stores up to m memory addresses when writing and reading data to and from n-byte memory addresses requested to be accessed by the access unit; Temporary storage means temporarily stores data read from memory addresses stored in the storage means, and up to m memory addresses to which access is requested every n bytes from the access means are stored in the storage means. A control means for reading data from a memory address via a temporary storage means, and the invention according to claim 5 provides a control means for reading data from a memory address via a temporary storage means. and a memory access control device for controlling reading, an access means for accessing a memory address with an access width of n bytes and instructing reading and writing of data to the address, and a data access width of m times the access width. a storage means constituted by a RAM or the like that stores up to m memory addresses when writing and reading data to and from n byte memory addresses requested to be accessed by the access means; and a memory stored in the storage means. Temporary storage means for temporarily storing data to be written to an address and data read from a memory address; and up to m memory addresses to which access is requested every n bytes from the access means are stored in the storage means; It is characterized by comprising a control means for writing and reading data to and from a memory address via a temporary storage means, and an error detection means for detecting an error in data read from the m memory addresses. The invention according to claim 6 provides a memory access control device that controls writing and reading of data by accessing addresses in a memory via a system bus. an access means for instructing reading and writing of data to an address, and a data access width that is m times the access width;
When writing and reading data to n-byte memory addresses that are requested to be accessed by the access means, a storage means constituted by a RAM etc. that stores up to m memory addresses, and data to be written to the memory addresses stored in the storage means. and a temporary storage means for temporarily storing data read from the memory address; and a storage means for storing up to m memory addresses to which access is requested every n bytes from the access means, and data for the m memory addresses. control means for executing writing and reading of data through the temporary storage means; error detection means for detecting errors in data read from the m memory addresses; and error detection means for detecting errors detected by the detection means on the system bus The present invention is characterized by comprising an error output means for outputting an output.

[0005]

[Operation] The invention as claimed in claim 1 provides a memory access control device which includes: access means for accessing a memory address with an access width of n bytes; When writing and reading the memory address m
a temporary storage means for temporarily storing data written to the memory address stored in the storage means and data read from the memory address; and a memory address requested to be accessed every n bytes from the access means. A control means is provided for storing up to m pieces of data in the storage means, and writing and reading data to and from the m memory addresses via the temporary storage means, and a memory address that is requested to be accessed every n bytes from the access means. Up to m memory addresses are stored in the storage means, and writing and reading of data to and from the m memory addresses is executed via the temporary storage means.

[0006] Therefore, without using high-speed devices or cache memory, it is possible to shorten the time it takes to complete memory access when reading and writing data, and to speed up data access in devices to which a memory access control device is applied. be able to. The invention as claimed in claim 2 provides a memory access control device comprising: access means for accessing a memory address with an access width of n bytes; writing data to the memory address of n bytes requested for access from the access means; A storage means that stores up to m memory addresses at any time during reading, a temporary storage means that temporarily stores data read from the memory addresses stored in the storage means, and a memory that is requested to be accessed every n bytes from the access means. A control means is provided for storing up to m addresses in the storage means and reading data for the m memory addresses through the temporary storage means, and the memory address requested to be accessed every n bytes from the access means is provided. Up to m memory addresses are stored in the storage means, and data reading for the m memory addresses is executed via the temporary storage means.

[0007] Therefore, without using a high-speed device or cache memory, it is possible to shorten the time required to complete memory access when reading data, and to speed up data access in equipment to which the memory access control device is applied. . The invention according to claim 3 provides a memory access control device, which includes: access means for accessing a memory address with an access width of n bytes; writing data to the memory address of n bytes requested for access from the access means; A storage means that stores up to m memory addresses at any time during reading, a temporary storage means that temporarily stores data to be written to the memory addresses stored in the storage means, and a memory address that is requested to be accessed every n bytes from the access means. A control means is provided for storing up to m pieces of data in the storage means, and writing data to the m memory addresses via the temporary storage means, and storing memory addresses requested to be accessed every n bytes from the access means. Up to m memory addresses are stored in the means, and writing of data to the m memory addresses is executed via the temporary storage means.

[0008] Therefore, without using a high-speed device or cache memory, it is possible to shorten the time required to complete memory access when writing data, and to speed up data access in devices to which the memory access control device is applied. . The invention according to claim 4 provides a memory access control device, which includes: access means for accessing a memory address with an access width of n bytes; writing data to the memory address of n bytes requested for access from the access means; a storage means for storing up to m memory addresses at the time of reading; a temporary storage means for temporarily storing data to be written to the memory address stored in the storage means and data read from the memory address; A control means is provided for storing up to m memory addresses to which access is requested in the storage means and reading data from the m memory addresses through the temporary storage means, and the access means requests access every n bytes. Up to m memory addresses are stored in the storage means, and data reading for the m memory addresses is executed via the temporary storage means.

[0009] Therefore, without using a high-speed device or cache memory, it is possible to shorten the time required to complete memory access when reading data, and to speed up data access in devices to which the memory access control device is applied. . The invention as set forth in claim 5 provides a memory access control device that includes access means for accessing a memory address with an access width of n bytes, writing data to the memory address for n bytes requested for access from the access means, and a storage means for storing up to m memory addresses at any time during reading; a temporary storage means for temporarily storing data to be written to the memory address stored in the storage means and data read from the memory address; a control means for storing up to m memory addresses requested to be accessed in a storage means, and executing writing and reading of data to and from the m memory addresses via a temporary storage means; An error detection means for detecting an error in the data read from the memory is provided, and up to m memory addresses requested to be accessed every n bytes from the access means are stored in the storage means, and the data for the m memory addresses are stored in the storage means. Writing and reading are executed via the temporary storage means, and error detection processing for the read data is executed.

[0010] Therefore, without using high-speed devices or cache memory, the time taken to complete memory access when reading and writing data can be shortened, and errors can be detected before transferring read data and memory Data access of devices to which the access control device is applied can be sped up, and reliability can be improved.

The invention as set forth in claim 6 provides a memory access control device which includes: access means for accessing a memory address with an access width of n bytes; and data access to the memory address of n bytes requested by the access means. a storage means for storing up to m memory addresses at any time during writing and reading; a temporary storage means for temporarily storing data written to the memory addresses stored in the storage means and data read from the memory addresses; and an access means. Up to m memory addresses to which access is requested every n bytes are stored in the storage means, and the m
a control means for writing and reading data to and from memory addresses for each memory address through a temporary storage means;
A detection means for detecting an error in the data read from each memory address, and an error output means for outputting the error detected by the detection means to the system bus, and an access request is received every n bytes from the access means. A system for storing up to m memory addresses in a storage means, writing and reading data to and from the m memory addresses through a temporary storage means, and performing error detection processing on read data and detecting detected data errors. Executes output processing to the bus.

Therefore, without using high-speed devices or cache memory, it is possible to shorten the time required to complete memory access when reading and writing data, and to detect errors before transferring read data to improve system performance. It is possible to output data to the bus, speed up data access in devices to which the memory access control device is applied, and improve reliability.

[0013]

[Example] Next, a detailed description will be given based on an example. 1 to 6 are diagrams showing an embodiment of a memory access control device according to each invention described in claims 1 to 4. FIG. 1 is a block diagram showing the configuration of a memory access control device 1.
The memory access control device 1 is composed of an access instruction section 2 and a memory access section 3, and each section is connected to a system bus 4. Note that the system bus 4 has 16
It shall have a data width of bits.

[0014] The access instruction unit (access means) 2 is a C
PU (Central Processing Unit)
) 5 and a control section 6. The CPU 5 outputs command data to the memory access unit 3 via the control unit 6 to instruct writing and reading of data to and from a large capacity memory connected outside the figure to memory addresses of the large capacity memory with a predetermined access width. , receives response data and the like in response to instructions output from the memory access unit 3 via the control unit 6. Note that the data access width (n) of the CPU 5 is, for example, 8 bits or 16 bits.

The control unit 6 converts the command data input from the CPU 5 into a data format that can be output to the system bus 4 and outputs it to the system bus 4, so that the data input from the system bus 4 can be processed by the CPU 5. Convert to form C
Output to PU5. The memory access unit 3 has memories 8 to 8.
11, buffers 12 to 15, a bus I/F 16, a control section 17, and the like.

Memories (storage means) 8 to 11 are DRAMs.
(DynamicRAM), etc., and each
Memory address data is stored with the access width of the CPU 5, and the memories 8 to 11 as a whole are configured to have an access width that is an integral multiple (m times) of the access width of the CPU 5. Each of the memories 8 to 11 transfers the corresponding memory address data to the buffer 12 according to instructions from the control unit 17 in response to a memory address access request output from the CPU 5.
Transfer to ~15.

Buffers (temporary storage means) 12 to 15 are
Data is accessed with a data width that is an integral multiple of the system bus 4, and in this embodiment, 32 bits (A1 to A
32), that is, it has a data access capability of 4 bytes. The buffers 12 to 15 temporarily store data when writing and reading data to and from memory addresses transferred from the memories 8 to 11 according to instructions from the control unit 17.

When data is exchanged between the buffers 12-15 and the system bus 4, the bus I/F 16 converts the data into a data format that can be received by both the buffers 12-15 and the system bus 4. The control section 17 includes an address comparator decoder 21, a flip-flop 22, a RAM control 23, a selector 24, and a buffer selector 25, as shown in FIG.

The address comparator decoder 21 determines whether the memory address accessed by the CPU 5 is the address of the data stored in the buffers 12 to 15 (A1
~A32) and whether the memory of this embodiment has been accessed.
y Reset) and outputs the signal to the flip-flop 22. The flip-flop 22 receives a signal (Buffer Busy) indicating whether data is stored in the buffers 12 to 15 based on the determination data output from the address comparator decoder 21.
is output to the RAM control 23.

The RAM control 23 controls the memories 8 to 1.
Each signal (RAS, CAS,
WE, OE, MPX, etc.) and controls the storage operation of address data in the memories 8 to 11. selector 24
select signals for the memories 8 to 11 and the CPU 5 based on various signals (DS1, DS0, WRITE, etc.) input from the access instruction unit 2 via the system bus 4.
The buffer selector 25 determines the access width, etc., and outputs a signal to activate the buffer selector 25.

[0021] The buffer selector 25 is the selector 2
Select signals (B0 to B3) for selecting buffers 12 to 15 based on signals output from system bus 4
Output to. Next, the effect will be explained. First, memory access processing when there is a data read request to the memory will be described based on the flowchart of FIG. 3.

[0022] From the CPU 5 of the access instruction section 2 to the control section 6
When an access (read) request is input to the control unit 17 of the memory access unit 3 via the system bus 4 (step S1), the address comparator decoder 21 in the control unit 17 detects that the data has already been stored in the buffers 12 to 15. Check whether it is stored (step S2)
. Here, the address comparator decoder 21 compares the address accessed this time with the address accessed last time to determine the presence or absence of data in the buffers 12-15.

When data is stored in the buffers 12-15, it is determined whether the data width of the accessed address exceeds the accessible data width of the buffers 12-15 (step S3). Here, when the data width is not exceeded, a trigger signal is output from the address comparator decoder 21 to the flip-flop 22 (DATACLK is set to high), and the Buffer Busy signal output from the flip-flop 22 is output.
The signal is output to the RAM control 23 in an enabled state. Moreover, when the data width is exceeded, a clear signal (BusyReset) is output from the address comparator decoder 21 to the flip-flop 22, and the buffer B output from the flip-flop 22 is
The usy signal is output to the RAM control 23 in a disenable state. In RAM control 23,
It is determined whether data is stored in the buffers 12 to 15 depending on the state of the Buffer Bu-sy signal.

Therefore, in step S2, the buffer 12
When no data is stored in ~15, Buffe
r Set the Busy signal to disenable state and set the RA
Activate M control 23 and RAM control 23
The above-mentioned signals for controlling the storage operations of the memories 8 to 11 are outputted from the memory 8 to 11 to read the address data stored in the memories 8 to 11 (step S4), and the read address data is stored in the buffers 12 to 15 (step S4). S5
).

Here, from memories 8 to 11 to buffer 12
Accesses to buffers 12 to 15 are performed simultaneously using the accessible data width of each buffer 12 to 15. In this embodiment, 4 bytes are accessed at once by buffers 12-15. Next, the address comparator decoder 21 outputs a trigger signal to the flip-flop 22 to enable the BufferBusy signal (ON).
) (step S6), the buffer selector 25 is activated by the selector 24, and the buffer selector 2
5 outputs a select signal, enables the buffers 12 to 15 according to the access width from the CPU 5, outputs data from the buffers 12 to 15 to the system bus 4, and ends the process (step S7).

On the other hand, in step S2, the buffers 12 to 15
If data is stored in the buffers 12 to 15, it is checked whether the address accessed by the CPU 5 is within the address range of data already stored in the buffers 12 to 15 (step S3). Specifically, memory 8~
Since the access from No. 11 is performed for 4 bytes at once, it is determined whether the previous access request and the current access request are within 4 bytes.

If it is not within the range, a Busy Reset signal is output from the address comparator decoder 21 to the flip-flop 22, and the Buffer Busy
The signal is set to a disenable state (step S8),
The RAM control 23 is activated, the RAM control 23 outputs each of the above-mentioned signals that control the access operation to the memories 8 to 11, and the address data stored in the memories 8 to 11 is read out and stored in the buffers 12 to 15. (Steps S4, S5).

Next, the address comparator decoder 21 outputs a trigger signal to the flip-flop 22 to enable the Buffer Busy signal (O
N) (step S6), the buffer selector 25 is activated by the selector 24, a select signal is output from the buffer selector 25, and the buffers 12 to 15 corresponding to the access width from the CPU 5 are enabled, and the buffer 12 is activated. 15 to the system bus 4, and the process ends (step S7).

Further, when the access-requested address is within the range of addresses of data already stored in the buffers 12 to 15, the buffer selector 25 is activated by the selector 24, and the buffer selector 25 is activated.
A select signal is output from the CPU 5, the buffers 12 to 15 corresponding to the access width from the CPU 5 are enabled, data is output from the buffers 12 to 15 to the system bus 4, and the process ends (step S7).

FIG. 4 is a diagram showing a timing chart of each signal in the memory access process when reading data. In this figure, as shown in section A, when no data is stored in the buffers 12 to 15, , or when the address accessed by the CPU 5 is outside the range of data stored in the buffers 12 to 15, the RA
Since data is output to the system bus 4 after activating the M control 23 and accessing the memories 8 to 11 and outputting address data to the buffers 12 to 15, the access time tends to be longer.

On the other hand, as shown in section B, the buffer 12
15 is accessed by the CPU 5 and data is stored therein, the data is output to the system bus 4 just by selecting the buffers 12 to 15, so the access time is shortened and the memory can be accessed at high speed. It becomes possible to do so. Next, memory access processing when writing data will be explained based on the flowchart of FIG. 5.

From the CPU 5 of the access instruction section 2 to the control section 6
When an access (write) request is input to the control unit 17 of the memory access unit 3 via the system bus 4 (step T1), the RAM control 23 in the control unit 17
checks whether data is already stored in the buffers 12 to 15 (step T2). Buffer 12
When data is stored in ~15, buffer 12
Wait for data of ~15 to become invalid (step T3)
.

That is, the RAM control 23 is activated in response to an access from the CPU 5, and waits until the access from the memories 8 to 11 to the buffers 12 to 15 is completed. When no data is stored in the buffer, the data on the system bus 4 is stored in the buffer (step T4), and the address comparator decoder 21 is used to indicate that the write data stored in the buffers 12 to 15 is valid. outputs a trigger signal to the flip-flop 22 and outputs a Buffer Busy signal.
enable state (ON) (step T5). Next, to indicate that the access from the selector 24 to the CPU 5 has ended, an access end signal (DTACK) is output to the system bus 4 (step T6).

When the CPU 5 receives this DTACK signal, it is recognized that the write access has been completed. Then, the RAM control 23 controls the buffers 12 to
In response to the write data being stored in memory 8.
- 11 are output, and the write data stored in buffers 12 - 15 are written into memories 8 - 11 (step T7). Next, when the writing is completed, the address comparator decoder 21 sends the flip-flop 2 to indicate that the write data stored in the buffers 12 to 15 is invalid.
Output the Busy Reset signal to Buffer
The Busy signal is set to a disenable (OFF) state and the process ends (step T8).

FIG. 6 is a diagram showing a timing chart of each signal in the memory access process at the time of data writing. In this figure, data stored in the buffers 12 to 15 is When is invalid, the write access is completed by simply writing the write data on the system bus 4 to the buffers 12 to 15, so high-speed access is possible.

On the other hand, when the data stored in the buffers 12 to 15 is valid, the data stored in the buffers 12 to 15 is transferred from the memories 8 to 11 to the buffer 12.
The access to buffers 12 to 15 is completed, and buffers 12 to 15 are
Although the write access timing will be delayed by the time it takes for the data in the memory to become invalid, many conventional CPUs (
In particular, since there is an overhead when accessing continuously (particularly those that operate on an asynchronous bus system), this waiting time is offset. Therefore, the write access time becomes longer less frequently, and the overall memory access time can be shortened.

Note that the memory access control when reading and writing data to the memory may be such that only the memory access control function during reading is applied, or only the memory access control function during writing may be applied, depending on the system to which the memory access control device 1 is applied. It is also possible to apply only the memory access control function at the time. In addition, when applying only the memory access control function at the time of reading, the memories 8 to 11 provided in the memory access unit 3 are not RAM but R
It may be replaced with OM.

Therefore, by applying the memory access control device 1 to various information processing devices, etc., it is possible to achieve high-speed memory access processing without using a high-speed device or cache memory system, and to increase the speed of memory access functions. It is possible to avoid increasing the cost and complexity of each device. FIG. 7 is a diagram showing an embodiment of the memory access control device according to each invention as claimed in claims 5 and 6. In FIG. 7, the same components as the memory access control device 1 shown in FIG. , the same numbers are given and the explanation is omitted.

The present embodiment is characterized in that, as shown in FIG. 7, a parity control section 33 and a parity memory 34 are provided within the memory access section 32 of the memory access control device 31. Parity control unit (error detection means) 33
has a function of generating parity bits and performing a parity check on 4-byte data all at once when accessing the memories 8 to 11, and the parity memory (error output means) 34 is checked by the parity control unit 33. The parity bit thus obtained is stored and output to the control section 17.

Therefore, conventional parity bit generation and parity checking are performed using the CPU access width (8 bits, 16 bits, etc.), but in this embodiment, parity bit generation and parity checking are performed every 4 bytes, which is greater than the CPU access width. The parity check can be performed quickly, and the parity bit check can be completed more quickly. For example, in a system where the CPU accesses in 8-bit width, if 1 byte of consecutive 4-byte data causes a parity error, the parity check for every 8 bits will not execute the access up to 4 times. However, if the memory access control device 31 of this embodiment is applied, a parity error can be detected in one access.

As a result, it is possible to speed up memory access processing in a device to which the memory access control device 31 is applied, and improve reliability.

[0042]

According to the invention as claimed in claim 1, in the memory access control device, up to m memory addresses to which access is requested every n bytes are stored in a RAM or the like, and data for the m memory addresses are stored. Writing and reading of data are temporarily stored in a buffer etc., so the time taken to complete memory access when reading and writing data is shortened without using high-speed devices or cache memory. It is possible to speed up data access in devices to which the memory access control device is applied.

According to the second aspect of the invention, in the memory access control device, up to m memory addresses to which access is requested every n bytes are stored in a RAM or the like, and
Data reading for individual memory addresses is temporarily stored in a buffer, etc., so the time required to complete memory access when reading data is reduced without using high-speed devices or cache memory. However, it is possible to speed up data access in devices to which the memory access control device is applied.

According to the third aspect of the present invention, in the memory access control device, up to m memory addresses to which access is requested every n bytes are stored in a RAM or the like, and writing of data to the m memory addresses is performed in a buffer. Because the data is temporarily stored and executed in the memory, the time taken to complete memory access when writing data is shortened without using high-speed devices or cache memory.
It is possible to speed up data access in devices to which the memory access control device is applied.

According to the fourth aspect of the invention, in the memory access control device, up to m memory addresses to which access is requested every n bytes are stored in a ROM or the like, and reading data to the m memory addresses is performed in a buffer. Because the data is temporarily stored and executed in the memory, the time taken to complete memory access when reading data is shortened without using high-speed devices or cache memory.
It is possible to speed up data access in devices to which the memory access control device is applied.

The invention as set forth in claim 5 provides a memory access control device that stores up to m memory addresses to which access is requested every n bytes in a RAM or the like, and writes and reads data to and from the m memory addresses. It is executed by temporarily storing it in a buffer etc., and also performs error detection processing on the read data.
without using high-speed devices or cache memory.
In addition to shortening the time it takes to complete memory access when reading and writing data, it also detects errors before transferring read data, speeding up data access in devices that use memory access control devices. It is possible to improve reliability.

According to the sixth aspect of the invention, in the memory access control device, up to m memory addresses to which access is requested every n bytes are stored in a RAM or the like, and data is written to and read from the m memory addresses. This function temporarily stores the data in a buffer, etc., and executes it, as well as detecting errors in read data and outputting detected data errors to the system bus, without using high-speed devices or cache memory. In addition to reducing the time it takes to complete memory access when reading and writing data, it also detects errors and outputs them to the system bus before transferring the read data, and improves the data of devices using memory access control devices. Access can be made faster and reliability can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a memory access control device according to the invention according to claims 1 to 4.

FIG. 2 is a block diagram showing the configuration of a control section in the memory access section of FIG. 1;

FIG. 3 is a flowchart showing a program for memory access processing when reading data according to the invention according to claims 1 to 4;

FIG. 4 is a timing chart of each signal in a memory access control device controlled by memory access control during data reading according to the invention according to claims 1 to 4;

FIG. 5 is a flowchart showing a program for memory access processing when writing data according to the invention according to claims 1 to 4;

FIG. 6 is a timing chart of each signal in a memory access control device controlled by memory access control during data writing according to the invention according to claims 1 to 4;

FIG. 7 is a block diagram showing the configuration of a memory access control device according to the invention according to claims 5 and 6.

[Explanation of symbols]

1, 31 Memory access control device 2 Access instruction section 3, 32 Memory access section 4 System bus 5 CPU 6 Control section 8-11 Memory 12-15 Buffer 16 Bus I/F 17 Control section 21 Address comparator decoder 22
Flip-flop 23 RAM control 24 Selector 25 Buffer selector 33 Parity control section 34 Parity memory

Claims (6)

[Claims] 1. A memory access control device that controls data writing and reading by accessing a memory address via a system bus, wherein the memory access control device accesses a memory address with an access width of n bytes and writes data to the address. has an access means for instructing reading and writing of data, and a data access width m times the access width, and the memory address is used when writing and reading data to and from the n-byte memory address requested to be accessed by the access means. A storage means constituted by a RAM etc. that stores up to m data, a temporary storage means that temporarily stores data to be written to the memory address stored in the storage means and data read from the memory address, and an access means for every n bytes. The present invention is characterized by comprising a control means for storing up to m memory addresses to which access is requested in a storage means, and for executing writing and reading of data to and from the m memory addresses via a temporary storage means. Memory access control device. 2. A memory access control device that controls data writing and reading by accessing a memory address via a system bus, wherein the memory access control device accesses a memory address with an access width of n bytes and writes data to the address. an access means for instructing reading and writing, and a data access width m times the access width;
When writing and reading data to and from an n-byte memory address that is requested to be accessed by the access means, a storage means constituted by a RAM, etc., stores up to m memory addresses, and data is read from the memory address stored in the storage means. A temporary storage means for temporarily storing data; and a temporary storage means for storing up to m memory addresses to which access is requested every n bytes from the access means, and for reading data from the m memory addresses. A memory access control device characterized by comprising: a control means that executes the operation via the memory access control device. 3. A memory access control device that controls data writing and reading by accessing a memory address via a system bus, wherein the memory access control device accesses a memory address with an access width of n bytes and writes data to the address. an access means for instructing reading and writing, and a data access width m times the access width;
A storage means constituted by a RAM or the like that stores up to m memory addresses when writing and reading data to and from an n-byte memory address requested to be accessed by the access means, and data to be written to the memory address stored in the storage means. temporary storage means for temporarily storing the
Control means for storing up to m memory addresses that are requested to be accessed every n bytes from the access means in the storage means, and writing data to the m memory addresses via the temporary storage means. A memory access control device characterized by: 4. A memory access control device that controls data writing and reading by accessing a memory address via a system bus, wherein the memory access control device accesses the memory address with an access width of n bytes and writes data to the address. an access means for instructing reading and writing, and a data access width m times the access width;
A storage means constituted by a ROM etc. that stores up to m memory addresses when writing and reading data to n-byte memory addresses requested to be accessed by the access means, and reading from the memory addresses stored in the storage means. a temporary storage means for temporarily storing the data, and a storage means for storing up to m memory addresses that are requested to be accessed every n bytes from the access means, and temporarily storing data read to the m memory addresses. 1. A memory access control device, comprising: a control means that executes the control via the means. 5. A memory access control device that controls data writing and reading by accessing a memory address via a system bus, wherein the memory access control device accesses a memory address with an access width of n bytes and writes data to the address. an access means for instructing reading and writing, and a data access width m times the access width;
A storage means constituted by a RAM or the like that stores up to m memory addresses when writing and reading data to and from an n-byte memory address requested to be accessed by the access means, and data to be written to the memory address stored in the storage means. and a temporary storage means for temporarily storing data read from the memory address, and a storage means for storing up to m memory addresses that are requested to be accessed every n bytes from the access means, and data for the m memory addresses. A memory access device comprising: a control means for executing writing and reading of data through a temporary storage means; and an error detection means for detecting an error in data read from the m memory addresses. Control device. 6. A memory access control device that controls data writing and reading by accessing a memory address via a system bus, wherein the memory access control device accesses a memory address with an access width of n bytes and writes data to the address. an access means for instructing reading and writing, and a data access width m times the access width;
A storage means constituted by a RAM or the like that stores up to m memory addresses when writing and reading data to and from an n-byte memory address requested to be accessed by the access means, and data to be written to the memory address stored in the storage means. and a temporary storage means for temporarily storing data read from the memory address, and a storage means for storing up to m memory addresses that are requested to be accessed every n bytes from the access means, and data for the m memory addresses. control means for executing writing and reading of data through the temporary storage means; error detection means for detecting errors in data read from the m memory addresses; 1. A memory access control device comprising: error output means for outputting an output to the memory access controller.