JPH04260903A - Specific function unit for programmable controller - Google Patents

Abstract

PURPOSE:To make it unnecessary to form a sequence program for data communication between specific function units in a programmable controller, to make it possible to execute data communication at optional time and to determine a sampling period on the specific function unit side. CONSTITUTION:Since the specific function unit in the programmable controller 10 is provided with data communication interface circuits 3f, 4f for directly execute data communication with other specific function units, the formation of a sequence program for data communication between different specific function units is made unnecessary. Since the data communication can be executed at optional time, the instataneousness of data can be obtained and the sampling period can be determined on the specific function unit side.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a special function unit of a programmable controller.

0002

2. Description of the Related Art FIG. 4 is a block diagram of an example of a conventional programmable controller. (10) is a programmable controller.

(1) is a CPU unit, (1a) is a microprocessor, (1b) is a data memory, (1c) is a system bus interface circuit, (1d) is an internal bus, and (1e) is a sequence program memory.

(3) is an A/D conversion unit that converts input analog voltage and analog current into digital values;
3a) is a microprocessor, (3b) is a dual port memory that exchanges data with the CPU unit (1), (3c) is a system bus interface circuit, (3d) is an internal bus, and (3e) is an A /D conversion circuit.

(4) is a data collection unit, (4a) is a microprocessor, and (4b) is the CPU unit (
1) Dual port memory that transfers data between the two, (4c) is the system bus interface circuit,
(4d) is an internal bus, and (4e) is a data memory.

(2) The CPU unit (1), A
This is a base unit to which units such as a /D conversion unit (3) and a data collection unit (4) are attached. (2a
) is the system bus.

FIG. 5 shows a part of the sequence program stored in the sequence program memory (1e) of the CPU unit (1). The sequence program is
The steps from 0 step to END step are sequentially and repeatedly scanned and calculated.

(6) The CPU unit (1) is an A/D
This is an instruction to read data from the dual port memory (3b) of the conversion unit (3). The declaration "FROM" represents a data read request. The next "H0" is C
Indicates the unit number from which to read counting from the PU unit (1). In this case, A/D
This becomes a conversion unit (3). The next "K10" is A/D
This represents address designation as to where in the dual port memory (3b) of the conversion unit (3) to read from. The next "D0" represents address designation as to where in the data memory (1b) of the CPU unit (1) the data read from the dual port memory (3b) of the A/D conversion unit (3) is to be stored. The next "K10" represents a data count designation indicating how many data are to be read.

(7) is an instruction to write data from the data memory (1b) of the CPU unit (1) to the dual port memory (4b) of the data collection unit (4). The declaration "TO" represents a data write request. The next "H1" represents a unit designation indicating which unit, counting from the CPU unit (1), data is to be written. The next "K0" represents address designation as to where in the dual port memory (4b) of the data acquisition unit (4) data is to be written. The next "D0" is the dual port memory (4b) of the data acquisition unit (4)
represents an address designation from which data memory (1b) of the CPU unit (1) is to read data to be written to the CPU unit (1). The next "K10" represents the data count specification of how many data to write.

Next, an explanation will be given of the operation when the digital value of the analog voltage or analog current input to the A/D conversion unit (3) is collected into the data collection unit (4).

First, an analog voltage or an analog current input from the outside is converted into an A/D converter unit (3).
A D conversion circuit (3e) converts it into a digital value. The microprocessor (3a) transfers the digital value to the internal bus (
3d) and transferred to a predetermined address in the dual port memory (3b). A/D conversion unit (3)
repeats the above operations to store and update the ever-changing digital value of the analog voltage or analog current in the dual port memory (3b).

The CPU unit (1) sequentially and repeatedly scans the sequence program stored in the sequence program memory (1e) from the 0 step to the END step and performs calculations.

When the sequence program instruction (6) is executed, data 10 at addresses 10 to 19 of the data in the dual port memory (3b) of the A/D conversion unit (3)
These are the system bus interface circuit (3c), system bus (2a), and CP of the A/D conversion unit (3).
The data memory (1b) of the CPU unit (1) is connected to the data memory (1b) of the CPU unit (1) through the system bus interface circuit (1c) of the U unit (1) and the internal bus (1d) of the CPU unit (1).
It is transferred to addresses 0 to 9 of .

Next, the sequence program command (7)
When executed, 10 pieces of data at addresses 0 to 9 of the data memory (1b) of the CPU unit (1) are transferred to the internal bus (1d) of the CPU unit (1) and the system bus interface circuit of the CPU unit (1). (1c), the system bus (2a), and the dual port memory (4b) of the data acquisition unit (4) through the system bus interface circuit (4c) of the data acquisition unit (4).
Transferred to address 9.

[0015] The microprocessor (4a) of the data acquisition unit (4) has the dual port memory (4b)
Read the data at address ~9 through the internal bus (4d),
The data is transferred to a predetermined address in the data memory (4e). Thus, the digital value of the analog voltage or analog current input to the A/D conversion unit (3) is collected by the data collection unit (4).

[0016]

[Problems to be Solved by the Invention] Special function units of conventional programmable controllers cannot directly transmit and receive data with other special function units, and as shown in the example of FIG. The CPU unit (1) reads data from the special function unit on the sending side via the system bus and system bus interface circuit,
Next, the CPU unit (1) writes data to the special function unit on the receiving side via the system bus and the system bus interface circuit.

[0017] Therefore, it is necessary to create a sequence program for data communication between special function units, which poses a problem of complexity. In addition, the CPU unit (
In 1), the time for data communication is determined by the scan time of the sequence program, so there is a problem that data communication cannot be performed at an arbitrary time. Another problem was that the sampling period could not be determined on the special function unit side.

The present invention was made to solve the above-mentioned problems, and it is not necessary to create a sequence program for data communication between special function units, and data communication can be performed at any time. It is an object of the present invention to provide a special function unit of a programmable controller which is capable of performing the following and further allows the sampling period to be determined on the special function unit side.

[0019]

[Means for Solving the Problems] A special function unit of a programmable controller of the present invention is characterized in that it is equipped with a data communication interface circuit for directly communicating data with other special function units. It is something.

[0020]

[Function] By providing a data communication interface circuit for direct data communication between special function units of the programmable controller, data communication can be performed using
There is no need to intervene with the PU unit (1). Therefore, there is no need to create a sequence program for data communication between special function units. Also, C
Data communication can be performed at any time regardless of the scan time of the sequence program in the PU unit (1). Additionally, the sampling period can be determined on the special function unit side.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, (10) is a programmable controller.

(1) is a CPU unit, (1a) is a microprocessor, (1b) is a data memory, (1c) is a system bus interface circuit, (1d) is an internal bus, and (1e) is a sequence program memory.

(3) is an A/D conversion unit that converts input analog voltage and analog current into digital values;
3a) is a microprocessor, (3b) is a dual port memory that exchanges data with the CPU unit (1), (3c) is a system bus interface circuit, (3d) is an internal bus, and (3e) is an A /D conversion circuit, (3f) is a data communication interface circuit, (
3g) is a buffer circuit, and (3h) is a data latch circuit.

(4) is a data collection unit, (4a) is a microprocessor, and (4b) is the CPU unit (
1) Dual port memory that transfers data between the two, (4c) is the system bus interface circuit,
(4d) is the internal bus, (4e) is the data memory, (4f
) is a data communication interface circuit.

(2) The CPU unit (1), A
This is a base unit to which units such as a /D conversion unit (3) and a data collection unit (4) are attached. (2a
) is the system bus.

(5) The A/D conversion unit (3)
This cable connects the data communication interface circuit (3f) of the data acquisition unit (4) to the data communication interface circuit (4f) of the data collection unit (4).

Next, the data collection unit (4)
The operation of collecting A/D conversion data from the conversion unit (3) will be explained.

First, an analog voltage or an analog current input from the outside is input to the A/D conversion unit (3).
The D conversion circuit (3e) performs A/D conversion, and the buffer circuit (3e) performs A/D conversion.
g). The A/D conversion data stored in the buffer circuit (3g) is processed by the microprocessor (3a).
It is read through the internal bus (3d) and transferred to a predetermined address in the dual port memory (3b). The A/D conversion unit (3) repeats the above operations to store and update the A/D conversion data of the analog voltage or analog current that changes every moment in the dual port memory (3b).

The microprocessor (4a) of the data acquisition unit (4) includes a data communication interface circuit (4f), a cable (5), and an A/D conversion unit (3).
via the data communication interface circuit (3f) of
Data latch circuit (3h) of A/D conversion unit (3)
, outputs a latch command for A/D conversion data. The data latch circuit (3h) that receives the latch command holds the A/D converted data output from the A/D conversion circuit (3e).

The microprocessor (4a) of the data acquisition unit (4) converts the A/D conversion data held in the data latch circuit (3h) of the A/D conversion unit (3) into
The data is read through the data communication interface circuit (3f) of the A/conversion unit (3), the cable (5), and the data communication interface circuit (4f) of the data acquisition unit (4), and the specified data is stored in the data memory (4e). Store it at the address of . FIG. 2 shows the above operation in a flowchart.

FIG. 3 is an explanatory diagram showing the relationship between the OS program and the A/D conversion data collection operation in the data collection unit (4). The microprocessor (4a) of the data collection unit (4) operates on an OS program stored in an OSROM (not shown). When A/D conversion data collection is activated at a certain time, the above-described A/D conversion data collection operation is executed for a preset number of samples at a preset sampling period.

[0032]

According to the special function unit of the programmable controller of the present invention, data communication can be directly performed between the special function units, and the CPU unit (
1), there is no need to create a sequence program for data communication between special function units.

Furthermore, it becomes possible to exchange data between the special function units at any time regardless of the scan time of the sequence program in the CPU unit (1), and it becomes possible to obtain data immediacy. .

Furthermore, the sampling period can be arbitrarily determined on the special function unit side.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a programmable controller system including an embodiment of a special function unit of a programmable controller according to the present invention.

FIG. 2 is a flow diagram showing the operation of data collection according to the present invention.

FIG. 3 is an explanatory diagram showing the relationship between a data collection operation and an OS program according to the present invention.

FIG. 4 is a configuration diagram of a programmable controller system including special function units of a conventional programmable controller.

FIG. 5 is an explanatory diagram of main parts of a conventional sequence program for data communication.

[Explanation of symbols]

1 CPU unit 2 Base unit 2a System bus 3 A/D conversion unit 3c System bus interface circuit 3f Data communication interface circuit 4 Data acquisition unit 4c System bus interface circuit 4f Data communication interface circuit 5 Cable 10 Programmable controller

Claims (1)

[Claims] 1. A programmable controller equipped with a data communication interface circuit for directly communicating data with other special function units in a special function unit installed on a system of a programmable controller. Special function unit of controller.