JPH04258153A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the coverage of a wiring layer stacked later by flattening the topside of the high melting point metal, which is stacked in the contact hole having high aspect ratio, and the topside of a smooth coat layer. CONSTITUTION:A barrier metal 5 (TiN) is stacked in a contact hole, and tungsten '6' is stacked to fill up the above contact hole above the barrier metal 5, and that tungsten '6' is etched back to the interface between the above barrier metal 5 and that tungsten '6', and an AR wiring layer 9 is made over the above tungsten '6'. Furthermore, thereon a resist pattern 10 is made, and with this as mask, the Al wiring layer 9 is etched off to the interface between the Al wiring layer 9 and the above barrier metal 5, and the tungsten residual on the barrier metal 5 around the contact hole is etched off, and the barrier metal 5 around the contact hole is etched off.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a technique for burying contact holes (or interlayer connection holes, etc.) having a high aspect ratio.

0002

2. Description of the Related Art FIGS. 6 to 10 are cross-sectional flowcharts showing a conventional method of manufacturing a semiconductor device, particularly a method of filling a contact hole.

Among semiconductor memory devices, RAM and DRAM with a storage capacity of 16 Mbyte class,
The contact hole has an opening diameter of 0.6μmφ to 1.0
μmφ has a high aspect ratio of about 1.0 μm or more in depth (aspect ratio = depth/opening diameter, and this is usually called a high aspect ratio when it is 1 or more), and Al-Si or Al
- Even if Al wiring such as Si-Cu is directly sputtered, it will break at the bottom of the contact hole and it is obvious that there will be no coverage.As a countermeasure, metals (especially high melting point metals are often used, and tungsten is the most commonly used) ) is buried in the contact hole, etched back, etc., the surface is flattened, and then the above-mentioned Al-based metal is sputtered. This technology is generally called W-Plug (tungsten plug). Also, selection W-CV
In the case of D, tungsten (hereinafter referred to as W) is deposited only in the contact hole, and there is no need to etch back afterwards, but it is difficult to selectively deposit it, so it is still a step away from practical application. . On the other hand, a method of depositing thick W on the entire surface and etching back to planarize it is fully possible with the current technology.

FIG. 6 is a sectional view showing the state after the contact hole is formed. In the figure, 1 is a silicon (Si) substrate, 2
is a smooth coat film, usually made of BPSG and SiO2
(formed by CVD, spin-on glass method, etc.), and has a thickness of approximately 1.6 μm. 3 is an opening formed in this smooth coat film 2 by anisotropic dry etching. 4 is the diameter of the contact hole, and if this is about 0.8 μm, the aspect ratio of this contact hole is 2.

Next, as shown in FIG. 7, for example, titanium nitride (hereinafter referred to as Ti) is deposited on the upper surface of the substrate including the contact hole.
Write N. In addition, titanium/tungsten [TiW]
The barrier metal 5 is formed by sputtering a film of about 1000 angstroms (commonly used molybdenum silicide [MoSi2], etc.). As is well known, this barrier metal TiN5 is necessary in particular to prevent Si from being deposited on the Pch contact portion and to form a stable fine ohmic contact. Tungsten (W) 6 having a thickness of about 1.0 μm is further deposited on the barrier metal 5 by sputtering or CVD.

Next, this tungsten 6 is etched back to obtain a shape as shown in FIG. Etching conditions for etchback include, for example, using an anode-coupled plasma etcher and using gas such as SF6 (or NF3, CF4/O2, etc. can also be used) at 10%
0SCCM, gas pressure 0.2 Torr, RF output approximately 200
Under W conditions, the tungsten etch rate is 4000 angstroms/m, and the TiN etch rate is approximately 100 angstroms/m.
It is approximately 0 angstrom/m. In this case the etching is isotropic. Usually, TiN on the smooth coat film 2 is removed by this etch-back, so the tungsten 6' in the contact hole is etched by about 4000 angstroms depending on the etch rate ratio of tungsten and TiN. It is recessed by about 4000 angstroms from the upper end surface of No. 3.

Next, in FIG. 9, 7 is a sputtered film, for example, Al--Si or Al--S, which is sputtered on the state shown in FIG.
The Al wiring layer is made of i-Cu or Al-Cu and has a film thickness of 10,000 angstroms, and 7' in FIG. 10 is an Al wiring layer formed by further processing the Al wiring layer by photolithography and anisotropic etching. It is.

[0008]

[Problems to be Solved by the Invention] Since the conventional method of manufacturing a semiconductor device is as described above, the upper surface of the W-Plug in the contact hole 3 is lower than the surface of the smooth coat film 2 and a step is created. The Al wiring layer that will be deposited later becomes thinner at the step part, or in severe cases, the wire breaks.
The reduction in the wiring cross-sectional area of the resulting Al wiring and the resulting increase in current density have caused problems such as a decrease in reliability due to so-called electromigration, which significantly shortens the wiring life.

The present invention was made to solve the above-mentioned conventional problems, and provides a semiconductor device in which a smooth coat film and a contact hole, or an interlayer insulating film and an interlayer connection hole can be flattened. The purpose is to provide a manufacturing method for.

0010

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes depositing a barrier metal in a contact hole or an interlayer connection hole of a multilayer wiring and on the upper surface of a substrate, and depositing a barrier metal above the deposited barrier metal. Depositing high melting point metal to fill contact holes or interlayer connection holes of multilayer wiring,
The high melting point metal is etched back so that the barrier metal remains on the substrate around the contact hole or the interlayer connection hole of the multilayer wiring, and a wiring pattern is formed above the high melting point metal.

Further, when forming a wiring pattern above the high melting point metal, a resist pattern is formed on the wiring layer, and using the resist pattern as a mask, the wiring layer is coated with an anisotropic material containing chlorine-based gas. Etching is performed to remove the interface between the wiring layer and the barrier metal, and plasma etching containing a fluorine-based gas is used to remove the high melting point metal residue on the barrier metal around the contact hole or the interlayer connection hole of the multilayer wiring. The resist pattern and the barrier metal around the contact hole or the interlayer connection hole of the multilayer wiring are etched away by anisotropic etching containing chlorine-based gas.

0012

[Operation] The method for manufacturing a semiconductor device according to the present invention is to deposit a barrier metal in the contact hole or the interlayer connection hole of the multilayer wiring and on the upper surface of the substrate, and to apply the barrier metal to the contact hole or the interlayer of the multilayer wiring above the deposited barrier metal. A high melting point metal is deposited to fill the contact hole, the high melting point metal is etched back so as to leave the barrier metal on the substrate around the contact hole or the interlayer connection hole of the multilayer wiring, and a wiring pattern is formed above the high melting point metal. Since I tried to form
The upper surface of the high melting point metal deposited to fill the contact hole or the interlayer connection hole of the multilayer wiring becomes flush with the upper surface of the smooth coat film and is flattened, improving the coverage of the wiring layer deposited later.

Furthermore, when forming a wiring pattern above the high melting point metal, a resist pattern is formed on the wiring layer, and using the resist pattern as a mask, the wiring layer is anisotropically etched using a chlorine-based gas. The interface between the wiring layer and the barrier metal is etched away, and the high melting point metal residue on the barrier metal around the contact hole or the interlayer connection hole of the multilayer wiring is etched away using plasma etching containing fluorine-based gas. Since the resist pattern and the barrier metal around the contact hole or the interlayer connection hole of the multilayer wiring are etched away by anisotropic etching containing a system gas, the high melting point metal is etched back to remove the barrier metal. The high melting point metal residue remaining can be removed without denting the upper end surface of the wiring pattern formed above.

[0014]

[Embodiment] FIGS. 1 to 4 are flowcharts showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. In FIG. 1, 6" is tungsten, 8 is tungsten residue, and FIG.
In FIGS. 3 and 4, 9 is an Al wiring layer, 10 is a resist pattern, and in FIGS. 3 and 4, 10' is a resist pattern, 9'
is an Al wiring after patterning, etching, etc. are performed on this Al wiring layer 9. Further, FIG. 5 is a graph of the change in luminescence level over time used to demonstrate the end point detection method during etching of tungsten 6. In FIG.

Next, the manufacturing method will be explained. first,
The method of forming a smooth coat film 2 on a silicon substrate 1, forming a contact hole 3 by anisotropic dry etching, sputtering a barrier metal 5, and sputtering a tungsten 6 is the same as in the conventional example (Figs. 7
reference).

Next, the tungsten 6 in the state shown in FIG. 7 is etched back, but this time the etching is finished at the interface between the tungsten 6 and the barrier metal 5 in order to leave the barrier metal 5 formed by sputtering TiN. . In this case, a W residual of 8 inevitably remains. The end point of this etching is detected by emission spectroscopy. For example, if F* (703.8 nm wavelength light), which is a reactive species, is used, as shown in FIG.
Since this can be detected, if the etching is terminated at that point, the state shown in FIG. 1 can be achieved. If etching is performed up to FIG. 5B, the tungsten 6'' in the contact hole will be completely removed, so in the present invention, etching is not performed to this point.However, in this case, W residue 8 inevitably remains as shown in FIG.

Next, as shown in FIG. 2, an Al wiring layer 9 is deposited with the W residue 8 remaining, patterning is completed, and a resist pattern 10 is obtained. Next, the Al wiring layer 9 is anisotropically etched. Etching conditions at this time include, for example, 50 SCCM of BCl3 /Cl2 each.
/50SCCM, and the etching pressure was approximately 0.1 Torr.
r. Etching is performed using a parallel plate type RIE (reactive ion etching) device under conditions of an RF output of approximately 500 W, and the Al wiring layer 9 and barrier metal 5 (
After finishing the etching at the interface of TiN), the tungsten residue 8 remaining on the barrier metal 5 is removed using a gas containing F under the same etching conditions as those for etching back the tungsten 6 in the prior art section. As mentioned above, the tungsten etch rate is 4000 angstroms/
Also, since the etching rate of TiN is 1000 angstroms/m, if you choose an etching time of 20 to 30 seconds, the W residue will be about 1000 angstroms at most, so the W residue 8 will be removed while leaving the barrier metal 5 (TiN). is completely removed. Further, in this case, the side walls of the Al wiring are not etched at all by the F-based gas, and a cross-sectional shape as shown in FIG. 3 is obtained.

Next, BCl3 and Cl2 shown in this section
The barrier metal 5 (TiN) is etched by system etching, and by performing appropriate over-etching until no underlying residue remains, a shape as shown in FIG. 4 is obtained. In this case, if the Al wiring material is, for example, Al-Si-Cu, the etching rate of BCl3, Cl2 based etching is approximately 8000 angstroms/m under the above conditions.
The etching rate of TiN is about 4000 angstroms/m.

As described above, in the above embodiment, barrier metal 5 (TiN) is deposited in the contact hole 3, tungsten 6 is deposited above the deposited barrier metal 5 so as to fill the contact hole 3, and the barrier metal 5 is Since the etch back is completed at the interface between the tungsten 6 and the barrier metal 5, and the Al wiring pattern 9 is formed above the tungsten 6, a flat tungsten plug and Al wiring layer can be formed. This has the effect of improving reliability.

Further, in the above embodiment, tungsten 6
When forming the Al wiring pattern 9' above, the Al
A resist pattern 10 is formed on the wiring layer 9, and using the resist pattern 10 as a mask, the aluminum wiring layer 9 is etched by anisotropic etching containing BCl3 and Cl2 to the interface between the aluminum wiring layer 9 and the barrier metal 5. Tungsten 6 on the barrier metal 5 around the contact hole 3 is removed by plasma etching containing SF6.
Since the resist pattern 10 and the barrier metal 5 around the contact hole 3 are etched away by anisotropic etching containing BCl3 and Cl2, the barrier metal 5 is removed by etching back the tungsten 6. The remaining W residue 8 can be removed without denting the upper end surface of the Al wiring pattern 9' formed above.

It goes without saying that the above series of etchings is preferably performed continuously in a vacuum, whether in a single processing chamber or in multiple processing chambers. Also, as a matter of course, post-treatment for preventing after-corrosion should be performed continuously in a vacuum in a different treatment chamber after etching the barrier metal 5 (TiN), if possible. For example, CF4/O2 is heated at 100 SC each in a plasma processing chamber with an anode-coupled parallel plate.
CM/10SCCM flow, gas pressure is 0.4 Torr,
The RF output is about 150 W, and after-corrosion can be completely prevented by processing for about 20 to 40 seconds.

Furthermore, in the above embodiment, F-based gas plasma treatment is performed to remove the W residue 8, but this replaces the Cl-based deposits that adhered to the etched side surfaces during etching of the Al wiring layer 9 with F-based. There are also side effects that aid in the post-processing described above.

In the above embodiment, a parallel plate type etching apparatus was used for etching the Al wiring layer 9 and the barrier metal 5 (TiN), but a microwave plasma type etcher (for example, an RF bias applied microwave Even if a plasma etcher (such as Hitachi M-308AT) is used, the same effect as in the above embodiment can be obtained.

[0024] Also, for post-processing, we assumed a plasma processing chamber having an anode-coupled parallel plate.
A similar effect can be obtained by using a microwave asher type post-processing device. In this case, the gases are O2 /CF4,
The use of one or two gas mixtures of CHF3 is sufficiently effective.

In the above embodiment, the case of contact holes has been described, but similar effects can be obtained even if applied to interlayer connection holes of other multilayer interconnections.

[0026]

As described above, according to the present invention, a barrier metal is deposited in the contact hole or the interlayer connection hole of the multilayer wiring and on the upper surface of the substrate, and the barrier metal is deposited in the contact hole or the multilayer wiring above the deposited barrier metal. A high melting point metal is deposited so as to fill the interlayer connection hole, and the high melting point metal is etched back so as to leave the barrier metal on the substrate around the contact hole or the interlayer connection hole of the multilayer wiring, and wiring is formed above the high melting point metal. Since a pattern is formed, the top surface of the high melting point metal deposited to fill the contact or interlayer connection hole of multilayer wiring becomes flush with the top surface of the smooth coat film or interlayer insulating film, and is then flattened and deposited later. Deterioration of coverage at the top and bottom ends of contact holes or interlayer connection holes in the wiring layer is eliminated, and the wiring can be flattened, reducing the reduction in wiring life due to electromigration and improving the reliability of the resulting semiconductor device. It has the effect of improving.

Further, according to the present invention, when forming the wiring pattern, a resist pattern is formed on the wiring layer, and using the resist pattern as a mask, the wiring layer is coated with an anisotropic coating containing chlorine-based gas. The interface between the wiring layer and the barrier metal is etched away by chemical etching, and the high melting point metal residue on the barrier metal around the contact hole or the interlayer connection hole of the multilayer wiring is etched away by plasma etching containing fluorine-based gas. , the resist pattern and the barrier metal around the contact hole or the interlayer connection hole of the multilayer wiring are etched away by anisotropic etching containing chlorine-based gas, so that the barrier metal is removed by etching back the high melting point metal. The high melting point metal residue remaining on the metal can be removed without denting the upper end surface of the wiring pattern formed above.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional structural diagram showing one step following FIGS. 6 and 7 of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional structural diagram showing one step following FIG. 1 of the method of the present invention.

FIG. 3 is a cross-sectional structural diagram showing one step following FIG. 2 of the method of the present invention.

FIG. 4 is a cross-sectional structural diagram showing one step following FIG. 3 of the method of the present invention.

FIG. 5 is a graph showing a method for detecting an end point during W etchback according to an embodiment of the present invention.

FIG. 6 is a cross-sectional structural diagram showing one step of a conventional semiconductor device manufacturing method.

FIG. 7 is a cross-sectional structural diagram showing one step following FIG. 6 of the conventional method.

FIG. 8 is a cross-sectional structural diagram showing one step following the conventional process shown in FIG. 7;

FIG. 9 is a cross-sectional structural diagram showing one step following the conventional process shown in FIG. 8;

FIG. 10 is a cross-sectional structural diagram showing one step following the conventional process shown in FIG. 9;

[Explanation of symbols]

1 Silicon (Si) substrate 2 Smooth coat film 3 Contact hole 4 Diameter of contact hole 5 Barrier metal TiN 6 Tungsten (W) 6’　W inside the contact hole 6” W inside the contact hole 7 Al wiring layer 7’ Al wiring 8 W residue 9 Al wiring layer 9’ Al wiring 10 Resist pattern 10' resist pattern

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device in which a high-melting point metal is embedded in a contact hole or an interlayer connection hole of a multilayer wiring, and a wiring layer is formed thereon, wherein the contact hole or the interlayer connection hole of a multilayer wiring includes: and a step of depositing a barrier metal on the upper surface of the substrate, a step of depositing a high melting point metal above the deposited barrier metal so as to fill the contact hole or the interlayer connection hole of the multilayer wiring, and a step of depositing the barrier metal on the contact hole or the multilayer wiring. A method for manufacturing a semiconductor device, comprising the steps of: etching back the high melting point metal so as to leave it on the substrate around the interlayer connection hole of the wiring; and forming a wiring pattern above the high melting point metal. 2. The step of forming the wiring pattern comprises:
forming a wiring layer above the high melting point metal and forming a resist pattern on the wiring layer; using the resist pattern as a mask, the wiring layer is anisotropically etched using a chlorine-based gas; a step of etching away the high melting point metal residue on the barrier metal around the contact hole or the interlayer connection hole of the multilayer wiring by plasma etching containing fluorine-based gas; 2. The semiconductor device according to claim 1, further comprising the step of etching away the resist pattern and the barrier metal around the contact hole or the interlayer connection hole of the multilayer wiring by anisotropic etching containing a system gas. manufacturing method. 3. Aluminum is used as the wiring layer, titanium nitride is used as a barrier metal deposited in the contact hole or the interlayer connection hole of the multilayer wiring and on the upper surface of the substrate, and the contact hole or titanium nitride is used above the barrier metal. 3. The method of manufacturing a semiconductor device according to claim 1, wherein tungsten is used as the high melting point metal deposited to fill the interlayer connection holes of the multilayer wiring.