JPH04258151A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction of a circuit by voltage effect, etc., without reducing signal pins by separating the ground bus lines of a plurality of circuits systems such as inner circuits, outer buffer circuits, etc., and further shorting them at a power pad part. CONSTITUTION:A ground bus line 4 for ECL output buffer and a gourd bus line 5 for inner cell are connected by a ground power pad 1, a connecting pattern 2 between the power source pad and the bus line, and a through hole 3. The ground bus line 4 for ECL output buffer is connected to the ground pattern 7 in ECL output buffer. And it supplies a ground current to the base of the output emitter follower transistor of the ECL output buffer. On the other hand, the ground bus line 5 for inner cell supplies a ground current to the inner circuit by a ground supply pattern 8 for inner cell. Hereby, it does not reduce signal pins and the malfunction of the circuit by voltage effect, etc., can be prevented.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor integrated circuits.
Especially regarding the layout of power supply lines.

0002

BACKGROUND OF THE INVENTION In semiconductor integrated circuits, power bus lines such as ground bus lines are laid out around the semiconductor chip, a part of which is connected to a bonding pad, and connected to the package ground using a bonding line or TAB. Common. FIG. 3 shows an example of the layout of a conventional semiconductor integrated circuit. The surface of the semiconductor chip has a power supply bus line 11, a connection pattern 12 between lower layer bus line pads indicated by a dashed line, a power supply voltage supply pattern 13 to the internal circuit, and a power supply voltage supply pattern 14 to an external buffer whose boundary is indicated by a broken line. are doing.

Next, a description will be given of how the internal circuit and external buffer operate and current flows through the power supply bus line 11. I
If 1 is the current flowing in the internal circuit, I2 is the current flowing in the external buffer, and R is the resistance value of the power bus line 11, then
A current of (I1+I2) flows through the power bus line 11,
Due to R, a potential difference of (I1+I2)R is generated between the power supply pad position and the current extraction point A.

0004

[Problems to be Solved by the Invention] In this conventional semiconductor integrated circuit, power supply current is supplied to multiple circuit systems through one bus line, so the amount of current flowing through the bus line increases and the resistance of the bus line increases. There have been drawbacks such as deterioration of circuit performance, malfunction, and shift in the output level of the output buffer due to the potential drop caused by this.

[0005]

[Means for Solving the Problems] A semiconductor integrated circuit of the present invention has a plurality of power supply bus lines of the same potential prepared for a plurality of circuit systems, and a power supply pad that short-circuits the plurality of power supply bus lines at at least one place. - A power supply bus line connection pattern and a power supply pad connected to the power supply pad-current bus line connection pattern.

Further, the semiconductor integrated circuit of the present invention is configured to have a ground bus line for an internal circuit and an external circuit of a master slice type having an internal circuit cell area and an external buffer cell area.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a plan view of a master slice type semiconductor device according to an embodiment of the present invention. A ground power supply pad 1, a power supply pad-bus line connection pattern 2 shown by a dashed line,
It is connected to an ECL output buffer ground bus line 4 and an internal cell ground bus line 5 through a through hole 3. The ECL output buffer ground bus line 4 corresponds to the ECL output buffer internal ground pattern 7 indicated by a dashed-dotted line.
is connected to supply ground current to the base of the output emitter follower transistor of the ECL output buffer. On the other hand, the internal cell ground bus line 5 supplies ground current to the internal circuit by the internal cell ground supply pattern 8.

This embodiment is an example of realizing a semiconductor integrated circuit having an ECL level input/output buffer, and FIG. 2 shows a schematic circuit configuration diagram. The common ground 7 corresponds to the ground power supply pad 1 and is connected to the ECL output buffer ground bus line 4 and the internal cell ground bus line, and is connected to the ECL output buffer ground bus line 4.
is connected to the base of the output emitter follower transistor of the ECL output circuit via a resistor. The collector of the output emitter follower transistor Q is connected to a dedicated ground bus line 9 in order to prevent noise caused by a large current during operation of this transistor from affecting the ECL output buffer ground bus line 4 and the like.

At this time, only a current equal to one of the current amplification factor of the current flowing through the dedicated ground bus line 9 flows through the ECL output buffer ground bus line 4, but since this directly affects the output level, the ECL output buffer ground bus line 4 The stability of the voltage level on line 4 is extremely important.

On the other hand, the current flowing through the internal cell ground bus line 5 becomes extremely large depending on the scale and operating frequency of the internal circuit 15. If the resistance value of the ECL output buffer ground bus line 4 is r1, and the resistance value of the internal cell ground bus line 5 is r2, then in this embodiment, the potential difference between the ECL output buffer section A point and the ground power supply pad 1 is r2. -I2, and since I2 is small as mentioned above, the value of this potential difference can be kept small.

On the other hand, since the internal circuit 7 does not require as much stability of the ground voltage level as the ECL output circuit, the potential difference r1
- There is no problem even if I1 is a little large. In this example, (I1+
The only portion through which the current I2) flows is the power pad-power bus line connection pattern 2, and the current path is very short, so the voltage effect in this portion is extremely small. Furthermore, since the power supply pads are shared and not dedicated to each power supply bus line, there is no need to reduce the number of signal pins.

0012

[Effects of the Invention] As explained above, the present invention separates the ground bus lines of multiple circuit systems such as internal circuits and external buffer circuits, and further short-circuits them at the power supply pad, thereby eliminating the need to reduce the number of signal pins. Moreover, it has the effect of preventing circuit malfunctions due to voltage effects and the like.

[Brief explanation of the drawing]

FIG. 1 is a plan layout diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of a semiconductor integrated circuit using the layout of FIG. 1;

FIG. 3 is a plan layout diagram of an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

1 Power supply pad 2 Connection pattern between power supply pad and power bus line 3
Through hole 4 Ground bus line 5 for ECL output buffer
Internal circuit ground bus line 6 Signal pad 7 ECL output buffer internal ground pattern 8
Ground pattern for internal circuit 9 Dedicated ground for ECL output buffer emitter follower 10 Negative power supply 11 Power bus line 12 Connection pattern between power pad and power bus line 13 Power bus line for internal circuit 14 Power bus line for external circuit 15 Internal circuit

Claims (2)

[Claims] 1. A plurality of power supply bus lines with the same potential prepared for a plurality of circuit systems, a connection pattern between a power supply pad and a power supply bus line that short-circuits a plurality of the power supply bus lines at at least one point, and the power supply bus line. 1. A semiconductor integrated circuit comprising a power supply pad connected to a pad-current bus line connection pattern. 2. The semiconductor integrated circuit according to claim 1, further comprising ground bus lines for an internal circuit and an external circuit of a master slice type having an internal circuit cell area and an external buffer cell area.