JPH04258062A - Fsk signal modulator/demodulator circuit - Google Patents

Abstract

PURPOSE:To reduce the test time by testing a built-in analog filter in the inside of an FSK MODEM circuit and testing the filter without installing an exclusive analog tester externally at mass-production of a semiconductor integrated circuit or the like including the FSK MODEM circuit. CONSTITUTION:A 1st multiplexer 1 connects to a filter circuit (BPF) 2 by selecting an FSK input terminal or an output of an FSK modulation circuit 7, and a 2nd multiplexer connects to an output terminal of the filter circuit 2 and to an input terminal of an FSK demodulation circuit 6 and an input terminal of a level detection circuit 5 or an FSK signal output terminal switchingly. A test control circuit 8 outputs a test frequency signal to the FSK modulation circuit 7 to revise a detection level of the level detection circuit 5. A discrimination circuit 4 fetches an output signal of the level detection circuit 5 to discriminate the coincidence with a setting value and to output the result of discrimination.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FSK modulation/demodulation circuit, and more particularly to an FSK modulation/demodulation circuit having a built-in analog filter test circuit.

0002

2. Description of the Related Art The FSK (Frequency Shift Keying) method is one of the general methods used for data communication using modems, acoustic couplers, etc. ” is assigned to a low frequency and transmits data.

FIG. 8 shows a waveform diagram of an FSK modulation/demodulation signal,
FIG. 8(a) shows the original binary signal of data (transmission or demodulation data), and FIG. 8(b) shows the FSK signal.

Semiconductor integrated circuits with built-in FSK modulation and demodulation functions are generally used for data communications, but semiconductor integrated circuits with built-in sophisticated and complex functions are designed to allow easy testing of their functions. It is required to keep it.

An example of a conventional FSK signal modulation/demodulation circuit is a circuit shown in FIG.

[0006] Referring to the figure, first, a case will be described in which a demodulation operation of an FSK signal is performed. A received FSK signal (FIG. 8(b)) inputted to an input terminal 10 through a telephone line or the like is inputted to a filter section 2 through a multiplexer circuit (hereinafter referred to as an MPX circuit) 1. The filter section 2 is composed of an analog bandpass filter, and functions to remove unnecessary frequency components of the input received FSK signal. The received FSK signal from which unnecessary frequency components have been removed is input to a level detection circuit 5 and a demodulation circuit 6 through an MPX circuit 3.

[0007] The received FSK signal input to the level detection circuit 5 outputs the output terminal 12 to a high level only when the received power of the signal is higher than the effective reference level (for example, -40 dBm), and outputs the FSK signal at a level that can be demodulated. It is designed to notify the outside that the signal has been received. Similarly, the demodulation unit 6 which receives the received FSK signal that has passed through the filter unit 2 converts the received FSK signal into an original binary signal (FIG. 8(a)) using, for example, a digital counting method.
is demodulated and the demodulation result is output to the output terminal 13.

Next, when the transmission data is modulated into an FSK signal and transmitted, the transmission data inputted from the input terminal 14 (FIG. 8(a)) is converted into an FSK signal by the modulation section 7 using a frequency synthesizer method or the like. After being modulated, the signal is input to a filter section 2 through an MPX circuit 1, and its unnecessary frequency components are removed. The transmitted FSK signal from which unnecessary frequency components have been removed passes through the MPX circuit 3, is output from an output terminal, and is transmitted through, for example, a telephone line.

In the case of this FSK modulation/demodulation circuit, an analog bandpass filter is used in the filter section 2 in order to remove unnecessary frequency components of the input/output FSK signal. For this reason, when evaluating FSK modulation/demodulation circuits or
When mass producing semiconductor integrated circuits including modulation/demodulation circuits,
It is necessary to test the frequency characteristics of analog bandpass filters.

Conventionally, when testing the frequency characteristics of a built-in analog filter, first the test terminal 15 is set to a high level, and the frequency signal input from the input terminal 10 is
The signal is input to the filter section 2 through the MPX circuit 1, and the output signal of the filter section 2 is set to be outputted to the output terminal 9 through the MPX circuit 3. Its input terminal 10
The frequency characteristics of the filter section 2 can be tested by sequentially inputting signals of various frequencies to the filter and measuring the output level of the frequency signal output from the output terminal 9 for each input frequency signal.

For example, when the filter section 2 exhibits a frequency characteristic as shown in FIG. We were testing whether the frequency characteristics were as designed. A dedicated measuring instrument or analog tester is used for this test.

0012

[Problem to be solved by the invention] The above-mentioned conventional FSK
The modulation/demodulation circuit inputs a predetermined frequency signal from the outside to test the frequency characteristics of the built-in analog filter, and also inputs a predetermined frequency signal from the outside to measure the output level of the frequency signal output from the analog filter. It was necessary to use dedicated installed measuring instruments or analog testers.

[0013]Recently, it has become possible for FSK modulation/demodulation circuits to consist of digital circuits for most of the parts except for the analog filter part, but since the analog filter part requires a dedicated tester, the FSK modulation/demodulation circuit When mass producing semiconductor integrated circuits with built-in circuits, it becomes necessary to test them using two testers: a digital tester for testing the digital circuit section, and an analog tester for testing the analog filter section.

[0014] Therefore, when mass producing semiconductor integrated circuits with built-in FSK modulation/demodulation circuits, different types of expensive testers are required, and the cost of testing becomes extremely high.
Furthermore, it has a major drawback in that the test time becomes long.

An object of the present invention is to provide a circuit with means for generating a predetermined frequency for testing an analog filter and means for determining the level of a frequency signal that has passed through the analog filter. Sometimes,
There is no need to input a frequency signal from the outside and measure the output level of the frequency signal after passing through an analog filter.
An object of the present invention is to provide an FSK modulation/demodulation circuit that requires fewer testing steps.

[0016]

[Means for Solving the Problems] The configuration of the FSK modulation/demodulation circuit of the present invention modulates a frequency shift keying signal (hereinafter referred to as FSK signal) whose frequency changes corresponding to a binary digital signal, and modulates a plurality of different frequencies. F that generates a test signal of
an SK modulation circuit; a filter circuit that passes a desired frequency band of the FSK signal; a first multiplexer circuit that switches and connects an FSK signal input terminal or an output terminal of the FSK modulation circuit to an input terminal of the filter circuit; The output terminal of the filter circuit is connected to the input terminal of the FSK demodulation circuit and the input terminal of the level detection circuit, or the FS
a second multiplexer circuit switchably connected to the K signal output terminal; a test control circuit that causes the FSK modulation circuit to output a test frequency signal and controls a change in the detection level of the level detection circuit; and a determination circuit that takes in the output signal, determines whether it matches a predetermined set value, and outputs the determination result, and the test control signal from the test control circuit is
A test frequency signal of the FSK modulation circuit that is input to the FSK modulation circuit is input from the first multiplexer circuit and supplied to the level detection circuit.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an embodiment of the present invention, showing an FSK modulation/demodulation circuit incorporating an analog filter test circuit.

This FSK modulation/demodulation circuit includes a demodulation section 6 that demodulates received data from a received FSK signal, and a demodulation section 6 that demodulates received data from a received FSK signal.
The multiplexer circuit 1 includes a modulation unit 7 that modulates the received FSK signal into a K signal, and a level detection circuit 5 that determines whether the received level of the received FSK signal has reached a predetermined reference level. and the transmitted FSK signal from the modulation section 7 are selected and input to the filter section 2, which consists of an analog bandpass filter for removing unnecessary frequency components of the input/output FSK signal. The output of the filter section 2 is selected by the multiplexer circuit 3 to be output to the level detection circuit 5 and the demodulation section 6, or to be output to the outside through the output terminal 9.

Further, the test control circuit 8 controls the test operation when testing the filter, and the determination circuit 4 determines the result of the filter test.

First, when the FSK modulation/demodulation circuit performs normal modulation/demodulation operation, by keeping the test terminal 15 at a low level, the test signal 16 remains at a low level, and the modulation section 7, multiplexer circuits 1 and 3, and level detection circuit 5. The determination circuit 4 enters the normal modulation/demodulation mode.

At this time, in the case of demodulation operation, the input terminal 10
After the FSK signal is input from the multiplexer circuit 1
Unnecessary frequency components are removed by the filter section 2 through the filter section 2. After that, it passes through the multiplexer circuit 3, and the received FSK
The signal is judged by the level detection circuit 5, and if the signal has reached the effective reception level, the result is notified to the outside by setting the output terminal 12 to a high level, and at the same time, the demodulation unit 6 sets it to "1". The received data is demodulated to “0” and output to the output terminal 13.

In addition, when performing a modulation operation, the transmission data input from the input terminal 14 is modulated into an FSK signal by the modulation section 7, passes through the multiplexer circuit 1, and unnecessary frequency components are removed by the filter section 2. The signal is then passed through the multiplexer circuit 3 and outputted through the output terminal 9.

Next, the case of testing the analog filter built into the FSK modulation/demodulation circuit will be explained with reference to FIG.

When testing the analog filter, first, the test terminal 15 is set to high level, and the modulation section 7
, multiplexer circuits 1 and 3, level detection circuit 5, and determination circuit 4 are in test mode. In this test mode, a test frequency signal (for example, frequencies f1 to f4 in FIG. 7) specified by the control signal 17 and preset in the modulator 7 is output from the modulator 7. This control signal 17 has a test frequency signal of 4 as shown in the figure.
In the case of a type, it is 2 bits.

The multiplexer circuits 1 and 3 are set so that the test frequency signal output from the modulation section 7 passes through the filter section 2 and then is input to the level detection circuit 5 and the demodulation section 6. Next, in the test mode, the determination reference level of the level detection circuit 5 is changed according to the test frequency by the control signal 17 from the test control circuit 8.

For example, when the test frequency signal output from the modulation section 7 is f1 as shown in FIG.
If the frequency characteristics of the signal are as designed, the level detection circuit 5 will output a low level. Furthermore, when the test frequency signal is f2, the level detection circuit 5
In this case, when the frequency characteristic of the filter unit 2 is as designed, the level detection circuit 5 outputs a high level.

In the determination circuit 4, the detection circuit of the level detection circuit 5 according to the test frequency signal output from the modulation section 7 determines whether the frequency characteristics of the filter section 2 are as designed.

The internal block diagram of this judgment circuit 4 is shown in FIG. 2, and the timing chart showing its operation is shown in FIG.
become that way.

The determination circuit 4 includes registers 19 to 22 for storing the determination results of the level detection circuit 5, a determination decoder circuit 24 for determining the frequency characteristics of the filter from the contents stored in the registers, and these registers 19 to 22. The timing control circuit 23 generates the latch signal and the judgment timing of the judgment decoder circuit 24.

Next, a filter test is performed at timings T1 to T6. First, as shown in FIG. 3, by setting the test terminal 15 to a high level at timing T1, since the control signal 17 is "00", the test frequency signal f1 is output from the modulation section 7, and the test frequency signal f1 is outputted from the filter section 7. The result determined by the level detection circuit 5 is inputted to the determination circuit 4 through the input terminal 18.

In the determination circuit 4, the determination result of the level detection circuit 5 is stored in the register 19 by the latch signal 25 from the timing control circuit 23, as shown in FIG. Similarly, at timings T2 to T4, as the control signal 17 changes, the test frequency signals f2 to f2 are also applied to the registers 20 to 22.
The determination result at f4 is stored. And timing T
5, at T6, by the determination timing signal 29,
In the judgment decoder circuit 24, even when the stored results of the registers 19 to 22 are equal to the preset values, that is, in the case of this embodiment, the outputs of the registers 19 to 22 are "0110".
Only in this case, a high level is output to the output terminal 11 to test whether the filter characteristics are as designed.

FIG. 4 is a block diagram showing a second embodiment of the present invention. The figure shows that an FSK modulation/demodulation circuit and a central processing circuit (hereinafter referred to as CPU) 30 are configured on the same semiconductor integrated circuit. The CPU 30 can easily implement the functions of the determination circuit 4 and the test control circuit 8 as part of the functions using software.

FIG. 5 shows an example of a flowchart for realizing the functions of the determination circuit 4 and test control circuit 8 by the CPU 30.

[0034]

[Effects of the Invention] As explained above, in the present invention, the built-in analog filter can be tested inside the FSK modulation/demodulation circuit. Filters can be tested without installing a dedicated analog tester externally, which has the effect of minimizing testing costs and significantly shortening testing time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram of the determination circuit 4 in FIG. 1.

FIG. 3 is a timing diagram showing the operation of the determination circuit 4.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a flowchart showing the operation of the second embodiment of FIG. 4;

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a frequency characteristic diagram of the filter section 2.

FIG. 8 is a waveform diagram illustrating an FSK signal.

[Explanation of symbols]

1, 3 Multiplexer circuit 2 Filter section 4 Judgment circuit 5 Level detection circuit 6 Demodulation section 7 Modulation section 8 Test control circuits 9, 11 to 13 Output terminals 10, 14, 15, 18 Input terminals 16, 17
Test control signals 19-22 Register 23 Timing control circuit 24 Judgment decoder circuits 25-28 Latch signal 29 Judgment timing signal 30 CPU

Claims (1)

[Claims] 1. An FSK modulation circuit that modulates a frequency shift keying signal (hereinafter referred to as an FSK signal) whose frequency changes in accordance with a binary digital signal and generates a plurality of test signals of different frequencies, and the FSK signal. a first multiplexer circuit that switches and connects an FSK signal input terminal or an output terminal of the FSK modulation circuit to an input terminal of the filter circuit; a second multiplexer circuit switchably connected to the input terminal of the demodulation circuit and the input terminal of the level detection circuit or the FSK signal output terminal; and a second multiplexer circuit configured to cause the FSK modulation circuit to output a test frequency signal and to detect the detection level of the level detection circuit. a test control circuit that controls changes in the level detection circuit; and a determination circuit that takes in the output signal of the level detection circuit, determines whether it matches a predetermined set value, and outputs the determination result; A test control signal from a test control circuit is input to the FSK modulation circuit, and a test frequency signal of the FSK modulation circuit is input from the first multiplexer circuit and supplied to the level detection circuit. An FSK modulation/demodulation circuit featuring: