JPH04253363A - Lead frame and semiconductor device using the same - Google Patents

Lead frame and semiconductor device using the same

Info

Publication number
JPH04253363A
JPH04253363A JP942691A JP942691A JPH04253363A JP H04253363 A JPH04253363 A JP H04253363A JP 942691 A JP942691 A JP 942691A JP 942691 A JP942691 A JP 942691A JP H04253363 A JPH04253363 A JP H04253363A
Authority
JP
Japan
Prior art keywords
die pad
inner lead
semiconductor element
lead frame
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP942691A
Other languages
Japanese (ja)
Inventor
Akira Koga
彰 小賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP942691A priority Critical patent/JPH04253363A/en
Publication of JPH04253363A publication Critical patent/JPH04253363A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Abstract

PURPOSE:To prevent contact between a thin metal wire and a die pad and that between inner leads by covering from a location near a mount surface of a semiconductor element to be loaded to a tip of the inner lead and then providing an insulation layer which is fixed to the die pad and the inner lead. CONSTITUTION:An insulation layer 7 covers from a location near a mount surface of a semiconductor element 1 to a tip of an inner lead 4 on a surface for loading the semiconductor element 1 on a die pad 2 and at the same time is fixed to the die pad 2 and the inner lead 4. Therefore, even if a thin metal wire 5 is deformed downward, the thin metal wire 5 does not directly contact a location near an end face of the die pad 2 by the insulation layer 7. Also, when a similar stress is applied to the inner lead 4, the inner lead 4 cannot be deformed since a tip portion of the inner lead 4 is fixed by the insulation layer 7 and adjacent inner leads 4 do not contact each other.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、樹脂封止される半導体
装置のリードフレームの構造と、それを用いた半導体装
置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a lead frame for a semiconductor device sealed with resin, and a semiconductor device using the lead frame.

【0002】0002

【従来の技術】近年、半導体装置は低価格で大量生産が
可能なように樹脂封止型のものが主流となっている。
2. Description of the Related Art In recent years, resin-sealed semiconductor devices have become mainstream in order to enable mass production at low cost.

【0003】以下に従来の樹脂封止型半導体装置につい
て図3を用いて説明する。図3において、半導体素子1
はダイパッド2の上面にたとえば導電性樹脂などで接着
され、半導体素子1の電極とアウターリード3に連設さ
れたインナーリード4とを金属細線5によって接続し、
その周囲を封止樹脂6によって封止成形されている。半
導体装置を動作させると一般に半導体素子1は発熱する
。発生した熱は半導体素子1の上方に向っては封止樹脂
6を介して、下方に向ってはダイパッド2から封止樹脂
6を介して、側方に向っては金属細線5からインナーリ
ード4や封止樹脂6を介して、または封止樹脂6のみを
介してそれぞれ空気中に放散されたり、一部アウターリ
ード3を介して実装される基板に放散される。
A conventional resin-sealed semiconductor device will be described below with reference to FIG. In FIG. 3, semiconductor element 1
is bonded to the upper surface of the die pad 2 with, for example, a conductive resin, and the electrode of the semiconductor element 1 and the inner lead 4 connected to the outer lead 3 are connected by a thin metal wire 5.
The periphery thereof is sealed and molded with a sealing resin 6. When a semiconductor device is operated, the semiconductor element 1 generally generates heat. The generated heat is transferred upwardly to the semiconductor element 1 via the sealing resin 6, downwardly from the die pad 2 via the sealing resin 6, and laterally from the thin metal wire 5 to the inner lead 4. It is dissipated into the air through the sealing resin 6 or only through the sealing resin 6, or is partially dissipated into the board mounted via the outer lead 3.

【0004】一般にダイパッド2、インナーリード4お
よびアウターリード3はたとえばFe−Ni合金やCu
合金のような金属材料が用いられており、封止樹脂6に
比べ熱伝導性が高いので、半導体装置全体に占めるダイ
パッド2などの金属部分の割合を大きくすることは、熱
放散性を高める上で有利なる。
Generally, the die pad 2, inner leads 4, and outer leads 3 are made of, for example, Fe--Ni alloy or Cu.
Since a metal material such as an alloy is used and has higher thermal conductivity than the sealing resin 6, increasing the proportion of metal parts such as the die pad 2 in the entire semiconductor device is effective in improving heat dissipation. It's advantageous.

【0005】[0005]

【発明が解決しようとする課題】しかしながら上記の従
来の構成では、特にダイパッド2を大きくした場合、樹
脂封止工程中の注入樹脂の圧力や、樹脂封止工程以前の
たとえば搬送中における外的応力などにより、金属細線
5が変形し、ダイパッド2の端面付近に接触し、電気的
不良を引き起こす可能性が高くなるという欠点を有して
いた。
[Problems to be Solved by the Invention] However, in the above-mentioned conventional structure, especially when the die pad 2 is enlarged, pressure of the injected resin during the resin sealing process and external stress during transportation before the resin sealing process are affected. As a result, the thin metal wire 5 is deformed and comes into contact with the vicinity of the end surface of the die pad 2, which increases the possibility of causing electrical failure.

【0006】また、インナーリード4の先端部はインナ
ーリード4が長くなればそれだけ外的応力に対して不安
定になり、ワイヤーボンド工程(金属細線5による結線
工程)での結線不良や、樹脂封止工程での樹脂注入圧力
によって引き起こされるインナーリード4の変形やイン
ナーリード4同士の接触による電気的不良の危険性が高
くなるといった欠点も有していた。
[0006] Furthermore, the longer the inner lead 4 becomes, the more unstable the tip end of the inner lead 4 becomes with respect to external stress, leading to poor connection in the wire bonding process (connection process using the thin metal wire 5) and resin sealing. It also has drawbacks such as an increased risk of electrical failure due to deformation of the inner leads 4 caused by the resin injection pressure in the stopping process and contact between the inner leads 4.

【0007】本発明は上記従来の問題を解決するもので
、熱放散性が高く、かつ製造工程中における金属細線5
とダイパッド2との接触不良、金属細線5とインナーリ
ード4との結線不良、インナーリード4同士の接触不良
などが発生しない構造を有するリードフレームおよびそ
れを用いた半導体装置を提供することを目的とするもの
である。
The present invention solves the above-mentioned conventional problems, and has high heat dissipation properties and a thin metal wire 5 during the manufacturing process.
The purpose of the present invention is to provide a lead frame having a structure that does not cause poor contact between the metal wire 5 and the die pad 2, poor connection between the thin metal wire 5 and the inner leads 4, and poor contact between the inner leads 4, and a semiconductor device using the lead frame. It is something to do.

【0008】[0008]

【課題を解決するための手段】上記課題を解決するため
に本発明のリードフレームおよびそれを用いた半導体装
置は、ダイパッド上の半導体素子積載面の、この積載さ
れた半導体素子の側面近傍位置からインナーリード4の
先端までを覆うとともに、ダイパッドおよびインナーリ
ードに固定された絶縁層を備えたリードフレームに構成
されたものであり、さらにこのリードフレームを用いて
、半導体素子とインナーリードとの接続を金属細線で行
い、さらに全体を樹脂封止して半導体装置を構成したも
のである。
[Means for Solving the Problems] In order to solve the above problems, the lead frame of the present invention and a semiconductor device using the same are provided such that the lead frame of the present invention and the semiconductor device using the same are provided from a position near the side surface of the semiconductor element loaded on the semiconductor element loading surface on the die pad. It is configured as a lead frame that covers up to the tips of the inner leads 4 and has an insulating layer fixed to the die pad and the inner leads, and further uses this lead frame to connect the semiconductor element and the inner leads. The semiconductor device is constructed by using thin metal wires and then encapsulating the entire structure with resin.

【0009】[0009]

【作用】この構成によって、ダイパッドと金属細線は絶
縁層により完全に絶縁され、かつインナーリードは先端
が絶縁層により固定されるため外力による影響を受けな
くなる。
[Operation] With this structure, the die pad and the thin metal wire are completely insulated by the insulating layer, and the tips of the inner leads are fixed by the insulating layer, so that they are not affected by external forces.

【0010】0010

【実施例】以下本発明の一実施例について、図面を参照
しながら説明する。図1は本発明一実施例を示す半導体
装置の断面図、図2は本同半導体装置のリードフレーム
のワイヤーボンド後の様子を示した上面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a semiconductor device showing an embodiment of the present invention, and FIG. 2 is a top view showing a lead frame of the same semiconductor device after wire bonding.

【0011】図1および図2において、1は半導体素子
、2はダイパッド、3はアウターリード、4はインナー
リード、5は金属細線、6は封止樹脂であり、従来のも
のと同じような構成を有する。7は絶縁層であり、ダイ
パッド2上の半導体素子1積載面の、この積載された半
導体素子1の側面近傍位置からインナーリード4の先端
までを覆うとともに、ダイパッド2およびインナーリー
ド4に固定されている。
In FIGS. 1 and 2, 1 is a semiconductor element, 2 is a die pad, 3 is an outer lead, 4 is an inner lead, 5 is a thin metal wire, and 6 is a sealing resin, which has the same structure as the conventional one. has. Reference numeral 7 denotes an insulating layer, which covers the semiconductor element 1 loading surface on the die pad 2 from a position near the side surface of the loaded semiconductor element 1 to the tip of the inner lead 4, and is fixed to the die pad 2 and the inner lead 4. There is.

【0012】このように構成されたリードフレームおよ
びそれを用いた半導体装置について、以下その動作を説
明する。樹脂封止工程中の注入樹脂の圧力や、樹脂封止
工程以前のたとえば搬送中における外的応力などにより
、金属細線5が下方に変形しても、絶縁層7により金属
細線5とダイパッド2の端面付近とは直接接触すること
はない。また、同様の応力がインナーリード4に加わっ
た場合でもインナーリード4の先端部は絶縁層7によっ
て固定されているため、インナーリード4が変形するこ
とはなく、隣り合うインナーリード4同士が接触するよ
うな事態は起こらない。
The operation of the lead frame constructed in this manner and a semiconductor device using the lead frame will be described below. Even if the thin metal wire 5 is deformed downward due to the pressure of the injected resin during the resin sealing process or external stress before the resin sealing process, such as during transportation, the insulating layer 7 prevents the thin metal wire 5 and the die pad 2 from bonding. There is no direct contact with the vicinity of the end face. Further, even if a similar stress is applied to the inner leads 4, since the tips of the inner leads 4 are fixed by the insulating layer 7, the inner leads 4 will not be deformed, and adjacent inner leads 4 will come into contact with each other. Such a situation will not occur.

【0013】[0013]

【発明の効果】以上のように本発明によれば、ダイパッ
ド上の半導体素子積載面の、この積載される半導体素子
の側面近傍位置からインナーリード先端までを覆うとと
もに、ダイパッドおよびインナーリードに固定されるよ
うな絶縁層を設けたことにより、樹脂封止工程中の注入
樹脂の圧力や樹脂封止工程以前のたとえば搬送中におけ
る外的応力などによる金属細線とダイパッドの接触やイ
ンナーリード4同士の接触といった不良を防止すること
ができ、優れたリードフレームおよびそれを用いた半導
体装置を実現できるものである。
As described above, according to the present invention, the semiconductor element mounting surface on the die pad is covered from the position near the side surface of the semiconductor element to be loaded to the tip of the inner lead, and is fixed to the die pad and the inner lead. By providing an insulating layer that prevents contact between the thin metal wire and the die pad or contact between the inner leads 4 due to the pressure of the injected resin during the resin encapsulation process or external stress during transportation before the resin encapsulation process, It is possible to prevent such defects, and to realize an excellent lead frame and a semiconductor device using the lead frame.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例における半導体装置の断面図
である。
FIG. 1 is a cross-sectional view of a semiconductor device in one embodiment of the present invention.

【図2】同半導体装置のリードフレームのワイヤーボン
ド後の様子を示した上面図である。
FIG. 2 is a top view showing the state of the lead frame of the semiconductor device after wire bonding.

【図3】従来の半導体装置の断面図である。FIG. 3 is a cross-sectional view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1    半導体素子 2    ダイパッド 3    アウターリード 4    インナーリード 5    金属細線 6    封止樹脂 7    絶縁層 1 Semiconductor device 2 Die pad 3 Outer lead 4 Inner lead 5 Thin metal wire 6 Sealing resin 7 Insulating layer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  樹脂封止される半導体装置に用いられ
るリードフレームであって、ダイパッド上の半導体素子
積載面の、この積載された半導体素子の側面近傍位置か
らインナーリード先端までを覆うとともに、ダイパッド
およびインナーリードに固定された絶縁層を備えたリー
ドフレーム。
1. A lead frame used in a resin-sealed semiconductor device, which covers the semiconductor element mounting surface on a die pad from a position near the side of the loaded semiconductor element to the tip of an inner lead, and and a lead frame with an insulating layer fixed to the inner leads.
【請求項2】  リードフレームのダイパッド上の半導
体素子積載面の、この積載された半導体素子の側面近傍
位置からインナーリード先端まで絶縁層で覆うとともに
、この絶縁層がダイパッドおよびインナーリードに固定
されたリードフレームを用い、半導体素子とインナーリ
ードとの接続が金属細線で行われ、かつ全体が樹脂封止
されたことを特徴とする半導体装置。
2. The semiconductor element mounting surface on the die pad of the lead frame is covered with an insulating layer from a position near the side surface of the loaded semiconductor element to the tip of the inner lead, and this insulating layer is fixed to the die pad and the inner lead. A semiconductor device characterized in that a lead frame is used, a semiconductor element and an inner lead are connected by thin metal wires, and the whole is sealed with resin.
JP942691A 1991-01-30 1991-01-30 Lead frame and semiconductor device using the same Pending JPH04253363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP942691A JPH04253363A (en) 1991-01-30 1991-01-30 Lead frame and semiconductor device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP942691A JPH04253363A (en) 1991-01-30 1991-01-30 Lead frame and semiconductor device using the same

Publications (1)

Publication Number Publication Date
JPH04253363A true JPH04253363A (en) 1992-09-09

Family

ID=11720016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP942691A Pending JPH04253363A (en) 1991-01-30 1991-01-30 Lead frame and semiconductor device using the same

Country Status (1)

Country Link
JP (1) JPH04253363A (en)

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