JPH04253211A - Clock duty correcting circuit - Google Patents

Abstract

PURPOSE:To widen the allowable range of a duty ratio to be corrected concerning the clock duty correcting circuit to correct the duty ratio of a clock signal. CONSTITUTION:The clock signal as a correcting object is delayed for prescribed time by a first delay circuit 4 and by inputting the said delayed signal as the reset signal of an FF circuit 1, the duty ratio of the clock signal outputted from the said FF circuit 1 is corrected so as to be decided according to the time delay amount of the first delay circuit 4 as mentioned above. The clock signal as the correcting object is applied through an inverter 3 for polarity inversion to the first delay circuit 4 provided out of the device and delayed for prescribed time, and this delayed signal is inputted through an input buffer 5 to the reset terminal of the FF circuit 1. Therefore, the duty ratio of the clock signal outputted from the FF circuit 1 is corrected so as to be decided according to the time delay amount of the first delay circuit 4 as mentioned above.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock duty correction circuit for correcting the duty ratio of a clock signal.

0002

2. Description of the Related Art A conventional circuit configuration is shown in FIG. 5, and a time chart of the circuit is shown in FIG. In Figure 5, 1
is a flip-flop (
(hereinafter referred to as the FF circuit), 2 is the *Q of the FF circuit 1
This is a delay circuit (hereinafter referred to as the third delay circuit for convenience of explanation) that inputs a signal (* indicates polarity inversion) and outputs it to the reset terminal R of the FF circuit 1. The duty ratio of the output clock signal, which is the Q signal, is determined. Further, FIG. 6(a) shows the input clock signal to be corrected, and FIG. 6(b) shows the *Q signal of the FF circuit 1. Furthermore, FIG. 6(c) is a signal obtained by delaying the *Q signal (b) by the third delay circuit 2, and FIG. 6(d) is an output clock signal of the Q signal of the FF circuit 1. The operation of the conventional circuit will be explained below using FIGS. 5 and 6.

First, the input clock signal (
a) is input to the clock signal terminal C of the FF circuit 1, and at the rising edge of the signal (a), the Q signal and *Q signal are output as shown in FIGS. 6(b) and (d). The falling edge of this signal (b) is delayed by a certain amount in the third delay circuit 2 (the delay amount Td is fixed here) by a certain amount as shown in FIG. Enter R. Therefore, the FF circuit 1 outputs the Q signal and the *Q signal as shown in FIGS. 6(d) and 6(b), respectively. From the above results, it can be seen that the signal (d) of the FF circuit 1 rises after a certain amount of delay from the input clock signal (a), and rises by a certain amount of delay from the signal (b) at the third delay circuit 2. The time width αT0 is defined as the duty ratio α, which is the amount of time delayed by adding a certain amount of delay time (however, T0
is one cycle of the clock signal) output clock signal (d)
Output.

However, as mentioned above, since the signal (b) output from the FF circuit 1 is used as the reset signal, the removal time of the FF circuit 1 (from the release of the reset signal to the next input clock signal (a)) The duty ratio of the output clock signal (d) cannot be corrected to approximately 50% or more because of the minimum time to the rising edge of the output clock signal (d). Also, since they are in the same device, even if the duty ratio is set to a certain value (the delay amount Td of the third delay circuit is fixed to a certain value), the temperature and
The duty ratio of the output clock signal (d) fluctuates due to fluctuations such as power supply fluctuations, and the larger the delay amount, the larger the fluctuation range, and therefore correction distortion occurs in the corrected clock signal.

[0005]

[Problems to be Solved by the Invention] Therefore, the duty ratio of the corrected clock signal is limited to approximately 50% or less, and even if a clock signal with a certain duty ratio is generated, the correction may be made due to temperature power fluctuations within the device, etc. The problem is that the amount fluctuates. The present invention provides a clock duty correction circuit that can widen the allowable range of the duty ratio to be corrected and suppress fluctuations in the duty ratio due to variations in delay caused by temperature and power supply fluctuations in the device in which the duty correction circuit is built. The purpose is to

[0006]

[Means for Solving the Problems] The clock duty correction circuit of the present invention delays a clock signal to be corrected by a predetermined time in a first delay circuit 4, and inputs the delayed signal as a reset signal to the FF circuit 1. By this, the FF circuit 1
The duty ratio of the clock signal output from the first delay circuit 4 is corrected so that it is determined by the time delay amount of the first delay circuit 4.

In addition, the clock signal to be corrected is added to a first delay circuit 4 provided outside the device via a polarity inverting inverter 3 and delayed by a predetermined time, and this delayed signal is sent to an FF circuit via an input buffer 5. By inputting the clock signal to the reset terminal of the FF circuit 1, the duty ratio of the clock signal output from the FF circuit 1 is corrected so as to be determined by the time delay amount of the first delay circuit 4.

Furthermore, the clock signal is transmitted to a second delay circuit 6.
The configuration is such that the sum of the delay times of the polarity inversion inverter 3 and the input buffer 5 is set equal to the delay time of the second delay circuit 6.

[0009]

[Operation] In the present invention, by using the clock signal to be corrected as the reset signal of the FF circuit 1, the duty ratio to be corrected can be set over a wide range, and the first delay circuit 4 that determines the duty ratio is By installing this correction circuit internally or externally, applying a delay amount equivalent to the input/output delay amount to the clock signal to be corrected and using it as the clock signal of FF circuit 1, If the temperature characteristics and the like are the same, it is possible to send out a clock signal whose duty ratio is the delay amount determined by the delay circuit 4, regardless of the characteristics within the device.

0010

[Example] The present invention will be explained below using FIGS. 1 to 4. FIG. 1 is an example in which the first delay circuit 4 is provided within the device. In the figure, 1 is a conventional FF circuit as shown in FIG. Further, 3 is an inverter for inverting the polarity of the clock signal to be corrected, and 4 is a first delay circuit for delaying the output of the inverter 3. The output of the first delay circuit 4 is used as it is for the timing of the reset signal of the FF circuit 1. These 1, 3, and 4 constitute a duty correction circuit according to an embodiment of the present invention shown in FIG. Note that Figure 2 is Figure 1.
(a) is a clock signal to be corrected, and (b) is a clock signal to be corrected. After inverting the polarity of the clock signal (a) by an inverter 3, the inverted signal is delayed by a first delay circuit 4. This signal is used as the timing of the reset signal of the FF circuit 1 after the FF circuit 1 is reset. Also, the signal (c
) is the output clock signal of the FF circuit 1.

FIG. 3 shows an example in which the first delay circuit 4 is provided outside the device. In the figure, 3 is as shown in FIG. Note that 5 is an input buffer for inputting the output of the first delay circuit 4 into the device again with the same polarity, and the clock signal input to the input buffer 5 via the inverter 3 and the first delay circuit 4 is input as is. It is configured to be used for the timing of the reset signal of the FF circuit 1. and 6
is a second delay circuit configured so that the clock signal to be corrected has the same value as the sum of the delay amounts of the inverter 3 and the input buffer 5. These circuits 1 and 3 to 6 form a duty correction circuit according to another embodiment of the present invention. In Figure 4, (a) is the clock signal to be corrected, and (b) is the clock signal to be corrected (
a) Signal with inverted polarity, (c) is inverter 3
A signal obtained by delaying the output of by the first delay circuit 4, (d)
is a signal that is added to the FF circuit 1 by the output from the first delay circuit 4 via the input buffer 5 and is used as the timing of the reset signal of the FF circuit 1. And these signals (
b) to (d) determine the amount of delay that determines the duty ratio. Note that (e) is the delay (Δ
(b) is a signal delayed from the input clock signal (a) by the delay (Δd) required for inputting the input buffer 5, and (f) is the output clock signal. Below, the circuit of the present invention will be explained using FIGS. 1, 2, 3, and 4.

First, in FIGS. 1 and 2, FIG.
The clock signal (a) is inputted as shown in Fig. 1,
The inverter 3 and the first delay circuit 4 (fixed to a certain constant amount here) further delay Δb as shown in FIG. 2(b) and input it to the reset terminal R of the FF circuit 1. Further, a clock signal (a) is input to the clock signal terminal C of the FF circuit 1. Therefore, from the FF circuit 1, the signal (a)
A signal (b) that rises a certain time later than the rising edge of and is input from the delay of the first delay circuit 4.
A Q output (c) which is reset after a certain time delay from the falling edge of is sent out. That is, the duty ratio of the output clock signal is determined by the amount of delay of the first delay circuit 4 and the inverter 3.

In addition, in FIGS. 3 and 4, the clock signal (a) in FIG. 4 to be corrected is input to the FF circuit 1 as shown in FIG. The signal is delayed by Δb, its polarity is inverted, and sent out of the device. This signal (b) is further delayed by Δc in the first delay circuit 4 (here fixed at a certain amount) as shown in FIG. input into the reset terminal R of FF circuit 1.
Enter. Here, a signal obtained by delaying the clock signal (a) by the delay time of the inverter 3 and input buffer 5 by the second delay circuit 6 is input to the clock signal terminal C of the FF circuit 1 as shown in FIG. 4(e). Ru. This signal (e
) The signal (f), which is the Q output of FF circuit 1, is output at the rising edge of Sent out. From the above results,
As shown in FIG. 4, the delay time (falling edge) of the inverter 3 is Δb, the delay time (falling edge) of the input buffer 5 is Δd, and the delay time (rising edge) of the second delay circuit 6 is Δe.
Then, if Δb + Δd = Δe, if the variation in delay time due to temperature characteristics inside the device of this circuit is equal as described above, then this output clock signal (f)
The duty ratio αT0 is equal to the delay time (falling edge) Δc by the first delay circuit 4 shown in FIG. 4(c).

[0014]

[Effects of the Invention] As explained above, according to the present invention,
It can generate a clock signal that provides a wide range of duty ratios regardless of the duty ratio of the input clock signal, and can also be used as a clock duty correction circuit that can suppress fluctuations in duty ratio due to variations in delay due to fluctuations in temperature, power supply, etc. This has the effect of greatly improving characteristics problems.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a time chart of a circuit according to an embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of another embodiment of the present invention.

FIG. 4 is a diagram showing a time chart of a circuit according to another embodiment of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a conventional example.

FIG. 6 is a diagram showing a time chart of a conventional example circuit.

[Explanation of symbols]

1 is FF circuit 3 is the inverter 4 is the first delay circuit 5 is input buffer 6 is the second delay circuit

Claims (3)

[Claims] Claim 1: By delaying the clock signal to be corrected by a predetermined time in a first delay circuit (4) and inputting the delayed signal as a reset signal to the FF circuit (1),
A clock duty correction circuit characterized in that the duty ratio of the clock signal output from the FF circuit (1) is corrected so that it is determined by the amount of time delay of the first delay circuit (4). 2. A clock signal to be corrected is passed through a polarity inverting inverter (3) to a first delay circuit (4) provided outside the device, delayed by a predetermined time, and this delayed signal is sent to an input buffer (5). ) to the reset terminal of the FF circuit (1).
A clock duty correction circuit characterized in that the duty ratio of a clock signal output from the first delay circuit (4) is corrected so that the duty ratio thereof is determined by the amount of time delay of the first delay circuit (4). 3. The clock signal is transmitted through a second delay circuit (6
) to the FF circuit (1), and the above polarity inverter (3) and input buffer (5).
3. The clock duty correction circuit according to claim 2, wherein the sum of the delay times of said second delay circuit (6) is set equal to the delay time of said second delay circuit (6).