JPH04252689A - Image interpolating method - Google Patents

Abstract

PURPOSE:To obtain a more natural interpolation image without depending on a compression encoding system. CONSTITUTION:In three frames in which correlation detecting circuits 30, 32 are continued, a correlation between adjacent frames is detected. A switching control circuit 36 changes over a switch 34 so as to select the image data of a high correlation detected by the correlation detecting circuits 30, 32 in accordance with an error uncorrectable flag from an ECC decoding circuit 20.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image interpolation method.

0002

[Prior Art] Image transmission systems that digitize moving image signals and transmit image data via transmission lines such as optical fibers or communication satellites, or recording media such as magnetic tapes,
An error correction code that detects and corrects transmission errors is used, and the transmission errors are corrected by the error correction code on the receiving side (or reproduction side). For errors that cannot be corrected even with the error correction code, interpolation processing is performed to form an approximate value from surrounding pixels.

0003

SUMMARY OF THE INVENTION In order to prevent image quality from deteriorating during interpolation processing, peripheral pixels used for interpolation must be error-free. When high-efficiency encoding (image compression), which has been widely used in recent years, is employed, peripheral pixels that can be used for interpolation are limited. For example, in the DPCM (differential pulse code modulation) method, which is reset for each line, if an uncorrectable error occurs, the original data cannot be reproduced on the line containing the error. Therefore, only pixels included in the upper and lower lines can be used for interpolation in this case. In addition, in encoding systems that use orthogonal transform such as discrete cosine transform (DCT), when an uncorrectable error occurs, all pixels included in a transmission block (for example, 8 pixels vertically x 8 pixels horizontally) are The signal cannot be reproduced, and image quality deterioration cannot be prevented even by interpolation using the upper and lower lines.

[0004] As described above, even if interpolation is attempted within the same frame, depending on the encoding method, the effect may not be expected at all.

An object of the present invention is to provide an image interpolation method that can obtain more natural interpolated images regardless of the encoding method.

[0006]

The image interpolation method according to the present invention is characterized in that error-uncorrectable data of digitally transmitted moving image data is interpolated using image data of frames with high interframe correlation.

[0007]

[Operation] By using the above means, since image data adjacent in the time direction is used, a natural interpolated image can be obtained regardless of the compression encoding method within a frame.

[0008]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. 10 is an input terminal for an analog image signal, and 12 is an A/D that converts the analog image signal into a digital image signal.
Converter 14 is an encoder that encodes digital image signals with high efficiency; 16 is an encoder for detecting and correcting transmission errors that occur in recording and reproducing systems such as magnetic tapes and optical disks, and communication transmission systems such as optical fibers and communication satellites; This is an ECC addition circuit that adds an error detection and correction code (ECC). 18
is a transmission system, specifically a recording/reproducing system such as a magnetic tape or an optical disk, or a communication transmission system such as an optical fiber or a communication satellite.

20 is an EC corresponding to the ECC addition circuit 16.
A C decoding circuit 22 is a decoder corresponding to the encoder 14. The ECC decoding circuit 20 outputs the error-corrected data to the decoder 22, and outputs an error-correction impossible signal (flag) for the error-correctable data. This error uncorrectable signal (flag) is transmitted to the frame memories 33, 3.
5, the signal is delayed by two frames and is supplied to a switch control circuit 36, which will be described later. 24, 26, and 28 are serially connected frame memories, each with FIFO
Consists of (first-in, first-out) memory. 30 is a decoder 22
A correlation detection circuit 32 detects the correlation between the output of the frame memory 24 and the output of the frame memory 24, that is, the interframe correlation. 34 is frame memory 2
This is a switch that selects outputs 4, 26, and 28. The switch control circuit 36 switches the switch 34 based on the error correction impossible flag from the ECC decoding circuit 20 and the detection results of the correlation detection circuits 30 and 32. 38 is a D/A converter that converts the data selected by switch 34 into an analog signal, and 40 is an output terminal for the reproduced analog image signal.

FIG. 2 shows an example of the circuit configuration of the correlation detection circuits 30 and 32. 42 and 44 are image data input terminals, 44
is a subtracter that calculates the difference between image data input from input terminals 42 and 44. 48 is an adder, 50 is adder 4
The adder 48 and the D flip-flop 50 form an integrator. The output of the adder 48 obtained by adding the output of the subtracter 46 for one frame is output from the output terminal 52.

The operation of FIG. 1 will be explained. A/D converter 12
samples the analog image signal input to the input terminal 10 at a predetermined sampling rate, and
Convert to bit digital signal. The encoder 14 compresses the digital image signal output from the A/D converter 12, that is, performs high-efficiency encoding using DPCM encoding or ADCT encoding. This embodiment is not limited by the high-efficiency encoding method itself. ECC addition circuit 16
adds an error detection and correction code using a predetermined method.

The output of the ECC addition circuit 16 is input to the ECC decoding circuit 20 via a transmission system 18 consisting of a recording/reproducing system or a communication transmission system. During transmission in the transmission system 18, a transmission error occurs with a predetermined probability. The ECC decoding circuit 20 detects the presence or absence of an error, the position of the error, and whether or not it can be corrected in the data input from the transmission line 18, corrects the correctable error, and outputs the corrected error to the decoder 22. Furthermore, if there is an uncorrectable error, an error uncorrectable flag is output to the switch control circuit 36.

The decoder 22 decodes (expands) the data compressed by the encoder 14 and outputs the original image data to the frame memory 24 and the correlation detection circuit 30. Since the frame memories 24, 26, and 28 perform FIFO operation and are connected in series, data of three consecutive frame images are stored in the frame memories 24, 26, and 28 in sequence. The correlation detection circuit 30 detects the current frame (output of the decoder 22) and the previous frame (
output of the frame memory 24);
The correlation detection circuit 32 detects the frame one frame before the current one (output of the decoder 22) (output of the frame memory 24).
and the two previous frames (output of frame memory 26)
Detect the correlation between The correlation detection circuits 30 and 32 store the difference between two input frames of image signals for one frame, and calculate the amount of correlation.

The switch 34 connects the frame memory 24,
26 or 28 outputs can be selected, usually frame
The output of memory 26 is selected. Switch control circuit 3
6 learns the screen position of the uncorrectable error from the error uncorrectable flag from the ECC decoding circuit 20 and sends it to the correlation detection circuit 3.
From the outputs of 0 and 32, it can be known which of the front screen and the rear screen has a higher correlation with the output image of the frame memory 26. That is, the switch control circuit 36 switches the switch 34 to select image data at the same position on the screen that has a higher correlation, depending on the error correction impossible flag from the ECC decoding circuit 20.

The D/A converter 38 converts the image data output from the switch 34 into an analog signal, and outputs it to the output terminal 4.
An analog image signal reproduced from 0 is output.

FIG. 3 shows a block diagram of another embodiment of the present invention. This embodiment uses AD as a high-efficiency encoding method.
CT method is adopted.

110 is an analog image signal input terminal;
12 is an A/D converter, and 114 is an ADCT encoder, which converts DC within a DCT block, for example, 8×8 pixels.
It is separated into a DC component and an AC component by T-transform, the DC component is subjected to DPCM encoding between it and the previous DCT block, and the AC component is subjected to run-length processing and Huffman encoding. 116 is the A from ADCT encoder 114
This is an ECC addition circuit that adds an error detection and correction code to the encoded output of the C component and DC component.

118 is a transmission system, 120 is an ECC decoding circuit corresponding to the ECC addition circuit 116, and 122 is an ADCT decoder corresponding to the ADCT encoder 14. 12
4, 126, and 128 are serially connected frame memories, each consisting of a FIFO (first in, first out) memory. 129 and 130 are FIFO type frame memories that delay the DC component output from the ADCT decoder 122 by one frame, and are cascade-connected for correlation detection. 131 is the output of the decoder 122 and the frame
A correlation detection circuit detects inter-frame correlation with the output of the memory 129; 132 is a frame memory 129, 13;
This is a correlation detection circuit that detects interframe correlation from the output of zero. 134 is a switch for selecting the output of frame memories 24, 26, and 28; Switch control circuit 136
switches the switch 134 according to the error uncorrectable flag from the ECC decoding circuit 120 and the detection results of the correlation detection circuits 131 and 132. 138 is a D/A converter 1 that converts the data selected by the switch 34 into an analog signal;
40 is an output terminal for the reproduced analog image signal.

The characteristic operation of FIG. 3 will be explained. The A/D converter 112 converts the analog image signal input to the input terminal 110 into a digital signal, and converts the analog image signal input to the input terminal 110 into a digital signal.
performs DCT transformation on the digital image signal output from the A/D converter 112 within a DCT block, performs DPCM encoding on the DC component with the previous DCT block, and performs run length processing and Huffman encoding on the AC component. The ECC addition circuit 116 adds an error detection and correction code to the AC component output and DC component output of the ADCT encoder 114 using a predetermined method.

The output of the ECC addition circuit 116 is transmitted to the transmission system 1.
18 to the ECC decoding circuit 120. E.C.C.
The decoding circuit 120 receives AC and DC input from the transmission line 118.
The presence or absence of an error, the position of the error, and whether or not it is correctable are detected for the component data, correctable errors are corrected, and the corrected errors are output to the ADCT decoder 122. Furthermore, if there is an uncorrectable error, an error uncorrectable flag is output. This error uncorrectable flag is set in the frame memory 13.
3,135, the signal is delayed by two frames and is supplied to the switch control circuit 136.

ADCT decoder 122 converts the DC component into DP
CM decoding is performed, AC components are subjected to Huffman decoding and run-length decoding, and inverse DCT transformation is performed to restore the original image data. The image data restored by the ADCT decoder 122 is applied to the frame memory 124 and is also subjected to inverse DCT
Frame memory 129 whose DC component is a DC component before conversion
and is applied to the correlation detection circuit 131. Frame memories 124, 126, and 128 are frame memories 2 in FIG.
Similarly to 4, 26, and 28, data of three consecutive frame images are stored in sequence. Also, the frame
Since the memories 129 and 130 are also connected in cascade, the DC components of adjacent frames are stored for one frame. The correlation detection circuit 131 detects the current frame (
The correlation detection circuit 132 detects the correlation between the current frame (output of the decoder 122) and the previous frame (output of the frame memory 129). output) and the two previous frames (
(output of frame memory 130). The correlation detection circuits 131 and 132 may have the same circuit configuration as in FIG. 2, and store one frame's worth of DC component differences between two input frames of images. As a result, the interframe correlation amount can be obtained.

Switch 134 connects frame memory 12
4, 126, and 128 outputs can be selected, and normally the output of the frame memory 26 is selected. The switch control circuit 136 is similar to the switch control circuit 36 in FIG.
Control switch 134. That is, the switch 134 is
For data whose errors cannot be corrected, image data at the same position on the screen with a higher correlation is selected. D/A converter 1
38 converts the image data output from the switch 134 into an analog signal, and the reproduced analog image signal is output from the output terminal 140.

In the embodiment shown in FIG. 3, accurate correlation detection can be performed by using a DC component for correlation detection, so that more natural interpolation can be performed.

In the above embodiment, the decoder side (reception side)
Although a correlation detection circuit is disposed on the encoder side (transmission side), a correlation detection circuit may be disposed on the encoder side (transmission side) and correlation information may be transmitted between frames for each frame. In this way, the burden on equipment on the receiving side is significantly reduced. This is suitable for transmission systems such as television broadcasting, which have a large number of receivers and require the receiving device to be small and low-cost.

[0026]

As can be easily understood from the above explanation, according to the present invention, since error-uncorrectable data is interpolated using inter-screen correlation information, more natural interpolation can be performed.
A reproduced image (received image) with less unnaturalness can be provided.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

FIG. 2 is an example of a circuit configuration of correlation detection circuits 30 and 32.

FIG. 3 is a configuration block diagram of another embodiment of the present invention.

[Explanation of symbols]

10: Analog image signal input terminal 12: A/D converter 14: Encoder 16: ECC addition circuit
18: Transmission system 20: ECC decoding circuit 22: Decoder 24, 26, 28, 33, 35: Frame memory 30, 32: Correlation detection circuit 34: Switch 36
: Switch control circuit 38: D/A converter 40:
Output terminals 42, 44: Input terminal 44: Subtractor 4
8: Adder 50: D flip-flop 52: Output terminal 110: Image signal input terminal 112: A/
D converter 114: ADCT encoder 116: EC
C addition circuit 118: Transmission system 120: ECC decoding circuit 122: ADCT decoder 124, 126
, 128, 129, 130, 133, 135: Frame memory 131, 132: Correlation detection circuit 134
: Switch 136: Switch control circuit 138:
D/A converter 140: output terminal

Claims (1)

[Claims] 1. An image interpolation method characterized by interpolating uncorrectable error data of digitally transmitted moving image data with image data of frames with high interframe correlation.