JPH04252621A - Method for setting offset control voltage applied to voltage controlled oscillator and radio communication equipment of this method - Google Patents

Abstract

PURPOSE:To compensate offset control voltage data in consideration of the whole of a frequency synthesizer or the whole of a radio communication equipment with respect to the setting method for the offset control voltage applied to a voltage controlled oscillator at the time of channel switching and the radio communication equipment of this method. CONSTITUTION:In the radio communication equipment in the frequency heterodyne system provided with a local oscillator 200 of a PLL, a channel switching control part 500 is energized to open the PLL loop of the local oscillator 200 at the time of waiting for signals other than a transmission frame signal or a frame signal destined for its own station, and a prescribed offset control voltage DA is applied to the voltage controlled oscillator, and this prescribed offset control voltage DA is changed until the output of an intermediate frequency amplifier 400 is detected, and the offset control voltage at the time of detection is fixed.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention opens the PLL loop of the local oscillator and applies an offset control voltage to the voltage controlled oscillator when switching reception channels, thereby quickly switching the output frequency of the voltage controlled oscillator. The present invention relates to a method for setting the offset control voltage and a wireless communication device using the method.

[0002] Wireless devices such as car phones and mobile phones are generally configured to switch to a designated channel to make a call, and for this reason, a frequency synthesizer is used as a local oscillator to facilitate channel switching. This frequency synthesizer uses the output frequency of a voltage-controlled oscillator, and is required to compensate for variations in characteristics of the voltage-controlled oscillator due to temperature, etc., and to constantly switch the output frequency at high speed and with high precision. .

0003

12 is a circuit diagram of a conventional frequency synthesizer, in which 1 is a reference oscillator, 2 is a variable frequency divider, 3 is a phase comparator, 4 is a loop filter, and 5 is a voltage controlled oscillator (VC
0), 6 is a 2-modulus prescaler, 7 is a program counter, 8 is a swallow counter, 9 is a pulse swallow type variable frequency divider consisting of the above-mentioned 6 to 8, and 10 is an output frequency switching control section.

In the figure, the output of a reference oscillator 1 is frequency-divided by a variable frequency divider 2 and applied to a phase comparator 3.
The output of O5 is frequency-divided by variable frequency divider 9 and applied to phase comparator 3. Then, the phase comparator 3 outputs a voltage signal according to the phase difference between these two input signals, and this voltage signal has its high frequency components removed by a loop filter 4 and is sent to the VC.
This is fed back to O5, and VCO5 outputs a signal fo at a frequency such that the phase difference between the two input signals becomes zero.

At this time, in the variable frequency divider 9, the prescaler 6 initially operates in the 1/(P+1) mode,
When the swallow counter 8 counts the output of the prescaler 6 by A, it outputs a division switching signal to the prescaler 6, and as a result, the prescaler 6 remains in the 1/P mode until the program counter 7 counts the remaining (N-A). Operate. Therefore, the total frequency division number D of the variable frequency divider 9 is {
A(P+1)+(N-A)P}, that is, D=(NP+A)
Here, by selecting N arbitrarily and A between 0 and (P-1), an arbitrary integer frequency division number D can be obtained.

[0006] Thus, the switching control section 10 has the variable frequency divider 2
By setting desired numbers for and 9, an oscillation signal fo of a desired frequency can be obtained from the VCO 5. by the way,
The sensitivity of phase comparator 3 is KD, and the sensitivity of VCO5 is KV.
Then, the loop gain KL of the PLL loop is
It is expressed as KL=(KD·KV)/D, and there is a relationship in which the larger the frequency division number D is, the smaller the loop gain KL is.

Nowadays, the frequency band used in mobile radio systems such as car telephones is becoming higher, so the frequency division number D becomes larger, the loop gain KL becomes smaller, and the phase pull-in required for frequency switching is increased. Time is getting longer.

[0008] Conventionally, therefore, when setting a predetermined frequency,
A method has been proposed in which the variable frequency dividers 2 and 9 are set so that the frequency division number D changes stepwise, thereby speeding up the switching of the output frequency.

FIG. 13 is an explanatory diagram of the operation of conventional multi-stage switching.
This shows the case of switching to 8125MHZ. Now, assuming that the oscillation frequency of the reference oscillator 1 is 8 MHZ, the switching control unit 10 sets sets of numbers M, N, and A in six stages as shown in Table 1 in the frequency dividers 2, 7, and 8, respectively. By VCO5
The frequency to be output changes as shown in FIG.

Note that the prescaler 6 is fixed at P=128, and in Table 1, Fr is the output frequency of the frequency divider 2,
Fout is the frequency that the VCO 5 should output. In the first stage, the switching control unit 10 controls Fr=100KH.
Z, Fout=800.1MHZ, and since the frequency division number D is as small as 8001, Fout=800.1MHZ.
ut approaches 800.1 MHZ relatively quickly. In the second stage, Fr=64KHZ, Fout=80
0.064 MHZ, which makes the frequency division number D somewhat large to 12501, but since the actual output frequency fo of the VCO 5 is already approaching 800.1 MHZ, this causes the phase comparator 3 to The beat frequency of the output is decreasing, and as a result, the drawing force due to the DC component of the loop filter 4 is increasing, so the actual output frequency fo of the VCO 5 continues to be 800.06.
Fast approaching 4MHZ. Below, in the same way, the 6th
The control advances to step 800.08125 in step 6.
Phase pull-in is performed on MHZ and PLL lock is achieved.

However, since the frequency synthesizer shown in FIG. 12 has a time lag due to the loop filter 4, the VCO
The actual output frequency fo of No. 5 will change like the dotted line curve in FIG. 13, and the request for faster switching to the designated channel cannot be met. Therefore, conventionally, a configuration has been proposed in which a predetermined offset control voltage is applied to the loop filter 4 in the first stage when switching the output frequency as described above.

FIG. 14 is a circuit diagram of another example of a conventional frequency synthesizer, in which the same reference numerals as in FIG. 12 indicate the same or corresponding parts, 11 and 12 are first switches, 13 is a second switch, 14 is offset control voltage data DA
D/A converter (D/A) that converts 1 to D/A, 15 is D
An amplifier 16 amplifies the output of the /A converter 14, and a switching control section.

FIG. 15 is an explanatory diagram of the operation of the frequency synthesizer shown in FIG. 14, in which (a) is the frequency division data output from the switching control section 16, (b) is the setting signal of the frequency division data, and (c) is the offset control. Voltage data, (d) is the first switch 11
, 12, (e) is the control signal of the second switch 13, (f) is the output analog voltage of the D/A converter 14,
(g) shows the transition of the control voltage applied to the VCO 5, respectively.

In the first stage of switching the output frequency, the switching control section 16 applies the frequency division data D1 to the frequency dividers 2 and 9 in the same manner as described with reference to FIG.
) and sets the frequency divided data D1 in the frequency dividers 2 and 9. At that time, the offset control voltage data DA1 is added to the D/A converter 14, so that the D/A converter 14
The analog output voltage of is shown in (f). Furthermore, at that time, the first switches 11 and 12 are turned off at the timing shown in (d), and the second switch 13 is turned on at the timing shown in (e), thereby opening the PLL loop, and The offset control voltage from the amplifier 15 is applied to the capacitor C of the loop filter 4 to force the voltage of the capacitor C to rapidly charge up to a voltage corresponding to a predetermined output frequency (for example, 800.075 MHZ) of the VCO 5. do. Then, after a predetermined time has elapsed for each, the second switch 13 is turned OFF and the first switches 11 and 12 are turned ON, and at the same time, the internals of the frequency dividers 2 and 6 are initialized, and the input of the phase comparator 3 is By controlling so that the phases of The output frequency fo immediately becomes the target frequency 800.08125M
Lock to HZ. Therefore, according to the frequency synthesizer of FIG. 14, only three stages are required, and the time required for switching the output frequency is significantly shortened.

By the way, since the reactance element that determines the oscillation frequency of the VCO 5 changes its characteristics depending on the temperature,
The output frequency fo when the PLL of the VCO 5 is released changes depending on temperature changes. However, since the actual output frequency fo of the VCO 5 is PLL-locked to the output frequency of the reference oscillator 1, as long as the reference oscillator 1 is stable, the actual output frequency fo of the VCO 5 is also stable. Therefore, because of the PLL, it is the control voltage of the VCO 5 that actually changes due to temperature changes.

However, in the frequency synthesizer shown in FIG. 14, the offset control voltage for causing the VCO 5 with the PLL open to output a predetermined output frequency (for example, 800.075 MHZ) is constant regardless of the temperature.
When there is actually a temperature change, etc., highly accurate pull-in in the first stage when switching channels as described above cannot be performed. Therefore, conventionally, the following frequency synthesizer has been proposed to solve this problem.

FIG. 16 is a circuit diagram of another conventional frequency synthesizer, in which the same symbols as in FIG. 14 indicate the same or corresponding parts, 17 is a switch circuit, SW1 and SW2 are switches, and 18 is an analog control voltage of A/D converter 19 is a switching control section.

In the figure, when switching channels, the switching control section 19 turns off the switch SW1 and turns off the switch SW1.
2 is turned on, offset control voltage data DA1 is added to the D/A converter 14, and the output frequency of the VCO 5 is controlled to switch quickly. However, once the PLL is locked, this control voltage is temperature compensated. Therefore, by reading the control voltage of the VCO 5 through the A/D converter 18, the offset control voltage data DA1 used at the next channel switching can be made accurate. Therefore, according to the frequency synthesizer of FIG. 16, even if the characteristics of the VCO 5 vary due to temperature or the like, the offset control voltage data DA1 is appropriately compensated for, so the approximate setting of the output frequency of the VCO 5 using the offset control voltage is as follows. Can always be performed with high precision.

However, even in the frequency synthesizer shown in FIG. 16, if the characteristics of the reference oscillator 1 vary due to temperature, etc., even if the PLL is locked, the output frequency itself will not be accurate, so the offset control voltage at that point will be Even if data DA1 is read, it cannot be used as is.

Furthermore, when such a frequency synthesizer is incorporated into a wireless communication device, the offset control voltage data should be updated in consideration of the temperature characteristics not only of the reference oscillator 1 but also of the entire wireless communication device.

[0021]

[Problems to be Solved by the Invention] As mentioned above, in the conventional frequency synthesizer, information for updating offset control voltage data is obtained only from the control voltage of the VCO 5. Accurate compensation of offset control voltage data could not be performed when considering the entire wireless communication device incorporating the .

An object of the present invention is to provide an offset control voltage setting method that can accurately compensate offset control voltage data when considering the entire frequency synthesizer or the entire wireless communication device incorporating this frequency synthesizer, and the method. An object of the present invention is to provide a wireless communication device according to the present invention.

[0023]

[Means for Solving the Problems] The above problems are solved by the configuration shown in FIG. That is, the wireless communication device of the present invention includes a high frequency reception amplification section 100, a local oscillation section 200 having a voltage controlled oscillator controlled by a PLL loop, and an output of the high frequency reception amplification section 100 and an output of the local oscillation section 200. a mixer section 300 that performs frequency heterodyning, an intermediate frequency amplification section 400 that amplifies the output of the mixer section 300, and a switching control that opens the PLL loop and applies an offset control voltage DA to the voltage controlled oscillator when switching reception channels. 500, the switching control section 500 is energized to apply a predetermined offset control voltage DA to the voltage controlled oscillator during a standby time other than transmission or a frame signal destined for the own station, A setting control section 600 is provided that changes the predetermined offset control voltage DA until the output of the frequency amplification section 400 is detected, and fixes the offset control voltage when the output is detected.

[0024]

[Operation] In the wireless communication device of the present invention, the setting control unit 600 activates the switching control unit 500 to open the PLL loop and switch the voltage controlled oscillator to A predetermined offset control voltage DA is applied, and the voltage controlled oscillator outputs a local oscillator signal fo having a frequency corresponding to the applied offset control voltage DA. This local oscillator signal fo is subjected to frequency heterodyning with the high frequency signal fr from the high frequency receiving and amplifying section 100 in the mixer section 300, and the intermediate frequency amplification is inputted to the section 400. Since this intermediate frequency amplifying section 400 amplifies only the intermediate frequency signal fi with a constant bandwidth, if the frequency of the local oscillator signal fo driven by the offset control voltage DA at this point is lower than the specified value, When it is shifted, the setting control section 600 cannot detect the output signal fi from the intermediate frequency amplification section 400, and therefore the setting control section 600 cannot detect the output signal fi from the intermediate frequency amplification section 400. The predetermined offset control voltage DA is changed until the output signal fi is detected, and the offset control voltage at that time is fixed.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 2 is a circuit diagram of the wireless communication device of the first embodiment, and the figure shows a part of the double superheterodyne receiving circuit, in which 21 is an antenna, 22 is a high frequency amplification circuit, 23 is a first mixer, 24 is a first intermediate frequency filter, 25 is a first intermediate frequency amplifier circuit, 26 is a second mixer, 27 is a second intermediate frequency filter, 28 is a second intermediate frequency amplifier circuit, 29 is a first local oscillator circuit, and 30 is a In the second local oscillator circuit, 31 is a frequency counter circuit, and 32 is a control circuit.

Regarding the relationship with FIG. 1, the high frequency amplifier circuit 2
2 is a high frequency reception amplification section 100, a first local oscillation circuit 29 is a local oscillation section 200, a first mixer 23 is a mixer section 300, a first
The intermediate frequency is a block conceptualization of the intermediate frequency filter 24, the first intermediate frequency amplification circuit 25, the second local oscillator circuit 30, the second mixer 26, the second intermediate frequency filter 27, and the second intermediate frequency amplification circuit 28. Amplification section 400, control circuit 3
2, which performs controls such as opening the PLL loop and adding an offset control voltage DA to the voltage controlled oscillator when switching the reception channel, is the switching control section 500, and the frequency counter circuit 31 and the control circuit 32. During the standby time for transmission or frame signals destined for the own station, the switching control unit 500 is activated to apply a predetermined offset control voltage DA to the voltage controlled oscillator, and the output of the intermediate frequency amplification unit 400 is detected. offset control voltage D until
The setting control unit 600 is a part that performs control to change A and fix the offset control voltage when detected.

In FIG. 2, a high frequency signal input from an antenna 21 is passed through a control circuit 3 in a high frequency amplification circuit 22.
The high frequency signal fr from the current communication partner is selectively amplified by the tuning selection signal DA3 sent from 2 and input to the first mixer 23, while the first local oscillator circuit 29 converts the high frequency signal fr to a predetermined first intermediate frequency. It outputs a first local oscillation signal fo1 for frequency conversion into a signal, and these two signals fr and fo1 are frequency heterodyned in a first mixer 23 and input to a first intermediate frequency filter 24, and the first local oscillation signal fo1 is outputted. Only the first intermediate frequency signal fi1 (for example, fr-fo1) is extracted from the first intermediate frequency filter 24,
It is amplified by the first intermediate frequency amplification circuit 25. Furthermore, this first intermediate frequency signal fi1 is input to the second signal generator 26, while the second local oscillator circuit 30 is connected to a second local oscillator circuit for converting the frequency of the first intermediate frequency signal fi1 into a predetermined second intermediate frequency signal. It outputs the oscillation signal fo2, and these two signals fi1
, fo2 are frequency-heterodyned in the second mixer 26 and input to the second intermediate frequency filter 27, from which only the second intermediate frequency signal fi2 (for example, fi1-fo2) is taken out. The intermediate frequency amplification circuit 28 amplifies the signal.

FIG. 3 is a circuit diagram of the first local oscillator circuit of the first embodiment, in which the same reference numerals as in FIG. 14 indicate the same or corresponding parts, and 20
is a D/A converter that converts the reference oscillator correction data DA2 into a D/A converter and applies the D/A converter to the reference oscillator 1.

FIG. 4 is a circuit diagram of the frequency counter circuit of the first embodiment, and the frequency counter circuit 31 constitutes a so-called automatic frequency control circuit (AFC circuit) as conventionally used. In the figure, 41 is an analog switch that selects and outputs any one of the input first local oscillation signal fo1, second local oscillation signal fo2, and second intermediate frequency signal fi2 according to the selection signal S3, and 42 is the selected one. A pulse shaping circuit 43 pulse-shapes the output signal; a counter 43 counts the pulse-shaped signal only during a gate signal G having a certain time width, which will be described later, and outputs a count signal CNT;
4 is a frequency-stabilized reference oscillation circuit, 45 is a frequency dividing circuit that divides the output of the reference oscillation circuit 44 by B, and 46 is triggered by an external trigger signal T, and in synchronization with this, the counter 4
This timing circuit outputs a reset signal R to the counter 43 as a gate signal G, and outputs only one pulse of the output of the frequency dividing circuit 45 generated thereafter to the counter 43.

FIG. 5 is a circuit diagram of the control circuit of the first embodiment.
The control circuit 32 has the functions of both the switching control section 16 of FIG. 14 and the setting control section 600 of FIG. 1. In the figure, 51 is a CPU that performs main control of the control circuit 32, 52 is a ROM that stores the control programs shown in FIGS. 7 to 9 executed by the CPU 51, and 53 is the current offset control voltage data as shown in FIG. RAM 54 stores DA1 and a plurality of offset control voltage data HN going back in the past, and I/54 interfaces between the CPU 51 and external circuits.
This is the O port.

FIG. 6 is a diagram explaining the storage mode of the RAM of the first embodiment, and (A) of FIG. 6 shows the storage mode of the current offset control voltage data (DA1) for each channel (CH). 6B shows a plurality of offset control voltage data HN(n-
1, n-2,,) is shown.

FIG. 7 is a flowchart of the main processing of the CPU in the first embodiment, and input is entered into this processing when the wireless communication device is powered on. In step S11, a counter register CR for counting the number of times the own frame has been received is reset, and in step S12, it is determined whether or not the transmission request is from a console (not shown).If the transmission request is a transmission request, step S1
3 to operate in transmit mode. If it is not a transmission request, step S13 is skipped. In step S14, it is determined whether or not the own station frame has been received. If the own station frame has been received, the operation is performed in the reception mode in step S15, and in step S16, since the own station frame reception has been performed once, the counter register CR is incremented by 1. Further, if it is determined in step S4 that the local station frame is not received, steps S15 and S16 are skipped. In the following step S17, it is determined whether or not the number of times the frame has been received by the own station is K times, and if it is not K times, the process proceeds to step S1.
Return to 2.

Eventually, when the determination in step S17 reaches K times, this is the time to update the offset control voltage data of the VCO 5. That is, as shown in the transmission/reception frame configuration in FIG. 10, this update time is a period in which the transmission frame is not in the transmission mode, and the reception frame for the own station is not in the reception mode t1 or reception mode t2. Reception mode t1 and reception mode t2
This is the period t3 sandwiched between. During this period, since there is a received carrier signal from the transmission partner, the following data correction process can be performed using this received carrier signal. That is, the control proceeds to step S18, where the reference oscillator correction data DA2 to be added to the reference oscillator 1 of the first local oscillator circuit 29 is updated, and then the control proceeds to step S18.
At step 19, the offset control voltage data DA1 for the VCO 5 of the first local oscillator circuit 29 is updated.

[0034] Thus, since the above data update process is performed once every K times the frame is received by the local station, during the interval, for example, the power of the circuit related to this data update process may be turned off. By doing so, you can save power. Note that the number of K times is determined by taking into consideration the speed of temperature change, etc.

FIG. 8 is a flowchart of the reference oscillator correction data updating process, which is executed in step S18 of FIG. In step S21, the selection signal S3 is applied to the analog switch 41 to select the second local oscillator signal fo2, and in step S22, the trigger signal T is applied to the timing circuit 46. As a result, the timing circuit 46 outputs a reset signal R to reset the counter 43, and also outputs a gate signal G having a constant time width, thereby causing the counter 4
3 counts the second local oscillator signal fo2 during the period of the gate signal G. When the gate signal G times out, the count value CNT of the counter 43 is loaded into the temporary register TR1 in step S23, and the frequency that the second local oscillator circuit 30 should originally output is determined in step S24 from the contents of the temporary register TR1. The corresponding reference count value REFo2 is subtracted, and the result is set in the temporary register TR1. As a result, the temporary register TR1 stores a count value corresponding to the current error in the oscillation frequency of the second local oscillator circuit 30, and this error count value can be a positive value or a negative value in response to temperature changes. It can also be a value.

Next, in step S25, the selection signal S3 is applied to the analog switch 41 to select the first local oscillation signal fo1, and in step S26, the trigger signal T is applied to the timing circuit 46. As a result, the timing circuit 46 outputs the reset signal R to reset the counter 43, and continues to output the gate signal G with a constant time width, and the counter 43 outputs the first local oscillation signal fo during the period of the gate signal G.
Count 1. When the gate signal G times out, the count value CNT of the counter 43 is loaded into the temporary register TR2 in step S27, and the count value CNT of the counter 43 is loaded into the temporary register TR2 in step S28.
From the contents of , the error count value of the second local oscillator circuit 30 stored in the temporary register TR1 is set to the reference count value REFfo1 corresponding to the frequency that the first local oscillator circuit 29 should output in the current PLL lock state. Subtract the added value and store the result in the temporary register T.
Set to R2. As a result, the temporary register TR2 stores the current count value of the sum of the error count value of the first local oscillator circuit 29 and the error count value of the second local oscillator circuit 30. In step S29, it is determined whether the contents of the temporary register TR2 are zero or not.
If it is not zero, in step S30, the temporary register T is
Correction data DA2 for the reference oscillator, which is obtained in a certain relationship from the contents of R2, is formed and output to the D/A converter 20. Then, the control returns to step S26, and the process continues in step S26 until the contents of the temporary register TR2 become zero.
The loop from ~S30 is repeated, and when the value reaches zero, the process exits.

Note that since the temperature characteristics of the oscillation reactance components of the first local oscillator circuit 29 and the second local oscillator circuit 30 can be known in advance, the above-mentioned A certain relationship can be defined.

By the way, the error frequency generated by the second local oscillator circuit 30 becomes the error frequency of the second intermediate frequency signal fi2 as it is, but in the double superheterodyne system, the error frequency of the first intermediate frequency signal fi2 is higher than the frequency of the second intermediate frequency signal fi2. fi
Since the frequency of No. 1 is overwhelmingly higher, the error frequency caused by the second local oscillator circuit 30 is relatively small. Therefore, in this embodiment, the error frequency of the second local oscillator circuit 30 is added to the oscillation frequency of the first local oscillator circuit 29 to absorb the error, and thereby the error frequency of the second intermediate frequency signal fi2 is is always set to zero. In this way, the entire receiving circuit of the wireless communication device has been calibrated through the process shown in FIG. 8, and an environment has been prepared for updating the current offset control voltage data DA1.

FIG. 9 is a flowchart of the offset control voltage data updating process, which is executed in step S19 of FIG. In step S41, the selection signal S3 is applied to the analog switch 41 to select the second intermediate frequency signal fi2, and in step S42, the first switches 11 and 12 are turned OFF and the second switch 13 is turned ON. That is, the PLL loop is turned off and the current offset control voltage data DA1 is applied to the VCO5. In step S43, the current offset control voltage data DA1 is output to the D/A converter 20, and in step S44, a trigger signal T is applied to the timing circuit 46. As a result, the timing circuit 46 outputs a reset signal R to reset the counter 43, and also outputs a gate signal G having a constant time width, whereby the counter 43 outputs a second intermediate frequency signal during the period of the gate signal G. Count fi2. When this gate signal G times out, step S
In step S45, the count value CNT of the counter 43 is taken into the temporary register TR1, and in step S46, it is determined whether the contents of the temporary register TR1 are greater than or equal to a predetermined number Q. If the current offset control voltage data D
If A1 can be used as is, that is, if there is no temperature change from the previous update time, the offset control voltage data DA
1, the frequency of the first local oscillation signal fo1 should be approximately accurate, so eventually the second intermediate frequency signal fi2 should be received, and this causes the temporary register TR1
should indicate a predetermined number Q or more. However, if the contents of the temporary register TR1 are not equal to or greater than the predetermined number Q, it can be determined that the current offset control voltage data DA1 is not accurate, so the control proceeds to step S47, and the current offset control voltage data DA1 is changed in the following manner. do.

That is, as a method of changing this, for example, when the contents of the temporary register TR1 are approximately zero, for example, the value of the current offset control voltage data DA1 is changed to H0.
Then, the next value H1 is H1 = H0 + 1U (
However, U is a predetermined number (for example, 3), the next value H2 is H2 = H1 - 2U, and the next value H3 is H3 =
H2 + 3U, that is, the value of the offset control voltage data DA1 is changed in such a way that the value of the offset control voltage data DA1 fluctuates from the current value H0, and the amplitude of the fluctuation increases. Then, when the contents of temporary register TR1 start to increase,
In the same direction as the previous time, and by changing the value Hi in small increments, the temporary register TR1
This is to guide the user so that the content of the information becomes equal to or greater than a predetermined number Q.

As another method of change, since the tendency of temperature change can be grasped in advance by the updating process shown in FIG. 8, the value Hi can be changed by taking this tendency of temperature change into consideration. For example, the sensitivity of the circuit of the DA converter 14 is 150kHz.
/ code, and the output frequency of VCO5 is 800M
For example, if it is obtained by the processing in Figure 8 that the HZ has changed by about +5 MHZ due to characteristic fluctuations, then 5 MHZ /
150kHz ≒ 33 codes, which results in D/
This means that the offset control voltage data applied to the A converter 14 only needs to be lowered by 33 codes than the current value.

Still another method of changing is to change the value Hi based on the transition of a plurality of past offset control voltage data.
An example is shown in Table 2. According to Table 2, the trend of multiple offset control voltage data going back five times in the past is a decrease of 3 codes, so the prediction of the current offset control voltage data is (116 codes) - (3 codes) = ( 113 code).

In this way, if the contents of the temporary register TR1 exceed the predetermined number Q as determined in step S46,
In step S48, the first switches 11 and 12 are turned ON and the second switch 13 is turned OFF, that is, the PLL loop is returned to. In step S49, the table of past offset control voltage data shown in FIG. 6(B) is stored in FIFO mode. The process is updated and the process returns to step S11 in FIG. Thus, the offset control voltage data D is always accurate regardless of temperature changes.
A1 will be obtained.

By the way, the frequency counter circuit 31 of the first embodiment is a conventional so-called automatic frequency control circuit (AFC circuit).
Since the AFC circuit is an existing circuit included in a conventional wireless communication device, the first embodiment of the present invention does not require any special expensive configuration. This means that it is possible to provide a wireless communication device that can update offset control voltage data at low cost without any trouble.

FIG. 11 is a circuit diagram of a wireless communication device according to the second embodiment, in which the same reference numerals as in FIG. 2 indicate the same or corresponding parts, and 61
62 is a received carrier extraction circuit that extracts a received carrier signal of a constant frequency from the second intermediate frequency signal fi2. 63 is a received carrier extraction circuit that compares the output amplitude of the received carrier extraction circuit 62 with a predetermined threshold value. A received carrier detection circuit 64 detects the presence or absence of a signal, and is a control circuit.

Regarding the relationship with FIG. 1, the high frequency amplifier circuit 2
2 is a high frequency reception amplification section 100, the first local oscillation circuit 61 is a local oscillation section 200, the first mixer 23 is a mixer section 300, the first
The intermediate frequency is a block conceptualization of the intermediate frequency filter 24, the first intermediate frequency amplification circuit 25, the second local oscillator circuit 30, the second mixer 26, the second intermediate frequency filter 27, and the second intermediate frequency amplification circuit 28. Amplification section 400, control circuit 6
4, which performs controls such as opening the PLL loop and adding an offset control voltage DA to the voltage controlled oscillator when switching the reception channel, is the switching control unit 500, and the reception carrier extraction circuit 62 and the reception carrier. Detection circuit 6
3 and a part of the control circuit 64, which activates the switching control section 500 to apply a predetermined offset control voltage DA to the voltage controlled oscillator during the standby time for transmission or frame signals destined for the own station, and at the same time, the intermediate frequency amplification section The setting control unit 600 is a part that performs control to change the offset control voltage DA until the output of 400 is detected, and to fix the offset control voltage when it is detected.

Note that the received carrier detection circuit 63 may be configured to detect the first intermediate frequency signal fi1 instead of the second intermediate frequency signal fi2, and this wireless communication device also includes a second intermediate frequency amplification section. It may also be a single heterodyne type without.

As described above, although the wireless communication device of the second embodiment does not include the frequency counter circuit 31 of FIG. 2, that is, the AFC circuit, it is clear that the present invention can be applied to such a wireless communication device. That is, the control circuit 64 controls the first
The PLL loop of the local oscillator circuit 61 is opened and a predetermined offset control voltage DA1 is applied to its voltage controlled oscillator, and the predetermined offset control voltage DA1 is applied until the received carrier signal from the intermediate frequency amplification section is detected. can be changed and the offset control voltage when detected can be fixed.

[0049] Even in the case of a conventional ordinary wireless communication device that does not have the setting control section 600 according to the present invention, an appropriate external transmitter is prepared at the time of manufacture, and a predetermined carrier signal is transmitted by the transmitter. At the time of reception, a person operates from the outside to first energize the switching control section 500 and switch the first local oscillator circuit 6.
Open the PLL loop of No. 1, apply a predetermined offset control voltage DA to its voltage controlled oscillator, and change the predetermined offset control voltage DA until a received carrier signal from the intermediate frequency amplification section is detected. , and it is possible to fix the offset control voltage DA when detected.

Therefore, according to the method of setting the offset control voltage applied to the voltage controlled oscillator of the present invention, even when manufacturing a conventional ordinary wireless communication device, it is possible to set the offset control voltage using the wireless communication device itself. Self-configuration is possible, which makes it possible to easily and quickly adjust the shipping of this type of wireless communication device.

[0051]

As described above, according to the present invention, when a predetermined carrier signal is received, the switching control section 500 is activated to apply a predetermined offset control voltage DA to the voltage controlled oscillator, and the intermediate frequency amplification section 400 is activated. The predetermined offset control voltage DA is changed until the output of This has the advantage that the offset control voltage can be easily set by oneself using the device itself.

Further, according to the present invention, the switching control section 500 is energized to apply a predetermined offset control voltage D to the voltage controlled oscillator during the standby time for a frame signal other than the transmission or own frame signal.
A, the setting control section 600 is provided which changes the predetermined offset control voltage DA until the output of the intermediate frequency amplification section 400 is detected, and fixes the offset control voltage when the output is detected. This has the effect of automatically correcting the offset control voltage taking into consideration the entire wireless communication device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention.

FIG. 2 is a circuit diagram of a wireless communication device according to a first embodiment.

FIG. 3 is a circuit diagram of the first local oscillator circuit of the first embodiment.

FIG. 4 is a circuit diagram of the frequency counter circuit of the first embodiment.

FIG. 5 is a circuit diagram of a control circuit of the first embodiment.

FIG. 6 is a diagram illustrating a storage mode of a RAM in the first embodiment.

FIG. 7 is a flowchart of main processing of the CPU in the first embodiment.

FIG. 8 is a flowchart of reference oscillator correction data update processing.

FIG. 9 is a flowchart of offset control voltage data update processing.

FIG. 10 is a diagram illustrating the structure of a transmission/reception frame.

FIG. 11 is a circuit diagram of a wireless communication device according to a second embodiment.

FIG. 12 is a circuit diagram of a conventional frequency synthesizer.

FIG. 13 is an explanatory diagram of conventional multi-stage switching operation.

FIG. 14 is a circuit diagram of another conventional frequency synthesizer.

FIG. 15 is an explanatory diagram of the operation of the frequency synthesizer of FIG. 14;

FIG. 16 is a circuit diagram of another conventional frequency synthesizer.

[Explanation of symbols]

100 High frequency reception amplification section 200 Local oscillation section 300 Mixer section 400 Intermediate frequency amplification section 500 Switching control section 600 Setting control section

Claims (3)

[Claims] Claim 1: A high frequency reception amplification section (100) and a PL
a local oscillation section (200) having a voltage controlled oscillator controlled by an L loop; a mixer section (300) for frequency heterodyning the output of the high frequency reception amplification section (100) and the output of the local oscillation section (200); an intermediate frequency amplifying section (400) that amplifies the output of the mixer section (300); and a switching control section (500) that opens the PLL loop and applies an offset control voltage (DA) to the voltage controlled oscillator when switching the receiving channel. ) In the method for setting the offset control voltage of a wireless communication device, the switching control unit (500) is activated to apply a predetermined offset control voltage (DA) to the voltage controlled oscillator when a predetermined carrier signal is received. In addition, the predetermined offset control voltage (DA) is changed until the output of the intermediate frequency amplification section (400) is detected, and the offset control voltage (D
A) A method for setting an offset control voltage characterized by fixing the voltage. Claim 2: A high frequency reception amplification section (100) and a PL
a local oscillation section (200) having a voltage controlled oscillator controlled by an L loop; a mixer section (300) for frequency heterodyning the output of the high frequency reception amplification section (100) and the output of the local oscillation section (200); an intermediate frequency amplifying section (400) that amplifies the output of the mixer section (300); and a switching control section (500) that opens the PLL loop and applies an offset control voltage (DA) to the voltage controlled oscillator when switching the receiving channel. ), in which the switching control unit (500) is energized to apply a predetermined offset control voltage (DA) to the voltage controlled oscillator during a standby time other than transmission or a frame signal destined for the own station; , comprising a setting control unit (600) that changes the predetermined offset control voltage (DA) until the output of the intermediate frequency amplification unit (400) is detected, and fixes the offset control voltage when the output is detected. A wireless communication device characterized by: 3. The setting control unit includes a memory storing a plurality of offset control voltage data going back in the past;
600) is characterized in that when the output of the intermediate frequency amplification section (400) is not detected, the offset control voltage (DA) is changed based on the transition of the plurality of offset control voltage data. Device.