JPH04251962A - Method for designing semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a prediction of a final chip shape in a short time by enabling a block to be corrected in a conversation style before and after a cell placement in a building block system using a standard cell system or a gate array system. CONSTITUTION:First, a rough placement position of a block achieving each function owned by a semiconductor chip and a cell to be placed within the block is determined by an initial floor plan. An area and a shape of the block are predicted based on this initial floor plan and displayed and a shape or a placement position of the displayed block are corrected in a conversation style. Further, a cell is placed within the predicted or corrected block and the shape or the placement position of the displayed block are corrected in a conversation style. Then, after correcting all blocks, the blocks are integrated and an entire chip is wired. thus enabling a desired chip shape to be predicted in a short time and a difference between a result of floor plan and a desired chip shape to be reduced.

Description

[Detailed description of the invention]

[Object of the invention]

0002

[Field of Industrial Application] The present invention relates to a method for designing a building block type semiconductor integrated circuit device using a standard cell type or a gate array type. This invention relates to a design method in which the shape or placement position can be modified.

0003

2. Description of the Related Art In a conventional method for designing a semiconductor integrated circuit device, processing proceeds linearly from floor planning, block arrangement, and interconnection between blocks. When a correction is made to the arrangement position of a block, etc., the process returns to the beginning and the same process is performed. Furthermore, during the floor planning process, which determines which area on a chip (semiconductor integrated circuit device) to allocate the functions to be implemented, it was not possible to predict the final shape of the block, taking into account cell placement and inter-cell wiring. For this reason, even if some blocks have too many cells allocated to them and others lack cells in the floor plan, it is not possible to predict the chip shape before the final wiring is completed. This allows the process to run to the end, and then
I had to go back to the beginning and change the floor plan and start over.

0004

[Problem to be Solved by the Invention] As described above, in the conventional design method for semiconductor integrated circuit devices, when a modification occurs, the process is executed to the end, and then the process is returned to the beginning and the floor plan is changed and the process is restarted. Ta. Therefore, there is a problem in that it takes time to obtain a final prediction of the chip shape.

The present invention has been made in view of the above-mentioned conventional circumstances, and its purpose is to improve the final chip by allowing blocks to be modified interactively before and after cell placement. It is an object of the present invention to provide a method for designing a semiconductor integrated circuit device that allows prediction of the shape to be obtained in a short time.

[Configuration of the invention]

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a method for designing a semiconductor integrated circuit device using a building block method using a standard cell method or a gate array method. The approximate placement position of the block that realizes each function of the block and the cells to be placed in this block are determined in an initial floor plan, and the area and shape of the block are predicted and displayed based on this initial floor plan. The shape or placement position of the created block can be modified interactively,
Furthermore, cells are arranged and displayed within the predicted or corrected blocks, and the shape or arrangement position of the displayed block can be modified interactively after cell arrangement is completed.

[0008]

[Operation] This invention divides the floor plan into two phases. In the first floor plan, it is determined in which areas on the chip all functions will be implemented, either fully automatically or partially manually. At the same time, the approximate placement positions of blocks that implement each function and the cells to be placed within each block are determined. Based on the determined information, the area and shape of the block required for arranging the cell are predicted and displayed. When modifying the shape or placement position of a block, do so interactively while looking at the displayed floor plan screen.

In the second floor plan, cells are arranged and displayed in the blocks predicted in the first floor plan. Depending on the excess or deficiency of placed cells, the shape or placement position of the block is modified interactively while looking at the floor plan screen.

0010

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. First Embodiment FIG. 1 shows a processing flow of a first embodiment of the method for designing a semiconductor integrated circuit device according to the present invention. In the figure, steps 11 to 16 are the first floor plan, and step 17 and the repetition from step 11 are the second floor plan. With the first floor plan,
The area and shape of the block are predicted and displayed, and further corrections are made. Based on the second floor plan, cells are placed in predicted and displayed blocks, and the shape or placement position of the blocks is further corrected depending on the placement state of the cells.

First, a block is created on the chip automatically or by the user (step 11). Next, the user designates where in the block the functions to be implemented are to be laid out. That is, a first interactive floor plan is performed (step 12). It is also possible to automatically specify where to layout everything. Thereafter, it automatically determines which block should implement the function that has not been specified by the user, and which cells should be placed in this block. A so-called first automatic floor plan determination is performed (step 13). This completes the initial floor plan.

Based on the results of this initial floor plan, the area and shape of each block are predicted (step 14). Then, the floor plan is displayed with the predicted center of gravity of the block superimposed on the center of gravity of the block on the floor plan previously defined by the user (step 15). At this stage, if the designer determines that it is unlikely that the desired result will be obtained by modifying the blocks in step 16 alone, and that it is necessary to change the number of blocks or the blocks to be realized, return to step 11 or step 12. , do the first interactive floor plan. If you judge that the desired result can be obtained by modifying the shape or placement position of the displayed block, make the modification interactively (Step 1)
6). If the desired result is not obtained even after the modification in step 16, the process returns to step 11 or step 12. This completes the first floor plan.

If the desired result is obtained, cell placement within each block is performed (step 17). Load the block whose cells have been placed into the floor plan and display it. If there is an excess or deficiency of cells in this display and the block needs to be corrected, the process returns to steps 11, 12 or step 16 and corrections are made interactively. This allows a second floor plan to be performed. After arranging cells within the block in step 17, all blocks are integrated and wiring for the entire chip is performed (step 18 and step 1).
9).

Second Embodiment FIG. 2 shows the processing flow of a second embodiment of the present invention. In the second embodiment, after the cell placement within the block in the first embodiment, intra-block wiring is performed, so-called split placement and split wiring. In FIG. 2, steps 11 to 16, which constitute the first floor plan, are the same processing as in the first embodiment.

After the block modification in step 16, cell placement and inter-cell wiring within some blocks are performed (steps 21 and 22). Load this result into the floor plan, and if there is a problem with the block configuration, step 1
Returning to step 6, the shape or arrangement position of this block or other blocks is corrected. If you have made any corrections,
Start over from the cell placement in the corrected block. Therefore, the processing performed in steps 21 and 22 is more effective if priority is given to blocks that have a particularly large influence on the overall block configuration. A second floor plan can be performed by repeating steps 16 to 22. After cell placement and inter-cell wiring in all blocks are completed, all blocks are integrated and inter-block wiring is performed (steps 23 and 24).

Third Embodiment FIG. 3 shows the processing flow of a third embodiment of the present invention. In the figure, steps 11 to 15, which constitute the first floor plan, are the same processes as in the first and second embodiments. In the third embodiment, step 31 is provided in place of step 16 in the first and second embodiments. That is, in addition to modifying the shape and arrangement position of the blocks as in the first and second embodiments, it is also possible to modify the functions to be realized within the blocks. When the functions to be realized change, the final area and shape of the chip also change. In the third embodiment, the area and shape of the block when the new function is realized is predicted and displayed (step 31). This eliminates the need to return to the first floor plan. Only the second floorplan is modified until the desired floorplan is obtained, and after the desired floorplan is obtained, the process proceeds from cell placement within the block to wiring for the entire chip (steps 17 to 19).

[0017]

As described above, according to the method for designing a semiconductor integrated circuit device of the present invention, it is possible to interactively modify the shape or arrangement position of a block before and after arranging cells within the block. This makes it possible to predict the desired chip shape in a short time and to reduce the difference between the final result of the floor plan and the desired chip shape.

[Brief explanation of the drawing]

FIG. 1 is a processing flow of a first embodiment of this invention.

FIG. 2 is a processing flow of a second embodiment of the present invention.

FIG. 3 is a processing flow of a third embodiment of the present invention.

Claims (1)

[Claims] Claim 1: When designing a semiconductor integrated circuit device using a building block method using a standard cell method or a gate array method, the approximate placement position of the blocks that realize each function of the semiconductor integrated circuit device and this Cells to be placed within a block are determined by an initial floor plan, the area and shape of the block are predicted and displayed based on this initial floor plan, and the shape or placement position of the displayed block can be modified interactively. A method for designing a semiconductor integrated circuit device characterized by the following.