JPH02168647A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable internal cells of an LSI to be arranged in an optimum pattern at a low cost by dividing all the cell arrays into at least two regions depending on a route of shuffling and positions of a pair of cell arrays for which shuffling is to be performed, and performing shuffling in consideration of relation of connection among the cell arrays in the respective regions. CONSTITUTION:When shuffling is to be performed among cell array numbers 71 73 75 in a module 70, for example, arrays irrelevant to the route of shuffling are also taken into consideration. Accordingly, when shuffling is to be performed for a pair of cell arrays 71 and 73, the cell array 71 is positioned on the lower side and the cell array 73 is positioned on the upper side. The cell arrays 72 and 74 irrelevant to the route in this case are positioned on the lower side and on the upper side, respectively. The cell 71a related closely is once taken out of the cell array 71 to the cell array 73, then transferred to the cell array 72 and arranged close to the cells 73a-73c. In this manner, the cell can be allocated in well-balanced conditions as a whole in consideration of the cost for drawing cells from all the arrays in the module.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Prior Art (Figure 20.21) Problems to be Solved by the Invention Means for Solving the Problems Examples of Actions of the Invention Embodiments (Figs. 1 to 19) Effects of the invention [Summary] Regarding a method for manufacturing a semiconductor device, it is an object of the present invention to provide a method for manufacturing a semiconductor device in which each internal cell of an LSI can be arranged in an optimal pattern at low cost. The first step is to determine a module for assembling and arranging a large number of internal cells based on the number and shape of the internal cells constituting a logic block, and the first step is to determine a module for assembling and arranging a large number of internal cells based on the number and shape of the internal cells that make up the logic block. A second step of dividing the module, a third step of allocating a plurality of cell rows in which external terminals and a predetermined number of internal cells are assembled in the cell row arrangement M Fijt area, and a third step of allocating the internal cells to the cell rows. A fourth step of optimizing, a fifth step of optimizing the arrangement of internal cells within cell columns, and changing the allocation of external terminals to internal cells to columns or setting wiring between cell columns. ,
a sixth step of determining the position of an external terminal; the fourth step is a shuffling method of exchanging cells between two adjacent cell columns; In the ring method, all columns are divided into at least two regions according to the shuffling path and the position of the column pair to be shuffled, and shuffling is performed by considering the connection relationship with the cell columns in each region. Configure.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device that improves the layout design of a semiconductor integrated circuit.

In general, in a semiconductor integrated circuit, layout design is the process of determining the approximate value of the chip size and determining the approximate internal allocation.

When designing the layout of an LSI, in order to reduce the time and effort required for design and to facilitate various verifications, rather than laying out elements (transistors and capacitors) one by one on a chip, A unit with logical functions, that is, a functional block
After completing the layout design for each block in advance, the layout design of the entire chip is usually completed while designing the placement and wiring between these functional blocks.

[Conventional technology]

Optimization of the allocation of each internal cell constituting each logical block of an LSI to columns is normally performed using a shuffling method. Here, the shuffling method is one of the methods for improving the arrangement by exchanging cells between two adjacent cell columns.

At this time, the connection relationship with cell columns other than the two columns of interest is important, and this affects the manufacturing cost.

As a conventional shuffling method of this type, for example, the 20th
．． In the case of a Rect (square) shaped module as shown in FIG. 21, this is carried out as follows. That is, the second
As shown in Figure 0, when the module l in the chip has the shape Rec and the cells 2 to 4 are lined up in the left-right direction (horizontal direction) in the figure, the order of shuffling is The process starts by shuffling cell 2, which is a column, and cell 3, which is the column above it, and then goes to the top column, and when it reaches the top column, cell 4, it returns to the bottom again. It's been a long time. This is indicated by cell column number,
Shuffling is performed in the following order: (2)-1(3) (3)-1(4) (3)←→(2). At this time, it can be easily determined that another column (for example, cell 4) other than the shuffling column pair (for example, cell 2-→3) is above or below that column pair.

On the other hand, as shown in FIG. 21, the module 5 in the chip has a so-called 8-shape.
When cells 6 to 10 are arranged within the module 5, there are two columns each touching the upper and lower sides of the module 5, and cell columns 6 to 7 and cell columns 9 and 10 are arranged. Therefore, the shuffling path from the lower row to the upper row and back again can be considered as follows when expressed by cell row numbers.

(6)−→ (8)←→(9) (6)←→ (8)←→(10) (7)−→ (8)←→(9) (7)←→ (8)←→( 10) [Problems to be solved by the invention] However, in the method of manufacturing a semiconductor device using such a conventional shuffling method, especially in the case shown in FIG. When performing this, although the vertical relationship of columns on the shuffling route is known, the connection relationship with cells in other columns unrelated to the route is not known. However, in practice, if we do not consider not only the vertical relationship but also the connection relationships of other columns other than the upper and lower columns, it may not be possible to obtain the optimal module layout pattern for the chip, and improvements in this respect are desired. It will be done.

That is, in the conventional method, simply speaking, shuffling of columns in the vertical direction is possible, but in the case shown in FIG.
In terms of cell column numbers, shuffling (6)←→(8)←→(7) is not possible, and as a result, the optimal pattern may not be possible, and the cost of LSI is reduced in terms of wiring connections, etc. Invite high.

Therefore, the present invention aims to manufacture a semiconductor device in which each internal cell of an LSI can be arranged in an optimal pattern at low cost, taking into account not only the columns on the shuffling path but also the vertical relationship with columns unrelated to the path. The purpose is to provide a method.

[Means for solving problems]

In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes a first step of determining a module for assembling and arranging a large number of internal cells based on the number, shape, etc. of internal cells constituting a logic block. , a second step of dividing the module into cell row arrangement regions in which internal cells are arranged in a line, and a third step of allocating a plurality of cell rows in which external terminals and a predetermined number of internal cells are assembled in the cell row arrangement regions. , a fourth step of optimizing the allocation of the internal cells to the cell columns, and a fifth step of optimizing the arrangement of the internal cells within the cell columns;
In addition to changing the assignment of external terminals to columns for internal cells or setting areas for wiring between cell columns,
a sixth step of determining the position of an external terminal; the fourth step is a shuffling method of exchanging cells between two adjacent cell columns; In the ring method, all columns are divided into at least two regions according to the shuffling path and the position of the column pair to be shuffled, and shuffling is performed by considering the connection relationship with the cell columns in each region. I have to.

[For production]

In the present invention, the process of optimizing the allocation of internal cells to cell columns is performed by a shuffling method, in which all columns are reduced depending on the shuffling path and the position of the column pair to be shuffled. (Both are divided into two areas, and shuffling is performed taking into account the connection relationship with the cell columns in each area.

Therefore, by taking into account the cost of attracting data from all columns within the module, it is possible to obtain an extremely well-balanced and optimal allocation overall.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 19 are diagrams showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, and in particular, an example of designing the layout of an LSI. The layout design in this embodiment is performed using, for example, a CAD system, and FIG. 1 is a flowchart showing a layout design program for one LSI chip. This program uses CAD to confirm that the design is correct at each step, and then proceeds to the next design step. In Figure 1, Pn (n=1..2...
...) indicates each step of the program.

When the program starts, first, input of various specification data and the like regarding the LSI to be designed and initial settings are performed at Pl. Inputs include, for example, the contents of the logic circuit, the shape of each cell constituting the logic block, the width and length of the module, and initial settings for these are performed.

Then, at P2, the module is divided into estimate columns. This division is performed in the following manner, particularly to reduce dead space and to equalize the wiring area by treating the entire module as a processing target. In this case, the method for estimating cell rows is new compared to the conventional method, and this is disclosed for the first time in this embodiment. Note that the new technology disclosed for the first time in this embodiment includes step P4 in addition to step P2.
There is processing of ~P. Before explaining the new process of step P2, a conventional technique will be described.

Previous EB B (Extended Build)
The module shapes that can be handled in the placement program of the ing Block method are Rec or 5h
Even in ape, it was only L-shaped at most. This is because the module shape is processed by dividing it into Rec shapes, and if the division is too fine, there may be areas where cells cannot be placed. Also,
Since each divided rect area is processed separately, the cell density may be large in some areas, while it may be small in other areas. As a result, it was a cause of unconnected wires in automatic wiring.

A concrete explanation of the above problem is as follows.

FIG. 2 is a diagram showing a module 20 with a complex 5-shape shape. For example, when trying to arrange cell rows in this module 20, first divide the module 20 into areas 21 and 20 as shown in FIG. 3. ~25 will be provided. Next, the placement of the cells 26 is estimated. For example, the cells 26 cannot be placed in areas 22.24 that are lower than the height H of the cells 26, and these areas 22.24 end up being dead spaces. In addition, in the L-shaped module 27 shown in FIG. 4, the area 28 is first divided into two Rects.
．． 29 is provided. Then cell 30 for every region 28.29
A to 30e are arranged respectively, but there is insufficient wiring area in the upper area 28 in the figure, and on the contrary, there is too much wiring area in the lower area 29. In other words, it becomes unbalanced.

In contrast, in this embodiment, the average cell height is first calculated considering the upper and lower wiring areas, and then the rect of the polygonal module is divided by this average cell height, and the cell height is Information on areas where placement is prohibited is stored in this Rec.
Overlap to t. Cell placement is performed by regarding the remaining arrangable area separated in this way as a cell column placement area. More specifically, FIG. 5 shows a module 31 having a complicated shape similar to that shown in FIG. 2 described above. When placing the cell 32 in this module 31, first
Find the average height Ha. This extracts various necessary numerical data regarding the cell 32 from, for example, a library for layout in a CAD system, and calculates the average height Ha based on this. Note that such a library is appropriately used in each step described below. Once the average height Ha of the cells 32 is determined, the modules 31 are placed in the areas 33 to 37 forming the columns as shown in FIG. 6, taking into account the wiring areas of the upper and lower columns based on this average height Ha. punctuate. Next, as shown by hunting in Fig. 6,
The portion less than the average height Ha of the cell 32 is defined as a dead space 38.39 and is used as prohibition information for the arrangement of the cell 32. In this way, the dead spaces 38 and 39 are removed, and the remaining areas 33 to 37 are regarded as areas in which the cells 32 can be placed, and the cells 32 are placed therein. According to this, the dead space is minimized compared to the conventional method, and the wiring area is sufficiently balanced, which is extremely convenient.

As another example, the L-shaped module 4 shown in FIG.
The case where a cell is placed at 0 is shown. In this case as well, the average height of the cells is first determined, and then the module 40 is connected to the cell rows 41 to 45 by taking this average height and the wiring area into consideration.
Divide the area into storage areas and place cells in each area. Therefore, the wiring areas are evenly distributed in this case as well.

Returning to the program again, P creates a submodule by composing the estimate columns in the module divided into estimate columns as described above.

For example, if it is an L-shaped module, there are two Rect
Since we can create shaped modules, we will define these as submodules. Next, in P4, internal cells and external terminals are allocated to columns. This allocation is performed as follows. In particular, the old placement results are utilized during the allocation so that convergence is quick when improving the placement and the placement is even more optimal than the old placement. In order to make the effects of this embodiment easier to understand, a conventional method will be described first.

In general, E C (Engineering Chang
When a part of the circuit is changed and rearranged due to e), conventional EBB type placement programs perform placement from the beginning regardless of the old placement results. This is because there is no flag in the input file of the placement program to determine whether the cell is placed or not. In this case, for example, even if you manually correct the placement results, the results will not be reflected in the next placement at all.

In contrast, in this embodiment, first, the input file is changed, a flag for determining whether a cell is placed is provided, and the coordinates of the already-equipped cell are read. Next, the modules are divided by cell heights that take into account the upper and lower wiring areas, and "estimated column areas" are set.

Furthermore, by looking at the overlap between this "estimated column area" and the cell column of the old arrangement result, it is determined to which column each cell will be allocated. Thereby, the columns in the old arrangement can be used as the initial arrangement in the new arrangement. The above is referred to as "partial initial arrangement".

Specifically, FIG. 8 shows an example in which three cell rows 51 to 53 are arranged in a rectangular module 50. Now, in order to cope with the case where the shape of the module 50 changes in the future, the arrangement shown in FIG. 8 is stored as the old arrangement. At this time, the arrangement coordinates of cell rows 5 to 53 are read, and as shown in FIG. 9, the module 50 is divided by cell heights that take into account the upper and lower wiring regions, and estimated row regions 54 to 56 are set.

Note that 57.58 indicates the estimate column boundary. Then the first
As shown in FIG. 0, the overlap between the estimated column areas 54 to 56 and the old placement result cell columns 51 to 53 is checked to determine which column each cell will be allocated to. The columns in the old arrangement are used as the initial arrangement in the new arrangement, and the arrangement can be improved smoothly thereafter.

That is, the module 50 having the shape shown in FIG.
When cells are arranged in the state shown in the figure, when these cells are relocated to a module 60 of a different shape as shown in FIG. 11, the state shown in FIG. 10 is stored as the old arrangement result using the method described above. This old placement result is used as the initial placement (
This is the information that it is a partial initial arrangement). therefore,
According to such information, cell columns 65 to 67 are actually arranged for each estimation area 61 to 64 of the module 60, as shown in FIG. In this case, in Figure 12,
The total cell width of cell columns 65 to -87 (horizontal length LL in the figure) exceeds the column width (horizontal length LX of estimation areas 61 to 64), or the column has no cell allocation. (estimate area 64) may occur. However, in this embodiment, such a situation is properly recognized as a partial initial placement, and in the subsequent processing (step Ps), the cell column placement is immediately improved based on this partial initial placement. Therefore, as a result, the cell arrangement can be improved efficiently.

Returning to the program again, PS optimizes the allocation of internal cells to columns. This process performs replacement or shuffling of part or all of the columns. For example, the cell arrangement shown in FIG. 12 is improved in step P.

Next, shuffling will be explained as a typical process. As already pointed out in the conventional problems section, when shuffling, an optimal cell layout pattern cannot be obtained unless not only the vertical relationship of columns but also the connection relationships of other columns other than the vertical relationship are taken into consideration.

Therefore, in this embodiment, when the cell rows 71 to 75 are arranged in an H-shaped module 70 as shown in FIG. 13, for example, these shuffling is performed as follows. In other words, when performing shuffling, all rows are divided into upper (U) or low (L) depending on the route and the position of the row pair to be shuffled, and one is conscious of the pull from each row. There is. Note that in the drawings from FIG. 13 onward, hunting for cell rows is stopped for convenience of explanation.

Specifically, in the module 70 of FIG. 13, when shuffling is performed for (71)←→(73)←−(75), the column unrelated to the path (
Cell columns 72, 74) are also taken into account. Therefore, when shuffling is to be performed in the column pair of cell column 71-→self 3, the cell column 71 side is set as the low side, and the cell column 73 side is set as the upper side. Then, a cell column 72 unrelated to the path
The column 74 is on the low side, and the cell column 74 is on the upper side. Now, as shown in FIG. 14(a), the cell 71a in the cell column 71 has strong connections with the three cells 72a to 72c in the cell column 72. Assuming that, as shown in FIG. 14(b), the strongly connected self 1a is sent out to the cell row 73 once, and then the cell row 7
When shuffling on the other path through the second row, the first
4. As shown in FIG. 4(C), the cells are moved to the cell row 72, and the cells 1a are rearranged near the cells 3a to 73c. Therefore, by doing this, you will be aware of the cost of attracting from all columns in the module, and you will be able to obtain an overall well-balanced allocation result, increasing the efficiency of LSI layout design, shortening delivery time, and reducing costs. It is possible to reduce the

By utilizing the process of step P above, for example, a module with a partial initial arrangement as shown in FIG. It can be moved appropriately and easily, and the arrangement can be improved very smoothly.

Returning to the program again, in P, initial improvement of the order of internal cells within a column (in particular, setting of cut lines) is performed. The setting of the cut line is also unique to this embodiment, and the technology is more advanced than the conventional one, so a conventional example will be described first.

-M, in the EBB method placement program, Min-Cu
The intra-column order is optimized using the t method.

The cut line at that time is automatically set. Here, the Min-Cut method sets cut lines in the vertical and horizontal directions on the chip, sequentially divides the circuit so that the number of nets cut by the cut lines is minimized, and subdivides the block set elements. This is a method of becoming more For example, as shown in FIG. 15(a), the cut line 82 that divides the cell row 81 is
A good example is a layout improvement method in which the cell 81a is moved and replaced near the cell 81b on the right side of the figure, as shown in FIG. 15(b), so as to minimize the number of nets (connection lines) 83 cut by .

Until now, we have only dealt with Rec or at most L-shaped modules, so cut lines are set based on the module width. However, as the module shape becomes more complex, the possibility that an invalid cutline will occur increases, and it is necessary to set a cutline for each column width. A specific example of this problem is shown in FIG. 16. In FIG. 16, when cut lines 91 to 93 are automatically set to divide the module width into 2n (4 pieces in this embodiment) for the module 90,
The three cell rows 94-96 of the module 90 are cut into a total of 12 regions by cut lines 91-93.

In this way, the cut line is set based on the module width, and there is a relatively low possibility that an invalid cut line will appear in the Rect-shaped module 90 as shown in FIG. However, as shown in Figure 17, 5 ha
In the case of a PE-shaped module 100, the internal cell row 10
For 1 to 105, three cut lines 10 are created to simply divide the module width into four parts as in the case of FIG. 16.
If 6 to 108 are set, one cut line 107 crosses cell row 103, but other cell rows 101.10
2.104.105 cannot be crossed.

Also, the cell row 10 cut by the cant line 106
1.104 is not divided at its center part, but one part (
104b) is narrow, and is not an optimal cut line considering the size of the row. therefore,
This may result in an invalid cut line, and improvements are desired.

Therefore, in this embodiment, vertically adjacent columns having substantially the same width are regarded as one group (submodule), and a cut line is set for each submodule based on the width. By doing so, each row is separated at appropriate intervals, making it possible to obtain optimal cell placement compared to conventional cut lines based on module width.

Specifically, when five cell rows 111 to 115 are arranged in a 5-shape module 110 as shown in FIG. I reckon. Then, for each submodule, in other words, cell rows 111 to
Cut line 116 to 1 using the width as a reference every 115
Set 30. As a result, each sub-module is divided into four parts with the same area within the row, and there is no wastage of the cut lines 116 to 130, resulting in an extremely appropriate division. The effect of the Min-Cut method can be maximized even when exchanging the cell arrangement.

On the other hand, in the case of an example in which five cell rows 141 to 145 are arranged in a module 140 that has a recessed shape as shown in FIG. 19, which has a different shape from that in FIG. are also considered submodules, and each submodule has nine cant lines 14 based on their width.
Set from 6 to 154. In this case, cell columns 141 and 14
3 and the cell rows 142 and 144 are each considered to have substantially the same width, are considered to be the same submodule, and have a common cut line. Of course, even with the module 140 having such a shape, the same effects as the example shown in FIG. 18 can be obtained.

Returning to the program again, after automatically setting the cut line optimally in P6, the order of internal cells within the column is optimized in P. This is a method of exchanging the arrangement of a large number of cells in the same column with each other in an optimal pattern by taking into consideration the connection relationship with cells in other neighboring columns.

Next, in P8, the arrangement is improved by Y-mirror inversion of the internal cells. This method considers the module as a two-dimensional plane and completely reverses the left and right cell positions with respect to its Y axis (vertical direction) as a reference, and is effective as a unique technological process using a CAD microprocessor.

Next, in P9, the allocation of the external terminals to the cell columns is changed so that the connection relationship between the external terminals and the cell columns is optimized.

Pl. Now estimate the channel width for wiring.

In most gate array LSIs and standard cell LSIs, cell regions face each other and wiring regions exist between them. This wiring area is called a channel, and the wiring grid within the channel is called a track. Terminals to be connected are lined up on the upper and lower sides of the channel, and wiring is completed by allocating wiring line segments to the main line and branch lines.

Then, every other cell row was X-mirrored at pH
The pattern is optimized by inversion, that is, by completely exchanging the positions of the cell rows above and below with respect to the X axis (horizontal axis).

At pHZ, coordinates of external terminals are determined for the cell row, and layout design is completed. Finally, the PI3 outputs the above wiring results to the outside. For example, output to an external profiler and draw the layout on a drawing.

In this way, in this embodiment, during the steps of the program, P
Since a new method different from conventional methods is used for z, P4, Ps, and Pa, the internal cells of the LSI can be arranged in an optimal pattern at low cost, and the efficiency of layout design can be significantly improved.

In addition, in the above program, steps PII,
The processes of P9, p, and □ are performed only when specified in the program control statement.

〔effect〕

According to the present invention, the process of optimizing the allocation of internal cells to cell columns is performed by a shuffling method, and in the shuffling method, all columns are Since it is divided into at least two areas and shuffling is performed taking into consideration the connection relationship with the cell rows in each area, the overall balance is extremely good considering the cost of attracting from all the rows in the module. It is possible to perform allocation, and each internal cell of an LSI can be arranged in an optimal pattern at low cost.

[BRIEF DESCRIPTION OF THE DRAWINGS] Figures 1 to 19 are diagrams showing an embodiment of the method for manufacturing a semiconductor device according to the present invention. A diagram showing the first module, FIG. 3 is a layout diagram when arranging cells in the first module, FIG. 4 is a layout diagram when arranging cells in the second module, and FIG. Figure 6 is a layout diagram when dividing the first module, Figure 6 is a layout diagram when dead space occurs when dividing the first module, Figure 7 is the layout diagram when dividing the first module, and Figure 7 is the layout diagram when the cells are optimally allocated to the second module. Figure 8 is a layout diagram showing an example of arranging cell columns in the third module; Figure 9 is a diagram showing the third module divided into estimated column areas; Figure 10 is a layout diagram showing an example of arranging cells in each estimate column area of the third module, Figure 11 is a diagram showing the fourth module, and Figure 12 is a layout diagram showing the arrangement of cells in each estimate column area of the third module. A layout diagram showing an example of the arrangement, Figure 13 is a diagram showing an example of placing cells in the fifth module, and Figures 14 (a) to (c) are when moving cells within the fifth module. Figures 15(a) and 15(b) are diagrams explaining the Min-Cut method, Figure 16 is a diagram showing its sixth module, and Figure 17 is its sixth module. FIG. 18 is a diagram showing the eighth module, FIG. 19 is a diagram showing the ninth module, and FIGS. 20 and 21 are for explaining the conventional method of manufacturing a semiconductor device. FIG. 20 is a diagram showing the first module, and FIG. 21 is a diagram showing the second module. 50.60.70.901. 140...Module, 33-37...Area, 32,...Cell, space, 71-75.65-68.81.10120.27.3
1.40. 100.110 21-25.28.29. 26.30a-30e. 38.39...Deso 41-45.51-53, ~105.111, 115.141-145...Cell column, 54-56...Estimation column area, 57.5
8... Estimation column boundary, 61-64...
Estimated area, 82.106-108. 116-130. 146
~154...cut line, 83...net. Figure 2 shows the first module of the embodiment. Figure 3 shows the second module of the embodiment. Figure 3 shows the second module of the embodiment. Layout diagram when cells are optimally placed in the second monoyl. In the third module of the first embodiment! Layout diagram of Figure 5 Layout diagram when generated Fig. 6 Estimating the third module of the first embodiment Divide into areas 1
Figure 1: Cells are arranged in each estimated column area of the third monoyl of the first embodiment. Figure 10: A diagram showing the fourth module of the embodiment. Cell rows are arranged in the fourth module of the first embodiment. When moving the cell within the fifth monolayer of the first embodiment
1. Explanatory drawings, box diagrams, 11. Actual diagrams, diagrams showing cells arranged in the fifth module of the example. Fig. 17 is a diagram showing the seventh monoyl of the first embodiment Fig. 18 is a diagram for explaining the conventional second shuffling method Fig. 1 is a diagram showing the eighth monoyl of the first embodiment Diagram showing the 9th monoyl Figure 19 Diagram to explain the conventional 1st Noyafling method Diagram Relationship to the incident

Claims (4)

[Claims] (1) A first step of determining a module for gathering and arranging a large number of internal cells based on the number and shape of internal cells constituting a logic block, and a cell row placement area for arranging internal cells in a line. The second step is to divide the module, the third step is to allocate multiple cell rows with external terminals and a predetermined number of internal cells in the cell row placement area, and to optimize the allocation of internal cells to the cell rows. a fourth step of optimizing the arrangement of internal cells within the cell columns, and a fifth step of optimizing the arrangement of internal cells within the cell columns, and changing the allocation of external terminals for internal cells to columns or setting areas for wiring between cell columns. With,
a sixth step of determining the position of an external terminal, and the fourth step is a shuffling method of exchanging cells between two adjacent cell rows, In the ring method, all columns are divided into at least two regions according to the shuffling path and the position of the column pair to be shuffled, and shuffling is performed by considering the connection relationship with the cell columns in each region. A method for manufacturing a semiconductor device, characterized in that: (2) In the second step, the average height of the internal cells is calculated taking into account the wiring areas of adjacent cell rows, and the inside of the module is divided into a plurality of cell row placement areas based on this average height. 2. A method of manufacturing a semiconductor device according to claim 1, wherein: (3) In the third step, a determination flag is provided to determine whether or not a cell is placed in the module, and the position of the previously placed cell is read, and the module is configured by a logic block consisting of cells. When there is a change in the circuit requirements for an integrated circuit, the module is divided into estimated column areas based on the cell height, taking into account the wiring area for adjacent cell columns, and the estimated column area and the 2. The method of manufacturing a semiconductor device according to claim 1, wherein each cell is allocated to a cell column in accordance with a circuit change request by checking the overlap with the cell column. (4) The fifth step includes a cut line method of dividing the cell row into a plurality of parts, and the cut line method considers adjacent cell rows of approximately the same width as one unified submodule, 2. The method of manufacturing a semiconductor device according to claim 1, wherein a cut line is set for each sub-module based on its width.