JPH04251958A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To improve overload capacity with heat dissipation to the main body of a semiconductor base body by connecting a polycrystalline silicon region to the front side semiconductor region of a dielectric-isolated semiconductor base body from its rear side. CONSTITUTION:A substrate 1 is bonded to a substrate 2 via a dielectric film 3 and dielectric-isolated into a plurality of semiconductor regions 20 by dielectric films 5 and polycrystalline silicon 6: these dielectric-isolated semiconductor regions 21-23 have built-in transistors 51-53, respectively. Particularly, a polycrystalline silicon region 30 is built from the rear side of a semiconductor base body 10 into a semiconductor region 2 with a built-in bipolar transistor 51. The substrate 2 that is the main body of the semiconductor base body 10 is p-type reverse to n-type of the substrate 1. The polycrystalline silicon region 30 is the same as the semiconductor region 21, but built in n-type reverse to the substrate 2. This process can solve a contradiction between the prevention of interference of circuit components of an integrated circuit due to dielectric isolation and deterioration in heat dissipation of semiconductor regions.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device such as a BiMOS type integrated circuit device incorporated in a dielectrically separated wafer or chip.

0002

2. Description of the Related Art As is well known, in an integrated circuit device, there is a possibility that operation interference may occur between the component circuit parts of the integrated circuit device through the inside of the semiconductor. The circuit is divided into regions, and circuit parts each consisting of a circuit element or a group of circuit elements such as a transistor or a diode are distributed and created in each region, and then the circuit parts are interconnected by a wiring film. For this reason, junction isolation is commonly used as a means of separating semiconductor regions into multiple semiconductor regions, but since it relies on pn junctions, isolation is not always perfect, and extra transistors are required between semiconductor regions. Due to the presence of parasitic diodes and diodes, unexpected problems such as latch-up or malfunction may occur during operation.

In order to solve this problem, in an integrated circuit device to which the present invention is directed, a semiconductor substrate, which is a chip or a wafer for the device, is dielectrically separated into a plurality of semiconductor regions. As is well known, this dielectric separation structure includes a structure in which the main body is made of polycrystalline silicon and a structure in which a pair of semiconductor substrates are bonded together. The conventional structure of the integrated circuit device incorporated therein will be briefly described below with reference to FIGS. 3 and 4.

FIG. 3(a) shows a state in which a pair of semiconductor substrates 1 and 2 are bonded to each other. One of the substrates 1 is made of, for example, an n-type substrate, and its surface is coated with silicon oxide or the like using a steam oxidation method. After covering with the dielectric film 3, both substrates 1 and 2 are firmly bonded to each other via the dielectric film 3 by heat treatment at high temperature while adsorbed onto the mirror-finished surface of the substrate 2, thereby forming the semiconductor substrate 10. shall be. In the next figure 3(b), the board 1
The surface is ground to a thickness of several tens of micrometers, which is suitable for fabricating integrated circuits.

The process from FIG. 3(c) onwards is a step of dielectrically separating the substrate 1 into a plurality of semiconductor regions, and in FIG. The substrate 1 is divided into semiconductor regions 21 to 23 by cutting the semiconductor regions 21 to 23 until the grooves 4 are cut, and as shown in FIG.
Then, polycrystalline silicon 6 is grown to fill the trenches 4 by a thermal CVD method, etc., and finally, as shown in FIG. By exposing the semiconductor regions 21 to 23, the semiconductor substrate 10 is completed.

In the completed state shown in FIG. 3(e), the substrate 2
As shown in the figure, the semiconductor substrate 10 has a semiconductor substrate 10 which is divided into a plurality of semiconductor regions 21 to 23, and these semiconductor regions have a dielectric film 5 surrounding them and a polycrystalline silicon film 5 filling the gaps between them. 6 and dielectrically separated from the substrate 2 by the dielectric film 3. Therefore, the circuit portions of the integrated circuit formed in each of the semiconductor regions 21 to 23 can be placed at completely independent potentials from each other. It can be operated under

FIG. 4 very simply shows a state in which an integrated circuit is incorporated into this semiconductor substrate 10. In this example, the integrated circuit is a BiCMOS type, and a bipolar transistor 51 is installed in the semiconductor region 21, and a bipolar transistor 51 is installed in the semiconductor regions 22 and 23. to MOS
Transistors 52 and 53 are built in as shown in the figure. Bipolar transistor 51 is located in semiconductor region 2
The MOS transistor 52 is of the n-channel type and has a p-type base layer 51a, an n-type emitter layer 51b, and a collector connection layer 51c, with 1 being an n-type collector region. A well 52a, a gate 52b, and a pair of n-type source/drain layers 52c
and a p-type substrate connection layer 52d, and the MOS transistor 53 has a p-type substrate connection layer 52d in which the semiconductor region 23 is an n-type well.
It has a channel type gate 53a, a pair of p-type source/drain layers 53b, and an n-type substrate connection layer 53c, and these terminals, which are simply shown in the figure, connect to the integrated circuit via a wiring film (not shown). connected to form a

The semiconductor substrate 1 thus dielectrically separated
In an integrated circuit device using 0, there is little possibility that mutual interference will occur during the operation of the circuit parts 51 to 53, which are divided into the semiconductor regions 21 to 23, and there are no parasitic transistors or diodes between the semiconductor regions. Therefore, the operation is very reliable and stable, and it is used especially in circuits that require high operational reliability and circuits that handle high-frequency signals.

[0009]

[Problems to be Solved by the Invention] Conventional integrated circuit devices that utilize dielectrically isolated semiconductor substrates as described above are
Although it has the advantage of reliable and stable operation, the heat generated inside the semiconductor region surrounded by a dielectric film tends to be insufficiently dissipated, and it is difficult to dissipate heat generated inside the semiconductor region surrounded by a dielectric film. In particular, there is the problem that abnormal temperature rises are likely to occur.

For example, in the example shown in FIG. 4, since the external load is driven by the bipolar transistor 51 based on the result of processing digital signals by the MOS transistors 52 and 53, the amount of power handled is less than that of the bipolar transistor 51.
is the largest, and therefore the internal heat generation of the semiconductor region 21 in which it is formed is large, and the temperature is most likely to rise abnormally.

The dissipation of this internal heat generation is insufficient because each semiconductor region is completely surrounded by dielectric films 3 and 5 on its lower surface and periphery, respectively, and its upper surface is also covered with silicon oxide, although this is not shown in FIG. This is because the thermal conductivity of these films is much lower than that of silicon even if they are thin, and especially when a large load is applied in a short period of time, the dielectric film 3 or 5 acts as a barrier for heat dissipation, and internal heat generation directly increases the temperature of the semiconductor region, resulting in a reduction in the overload resistance of the circuit built therein.

An object of the present invention is to solve the contradiction between preventing interference between circuit parts of an integrated circuit by dielectric separation and deteriorating heat dissipation in the semiconductor region, and to improve the dielectric separation of the semiconductor substrate within the semiconductor substrate. The purpose is to improve heat dissipation in semiconductor regions.

[0013]

[Means for Solving the Problems] According to the present invention, circuit parts constituting an integrated circuit are incorporated into semiconductor regions dielectrically separated from each other on the front side of a semiconductor substrate, and a predetermined semiconductor region on the front side The above object is achieved by forming a polycrystalline silicon region to be connected inside the semiconductor substrate from the back side of the semiconductor substrate, and providing a back electrode for the predetermined semiconductor region connected to this polycrystalline silicon region on the back side of the semiconductor substrate. achieved.

[0014] The polycrystalline silicon region is preferably of the same conductivity type as the semiconductor region to which it is connected, and it is advantageous to increase its impurity concentration to lower the connection resistance. In addition, if the semiconductor substrate is a substrate bonding type in which a pair of substrates are bonded, the conductivity type of the substrate forming the main body of the semiconductor substrate is opposite to that of the substrate dielectrically separated into the semiconductor region, and the conductivity type of the polycrystalline silicon region is It is advantageous that the conductivity type is opposite to that of the main body substrate.

In the practical application of the invention, it is advantageous to provide a polycrystalline silicon region which is connected to the semiconductor region in which the bipolar transistor is integrated, the corresponding back electrode being the collector electrode of the bipolar transistor.

[0016]

[Operation] By providing the polycrystalline silicon region referred to in the above-mentioned structure to be connected to a predetermined semiconductor region from the back side of the semiconductor substrate, the internal heat generation of the semiconductor region is absorbed by the polycrystalline silicon region. The heat is radiated to the main body side of the semiconductor substrate through the semiconductor substrate, and this main body portion, which has a much larger heat capacity than the semiconductor region, is used as a heat absorber to cool the semiconductor region, and the back side of the semiconductor substrate, which is idle, is used. By providing a backside electrode connected to the polycrystalline silicon region as a terminal for the semiconductor region, there is no need to lead out this terminal to the front side of the semiconductor region, and the area can be saved accordingly. . Therefore, according to the present invention, heat dissipation in the semiconductor region is improved, and the chip area required for fabricating an integrated circuit can be saved.

[0017]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a cross-sectional view of an integrated circuit device according to the present invention, which corresponds to the conventional FIG. Therefore, duplicate parts in the following explanation will be omitted. In the following embodiments, the semiconductor substrate is of a substrate-bonded type, but the present invention can also be applied to the case of using a dielectric-separated type semiconductor substrate whose main body is made of polycrystalline silicon.

In the embodiment of the present invention shown in FIG.
is bonded to the substrate 2 via the dielectric film 3, dielectrically separated into a plurality of semiconductor regions 20 by the dielectric film 5 and polycrystalline silicon 6, and the dielectrically separated semiconductor regions 21 to 2
The point that transistors 51 to 53 are respectively formed in the semiconductor substrate 10 is completely the same as in the conventional structure shown in FIG. The difference is that a polycrystalline silicon region 30 is formed from the side. Further, the illustrated embodiment differs in that the substrate 2, which is the main body of the semiconductor substrate 10, is of p-type, which is opposite to the n-type of substrate 1.
The polycrystalline silicon region 30 is the same as the semiconductor region 21, but is formed in an n-type opposite to that of the substrate 2.

This npn type bipolar transistor 51 is fabricated in the semiconductor region 21 as its n type collector region as before, and the polycrystalline silicon region 30 allows a terminal for this collector region to be led out from the back side with low connection resistance. A collector terminal C is provided on the lower surface of the aluminum back electrode 40 which is in conductive contact through a window in the oxide film (not shown). Therefore, it is only necessary to lead out the base terminal B and emitter terminal E from the surface of the semiconductor region 21 for the transistor 51, and there is no need to diffuse the collector connection layer 51c as in the conventional case shown in FIG. 4, so the area can be saved. can do.

In the illustrated example, in order to increase the area of the portion forming the so-called base width between the base layer 51a and the emitter layer 51b to increase the current capacity of the transistor 51 as much as possible, the base layer 51a is connected to the semiconductor region 51. It is diffused into only a part of the surface of the emitter layer 51b to leave an exposed area of the semiconductor region 21, but if this is not particularly necessary, it is diffused from the entire surface and only the lower part of the emitter layer 51b is left as the base width forming region. If so, the area required for the semiconductor region 21 can be further reduced.

Since the polycrystalline silicon region 30 is of course directly connected to the semiconductor region 21 without intervening the dielectric film 3, the internal heat generation of the semiconductor region 21 is caused by the connection between this connection and the polycrystalline silicon region 21, as indicated by H in FIG. Heat is radiated toward the substrate 2 via the silicon region 30. Since the heat capacity of the substrate 2, which is the main body of the semiconductor body 10, is much larger than that of the semiconductor region 21, in the present invention, the semiconductor region 21 is strongly cooled by using the substrate 2 as a heat sink.

Next, the manufacturing method will be explained with reference to FIG. Figure 3(a) corresponds to Figure 3(a) of the prior art, and n
A dielectric film 3 made of silicon oxide or the like is applied to a substrate 1 having a shape of 1 to 2 μm using a steam oxidation method.
This example, which has a thickness of 500 μm, shows a state in which it is bonded to a p-type substrate 2. Next, the substrate 1 is ground to the surface indicated by L in the figure to a thickness of several tens of μm, for example, 30 to 30 μm, suitable for incorporating an integrated circuit.
The state corresponds to that shown in FIG. 3(b) with a thickness of 60 μm.

Next, in FIG. 2(b), the substrate 1 is connected to the semiconductor region 2.
Figures 1 to 23 show the state of dielectric separation, and Figure 3(c) shows the dielectrically separated state.
, (d) After cutting the groove 4, a dielectric film 5 is attached, and polycrystalline silicon 6 is further grown to obtain the state shown in the figure. Note that the size of each of the semiconductor regions 21 to 23 varies depending on the case, but is, for example, about several tens of μm square.

FIG. 2(c) shows a step of digging from the back side of the semiconductor substrate 10, in which a plasma etching method using, for example, SF6 and O2 as reaction gases is used, using the oxide film 7 etc. attached to the back side as a mask. Then, a deep hole 8 with a diameter of about 10 μm is dug until it reaches the dielectric film 3, and the dielectric film 3 remaining at the bottom is removed by etching with an aqueous solution of several tens of percent hydrofluoric acid to form the state shown in the figure. At this time, it is advantageous in growing polycrystalline silicon in the next step to set the plasma etching conditions so that the side surface of the hole 8 has a slight slope as shown in the figure.

FIG. 2(d) shows the growth process of this polycrystalline silicon 9. Preferably, after removing the oxide film 7 by etching from the state shown in FIG. Polycrystalline silicon 9 is formed into hole 8 by CVD method.
At this time, by adding phosphine to the source gas, the polycrystalline silicon 9 is strongly doped to the n-type and has a low resistivity value of several hundred mΩcm or less. Note that the width of the groove 4 created in the process of Fig. 2(b) is shown in Fig. 2(c).
) By aligning the diameters of the holes 8 made in the process of step 2 to approximately the same extent, the polycrystalline silicon 6 in FIG. 2(b) and the polycrystalline silicon 6 in FIG.
) It is also possible to share the growth process of polycrystalline silicon 9.

FIG. 2E shows the process of grinding the semiconductor substrate 10. By grinding both sides of the semiconductor substrate 10, the semiconductor regions 21 to 23 are left on the surface side, leaving the polycrystalline silicon 6 in the groove 4, as shown in the figure. The polycrystalline silicon 9 in the hole 8 is left and the substrate 2 is exposed on the back side. Note that instead of this grinding, it is also advantageous to use a plasma etching method using a chlorine-based reactive gas, and in this case, the semiconductor region 21
The dielectric film 5 remaining on 23 can be easily removed by wet etching.

Through the process shown in FIG. 2(e), the polycrystalline silicon in the hole 8 is converted into the aforementioned polycrystalline silicon region 30 connected to the semiconductor region 21, and the circuit portions 51 to 53 of the integrated circuit are formed as shown in FIG. A semiconductor substrate 10 comprising dielectrically separated semiconductor regions 21 to 23 suitable for forming
is completed. In the above embodiment, the polycrystalline silicon region 30 is provided in the semiconductor region 21 in which the bipolar transistor 51 is formed, but of course other circuit parts such as MOS transistors for driving an external load may be provided as necessary. It is also provided in the semiconductor region where the semiconductor is fabricated. Furthermore, it is of course possible to connect polycrystalline silicon regions to a plurality of semiconductor regions in which circuit portions of an integrated circuit are formed, as necessary.

[0028]

Effects of the Invention As described above, in the present invention, circuit parts constituting an integrated circuit are incorporated in semiconductor regions dielectrically separated from each other on the front surface side of a semiconductor substrate, and the semiconductor substrate is placed in a predetermined semiconductor region on the front surface side. By forming a polycrystalline silicon region to be internally connected from the back side of the semiconductor substrate and providing a back electrode for a predetermined semiconductor region connected to this polycrystalline silicon region on the back side of the semiconductor substrate, the following effects can be obtained. .

(a) By connecting a polycrystalline silicon region from the back side to the semiconductor region on the front side of the dielectrically separated semiconductor substrate, internal heat generation in the semiconductor region is transferred to the main body of the semiconductor substrate through the polycrystalline silicon region. The main body, which has a much larger heat capacity than the semiconductor area, can be used as a heat absorber to effectively cool the semiconductor area in which the circuit parts of the integrated circuit are built, thereby reducing the voltage and current of the circuit parts. Processing ability, especially overload tolerance, can be improved.

(b) By using the back side of the semiconductor substrate to provide a back electrode connected to the polycrystalline silicon region to serve as a terminal for a circuit part built into the semiconductor region, it is possible to By reducing the number of terminals to be led out, the area of the semiconductor region required for building the circuit portion can be saved.

The integrated circuit device according to the present invention is particularly suitable when an output circuit that directly drives an external load and therefore handles a large amount of electric power is integrated, and is advantageous in terms of both improving the load driving ability and saving chip area. This can have a remarkable effect.

[Brief explanation of the drawing]

FIG. 1 is a partially enlarged sectional view of a dielectrically separated semiconductor substrate showing an embodiment of an integrated circuit device according to the present invention.

2 is a partially enlarged cross-sectional view showing each main step of an example of a method for manufacturing a semiconductor substrate for an integrated circuit device corresponding to the embodiment of FIG. 1; FIG.

FIG. 3 is a partially enlarged cross-sectional view showing each main step of a conventional method for manufacturing a dielectrically isolated semiconductor substrate for an integrated circuit device.

FIG. 4 is a partially enlarged sectional view of a dielectrically isolated semiconductor substrate showing an integrated circuit device according to the prior art.

[Explanation of symbols]

1　　　　Substrate constituting the semiconductor substrate 2　　　　Substrate constituting the semiconductor substrate 3 Dielectric film 5 Dielectric film 6 Polycrystalline silicon 7 Polycrystalline silicon 10 Semiconductor substrate 20 Semiconductor area 21 Semiconductor area 22 Semiconductor area 23 Semiconductor area 30 Polycrystalline silicon region 40　　　　Back electrode 50 Circuit part of integrated circuit

Claims (3)

[Claims] 1. Circuit parts constituting an integrated circuit are incorporated in semiconductor regions dielectrically separated from each other on the surface side of a semiconductor substrate, and a polycrystalline silicon region is connected to a predetermined semiconductor region on the surface side inside the semiconductor substrate. 1. An integrated circuit device characterized in that a semiconductor substrate is formed from the back side of the semiconductor substrate, and a back electrode for a predetermined semiconductor region connected to the polycrystalline silicon region is provided on the back side of the semiconductor substrate. 2. The integrated circuit device according to claim 1, wherein the polycrystalline silicon region has the same conductivity type as the predetermined semiconductor region. 3. The integrated circuit device according to claim 1, wherein the circuit portion built into the predetermined semiconductor region is a bipolar transistor having the collector region thereof, and the back surface electrode is the collector electrode.