JPH04251343A - Error information processing circuit - Google Patents

Abstract

PURPOSE:To recognize the place where an error occurs at once so that adjustment can be performed in a short time by detecting the error by means of plural error detecting sections respectively provided to plural status monitoring areas and controlling the error detecting sections by using individual hold signals. CONSTITUTION:When a signal having a logical value '1' is inputted to an error accumulating mode flag generating section 6 from the outside as a control signal 106, an error accumulating mode signal 104 having a logical value '1' indicating that an error accumulating mode is 'ON' is continuously outputted until '0' is inputted next. In the case an error detecting section 2B connected to another EIF, for example, EIF 3B in the same group operates and outputs '1' when the status of the 1st EIF 3A becomes '1' and error information is outputted, the hold control section 4B connected to the 1st EIF 3B operates and set the EIF 3B to the status of '1' by outputting the 1st hold signal 107B irrespective of the operation of the other 1st EIFs.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error information processing circuit, and more particularly to an error information processing circuit that generates a flag indicating the location of the fault when a fault occurs in an information processing device used in a computer or the like. Regarding.

0002

[Background Art] In order to monitor the operating status of a device that processes digital information such as a computer and detect abnormal conditions, a parity bit is added to the digital data used in the device and a parity check is performed to detect errors. method in which the unit of digital data is n
bit (n is 2 or more), the value of a specific digit is always set to the logical value "1", the value of this specific digit is monitored by the error detection unit, and if the value of this specific digit is "0", Errors are detected using the 1/n check method, which detects an error when the error occurs.

FIG. 3 is a block diagram showing an example of a conventional error information processing circuit. The information processing circuits to be directly monitored are divided into groups 1 to M in the lowest hierarchy, and error information processing circuits shown in group 1 in the lowest hierarchy are also provided in groups 2 to M in the lowest hierarchy. ing. The block diagram shown in FIG. 3 shows an error information processing circuit, and the registers 1A, 1B...1N have error detection units 2A, 2B...
2N is connected. These error detection units 2A, 2B
...The output side of 2N is the first error indicator flag generating section (hereinafter referred to as the error indicator flag generating section).
(referred to as IF) are connected to the input sides of 3A, 3B...3N. The outputs of these first EIFs 3A, 3B...3N are connected to the input side of the first OR gate 5. The output of the first OR gate 5 is applied as a first hold signal 109 to the first EIFs 3A, 3B...3N as a control signal. The registers 1A, 1B...1N, error detection units 2A, 2B...2N, first EIFs 3A, 3B...
3N and the first OR gate 5, one digital processing unit, that is, the first lowest hierarchical group 1
is monitoring errors. The conventional example shown in FIG. 3 shows a case where there are M such lowest hierarchy groups. There may be at least one such lowest hierarchy group.

As shown in FIG. 3, when there are a plurality of such lowest hierarchy groups, the output of the first OR gate 5 belonging to each lowest hierarchy is
Add to the input side of EIF7A, 7B...7M. The output of each of these second EIFs is connected to the input side of the second OR gate 8, and the output of the second OR gate 8 is connected to each of the second EIFs.
7A, 7B...7M as a second hold signal 108.

These second EIFs 7A, 7B, . . . , 7M and the second OR gate 8 constitute an error information processing circuit in the hierarchy immediately above the lowest hierarchy.

[0006] When there are a large number of lowest-level hierarchical groups, these lowest-level hierarchical groups are grouped into a smaller number of immediately superior hierarchical groups, and these multiple immediately superior hierarchical groups are arranged as shown in FIG. They may be grouped together in the same way as the immediately upper hierarchy shown.

When an abnormality occurs in the operation of the register 1A belonging to the lowest hierarchical group 1 in the error information processing circuit described above, the error detection section 2A detects this and outputs a signal with a logic value of "1", for example. This output is the first EIF3
It is input to A.

The first EIFs 3A, 3B...3N can have a state of either "1" or "0", and while an external hold signal, for example, a signal "1" is applied, Holds the state immediately before the hold signal is applied. Here, when there is no error detection signal from the error detection units 3A, 3B...3N, the first EIF 3A, 3B...3N
For example, when the error detection unit 2A outputs "1" as the error detection output, the state of the first EI is "0".
The state of F3A also becomes "1" and outputs this value. EIF
When 3A outputs "1", this output is applied to the first OR gate 5. The output of the first OR gate 5 is applied to each of the first EIFs 3A, 3 as a first hold signal 109.
B...3N to maintain the state of each EIF in the state immediately before the first hold signal 109 was applied. That is, the first EIF3A is in state "1"
Therefore, the other first EIFs 3B, . . . , 3N maintain the state "0", and thereafter maintain the above state until the first hold signal 105 is disconnected.

Furthermore, "1" is output from the first OR gate 5.
is output and the state of the second EIF7A becomes "1" and the second
The second hold signal 1 output from the OR gate 8 of
08 becomes "1" and all second EIFs 7A, 7B...
7M is held in the state immediately before this second hold signal 108 becomes "1". That is, the second EIF 7A is held in the state "1" and all EIFs 7B...7M are held in the state "0", and the above-mentioned state is maintained until the second hold signal is disconnected.

[0010] By monitoring the output of the second OR gate 8, all errors occurring in the lower hierarchy can be detected.

Normally, a scan path circuit (not shown) is incorporated in the first EIF 3A, 3B...3N and the second EIF 7A, 7B...7M, and as described above, this scan path circuit is operated by an external signal. Each EIF can be read externally without changing its status.
Further, the state of each EIF can be reset to any arbitrary state of "1" or "0" by the above-described scan path circuit.

0012

[Problems to be Solved by the Invention] In the conventional error information processing circuit described above, when any one of the plurality of EIFs is in the state "1", the error information processing circuit including the EIF in the state "1" A hold signal is also applied to other EIFs connected to the input side of the OR gate whose input is the EIF whose value is "1", and all EIFs connected to the output side of this OR gate are also held. Maintains the state immediately before the signal is applied.

[0013] Thereafter, even if an error is detected by the error detection section to which another EIF belonging to the same group as the lowest layer is connected, the EIF connected to this error detection section will be in the state "0". If the state remains unchanged, the state will not be "1".

[0014] In such an error information processing circuit, as long as the information processing circuit that monitors errors has already been sufficiently adjusted and is in a normal operating state, errors rarely occur frequently at multiple locations. The EIF of the lowest hierarchy and the EIF of the higher hierarchy related to the error that was first detected in time are set to "1", and the states of other EIFs are held to "0", so that the true fault location is It is easy to identify.

However, in a newly assembled information processing circuit in which such an error information processing circuit is incorporated, or in an unadjusted device having a plurality of these information processing circuits, errors occur frequently. If the information processing circuit or information processing device described above generates errors at multiple locations in chronological order during the process of processing determined information, adjust the location that causes the first error. Otherwise, it will be impossible to determine where the next error occurs. Therefore, when an error occurs while operating such an information processing circuit or device, it is necessary to adjust the cause of the error and then find the cause of the next error and make adjustments, which takes a long time. It had the disadvantage of requiring

An object of the present invention is to operate such a circuit or device for an appropriate period of time when a target information processing circuit or a device including a plurality of such information processing circuits is not adjusted, and to eliminate errors in multiple locations. This makes it possible to understand from the beginning how many places are causing errors and where they are, and to make adjustments in a short time. Another object of the present invention is to provide an error information processing circuit that can identify where an error occurs when it occurs, as in the prior art.

[0017]

[Means for Solving the Problems] The error information processing circuit of the present invention divides a target information processing section into a plurality of status monitoring areas, and detects errors using a plurality of error detection units provided for each status monitoring area. and inputs the detection output to a first error indicator/flag generation section each controlled by an individual first hold signal to generate the first error indicator and flag.
A first logic gate that operates the error indicator/flag generation units of the first error indicator/flag generation units to output individual signals and takes the logical sum of the output signals from each of the first error indicator/flag generation units; In the error information processing circuit that outputs a sum signal, when the first hold signal is applied, each of the first error indicator flag generating units maintains the state immediately before the hold signal is applied, and When the first hold signal is not applied, the hold signal changes according to the output from the error detection section, and the first hold signal is provided in one-to-one correspondence to each of the first error indicator flag generation sections. The output of the corresponding first error indicator flag generating section, the output of the first OR gate, and the error accumulation mode signal are input, and the output of the corresponding first error indicator flag generating section is a logical value. When it is "1", the hold signal is always output to the corresponding first error indicator flag generation section, and the error accumulation mode signal is "0".
'', if the output of the first OR signal becomes ``1'', the hold signal is changed to the corresponding first error signal.
Hold control that outputs the hold signal to the indicator/flag generation section and does not output the hold signal when the error accumulation mode signal is "1" even if the first OR signal is "1" or "0". and an error accumulation mode flag generating section that outputs the error accumulation mode signal in response to an external control signal.

[0018]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the error information processing circuit of the present invention, and FIG. 2 is a block diagram showing an embodiment of the hold control section in the embodiment of FIG.

The same parts as those already explained with reference to FIG. 3 will be omitted in the following explanation. In FIG. 2, as in FIG. A block diagram shows an embodiment in which error information that exists in a plurality of groups and that collects error information from these groups at the immediately upper layer is output.

The lowest hierarchy groups 1 to M each have the same configuration as that shown in the lowest hierarchy group 1. The output of the error accumulation mode flag generation section 6 is connected to the input side of the hold control sections 4A, 4B...4N whose outputs are connected to the first EIFs 3A, 3B...3N, respectively. A control signal 106 is input to.

[0022] Also, each hold control section 4A, 4
On the input side of B...4N, there is a first EIF3 in one-to-one correspondence.
The outputs of A, 3B, . . . , 3N are connected, and the output of the first OR gate 5 is also connected. Hold control section 4A
, 4B...4N may have the configuration shown as a block diagram in FIG. 2, for example.

When a signal having a logical value of "1" is applied to the error accumulation mode flag generating section 6 from the outside, for example, as the control signal 106, the error accumulation mode remains ON until the next input of "0". It outputs the value "1", and when "0" is input, it outputs the logical value "0" which indicates that the error accumulation mode is OFF until the next "1" is input.

Here, as the control signal 106, the control signal "
When 1'' is input to the error accumulation mode flag generation unit 6 in the lowest hierarchy group 1, an error accumulation mode signal 104 with a logical value of ``1'' indicating that the error accumulation mode is ON is output.

The error accumulation mode signal 104 is applied to the input side of the NOT circuit 41 constituting the hold control section 4A. At the same time, other hold control units 4B...4 having the same configuration
It is also added to the input side of N. In such a state, even if the output from the first OR gate 5 is "0" or "1", the output of the AND circuit 42 is "0", so the third OR gate 43 The output of the first signal is controlled by the first hold signal which is the output of this hold control section 4A.
The first hold signal 107A (logical value "1") is output only when the output 107A from the EIF 3A becomes "1". That is, the first hold signal 107A becomes "1" only when the state of the first EIF 3A becomes "1", and other first EIFs, such as the first EIF 3B, are not held.

Therefore, in such a state, even if the status of the other first EIF in the same group becomes "1" and outputs error information, the other first EIF in the same group
If the error detection unit 2B connected to the EIF, for example EIF3B, operates and outputs "1", this first EIF
The hold control unit 4B connected to the IF 3B operates and outputs the first hold signal 107B, and the first EIF
Hold 3B at "1". That is, when the error accumulation mode signal is ON, the hold control circuit to which this signal is input is connected to other first E in the first group.
Regardless of the operation of the IF, when the state of the first EIF to which the hold control circuit is connected changes from "0" to "1", a first hold signal is generated and the first EIF
hold the state.

Next, the error accumulation mode flag generating section 6
When the output of
...When any one of 3N becomes "1", the output 105 of the first OR gate 5 becomes the hold control section 4A, 4.
B...When input to 4N, the output of the AND circuit 42 becomes "1"
Therefore, the first hold signals 107A, 107B...1
07N, etc. are output, so all the first EIFs 3A, 3B, . . . , 3N belonging to the same group are held in their respective states immediately before the first hold signal is input.

In the error information processing circuit having the configuration shown in FIG. 1, a logic value "" is applied to any one of the error accumulation mode flag generation sections 6 provided in each of the lowest hierarchical groups. If a signal with a logical value of ``1'' is inputted to the other error accumulation mode flag generation unit 6, and a signal with a logical value of ``0'' is inputted, each of the first EIFs in the lowest hierarchical group to which the above-mentioned ``1'' was inputted can also be operated independently.

As described above, the error information processing circuit of the present invention has the hold control sections 4A, 4B...4N and the error accumulation mode flag generation section 4 in addition to the conventional error information processing circuit of this type.
A, 4B...4N is added, but the circuits provided in the lowest layer groups which are larger than those shown in FIG. A third EI (not shown) in a higher layer further collects the error information output from the logical sum gate and outputs the error information output from the OR gate.
It is clear that the error information can be output together by connecting F and the fourth OR circuit in the same way as the immediately upper layer shown in FIG.

[0030]

As explained above, the error information processing circuit of the present invention can identify where the first error occurred in terms of time, as well as the conventional error information processing circuit of this type, and can By adding a control signal, the error monitoring state is set to a different mode, and the occurrence status of errors that occur in a chronological order within a preset monitoring group is determined by multiple error flag generation units provided within this monitoring group. Since they can be held independently of each other and measured at once, multiple error locations can be determined in a short time when the information processing circuit or device being monitored for errors is in an unadjusted state, and this information can be obtained in a shorter time than before. The advantage is that the processing circuit or device can be adjusted.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an error information processing circuit of the present invention.

FIG. 2 is a block diagram showing an embodiment of the hold control section shown in FIG. 1;

FIG. 3 is a block diagram showing an example of a conventional error information processing circuit of this type.

[Explanation of symbols]

1A, 1B, 1N Register 2A, 2B, 2N Error detection section 3A, 3B, 3
N First error indicator flag generation section 4A, 4B, 4N Hold control section 5 First OR gate 6 Error accumulation mode flag generation section 8 Second OR gate 41 NOT circuit 42 AND circuit 43 Third disjunction gate of

Claims (3)

[Claims] Claim 1: A target information processing unit is divided into a plurality of condition monitoring areas, an error is detected by a plurality of error detection units provided for each condition monitoring area, and the detected output is stored in a separate first hold. input to a first error indicator flag generator controlled by the signal to operate the first error indicator flag generator to output a separate signal for each of these first error indicators. In the error information processing circuit that outputs a first OR signal in addition to a first logic gate that ORs output signals from the flag generation section, each of the first error indicator flag generation sections is connected to the first logic gate. When a hold signal is applied, the state immediately before this hold signal is applied is maintained, and when the first hold signal is not applied, the state is changed according to the output from the error detection section, and the state is changed according to the output from the error detection section. The output of the corresponding first error indicator/flag generating unit, the output of the first OR gate, and the error accumulation are provided in a one-to-one correspondence with each of the error indicator/flag generating units of mode signal as input and said corresponding first error indicator;
Whenever the output of the flag generation section is a logical value "1", the hold signal is outputted to the corresponding first error indicator flag generation section, and when the error accumulation mode signal is "0", the hold signal is outputted to the corresponding first error indicator flag generation section. When the output of the OR signal of 1 becomes "1", the hold signal is outputted to the corresponding first error indicator flag generating section, and when the error accumulation mode signal is "1", the hold signal is outputted to the first error indicator flag generating section.
a hold control unit that does not output the hold signal even if the OR signal of is “1” or “0”; and an error accumulation mode flag generation unit that outputs the error accumulation mode signal based on an external control signal. An error information processing circuit comprising: 2. A plurality of error information processing circuits, the input side being individually connected to the output of each error information processing circuit, controlled by a second hold signal, and similar to the first error indicator flag generation section. a plurality of second error indicator flag generation units that perform operations;
a second logical sum that receives the outputs of the plurality of second error indicator flag generating units, outputs a logical sum thereof, and adds the logical sum to each of the second error indicator flag generating units as the second hold signal; An error information processing circuit characterized by comprising a gate. 3. A NOT circuit that receives the error accumulation mode signal as an input, an AND circuit that receives the output of the first NOT circuit and the output of the first OR gate, and the first error indicator. - The hold control unit is configured by a third OR gate that receives the output of any one of the flag generation units and the output of the AND circuit as input and outputs the first hold signal. The error information processing circuit according to claim 1 or claim 2.