JPH0424952B2 - - Google Patents

Info

Publication number
JPH0424952B2
JPH0424952B2 JP59103337A JP10333784A JPH0424952B2 JP H0424952 B2 JPH0424952 B2 JP H0424952B2 JP 59103337 A JP59103337 A JP 59103337A JP 10333784 A JP10333784 A JP 10333784A JP H0424952 B2 JPH0424952 B2 JP H0424952B2
Authority
JP
Japan
Prior art keywords
voltage
pair
output
pulses
nand circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59103337A
Other languages
Japanese (ja)
Other versions
JPS60249867A (en
Inventor
Harunobu Yoshida
Tsuneaki Sasaki
Yasuhiro Arai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Telecom Networks Ltd
Original Assignee
Fujitsu Telecom Networks Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Telecom Networks Ltd filed Critical Fujitsu Telecom Networks Ltd
Priority to JP10333784A priority Critical patent/JPS60249867A/en
Publication of JPS60249867A publication Critical patent/JPS60249867A/en
Publication of JPH0424952B2 publication Critical patent/JPH0424952B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/22Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は、スイツチング周波数の基準となる鋸
歯状波電圧と負荷変動に対応する電圧(出力電圧
の定格電圧に対する変動電圧)とを比較し、パル
ス幅変調制御によりトランジスタをオン、オフ制
御して出力電圧を安定化するスイツチングレギユ
レータの改良に関する。
[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention compares a sawtooth wave voltage serving as a reference for the switching frequency with a voltage corresponding to load fluctuation (a fluctuation voltage with respect to the rated voltage of the output voltage), This invention relates to improvements in switching regulators that stabilize output voltage by controlling transistors on and off using pulse width modulation control.

(b) 技術の背景 パルス幅制御を行うスイツチングレギユレータ
は、スイツチング周波数を高周波に出来るので変
圧器は小形化出来又平滑回路を簡単に出来るので
最近電子機器用の直流電源として広く使用されて
いる。
(b) Background of the technology Switching regulators that perform pulse width control have recently been widely used as DC power sources for electronic devices because the switching frequency can be set to a high frequency, making it possible to miniaturize transformers and simplifying smoothing circuits. ing.

(c) 従来技術と問題点 従来例のスイツチングレギユレータ及び問題点
に付き図を用いて説明する。
(c) Prior Art and Problems A conventional switching regulator and problems will be explained using the accompanying drawings.

第1図は従来例のスイツチングレギユレータの
回路図、第2図第3図は第1図の各部の波形のタ
イムチヤートで、第2図は正常な場合第3図はダ
ブルパルス発生の場合であり、B〜Cは第1図の
b〜c点に対応している。
Fig. 1 is a circuit diagram of a conventional switching regulator, Fig. 2 and Fig. 3 are time charts of waveforms at various parts in Fig. 1, Fig. 2 shows normal operation, and Fig. 3 shows double pulse generation. In this case, B to C correspond to points b to c in FIG.

第1図の動作を説明すると、負荷7の電圧と参
照電圧Vrefとの差を演算増幅器1にて求ると、
正常な場合は第2図Aの2に示す如き電圧とな
る。
To explain the operation of FIG. 1, when the difference between the voltage of the load 7 and the reference voltage Vref is determined by the operational amplifier 1,
In a normal case, the voltage will be as shown at 2 in FIG. 2A.

この電圧と、鋸歯状波電圧発生器3よりの第2
図Aの1に示す電圧とを比較器2で比較すると鋸
歯状波電圧の方が大きい間の幅のパルスを発す
る。このパルスをフリツプフロツプ(以下FFと
称す)4とアンド回路5,6にて分離すると、第
2図B,Cに示す如きパルスがアンド回路5,6
の出力パルスとなる。
This voltage and the second voltage from the sawtooth voltage generator 3
When the comparator 2 compares the voltage shown at 1 in FIG. A, the sawtooth voltage generates a pulse with a larger width. When this pulse is separated by a flip-flop (hereinafter referred to as FF) 4 and AND circuits 5 and 6, a pulse as shown in FIG.
The output pulse will be .

これ等のパルスは、トランジスタTr1,Tr2
トランスT1を介し主トランジスタTr3,Tr4をス
イツチングするパルス電圧となり、主トランジス
タTr3,Tr4で直流電源Eをスイツチングして、
トランスT2に流れる電流を交流とし、このこと
によりトランスT2に誘起する電圧をダイオード
D1,D2チヨークL、コンデンサC3にて平滑化し
て負荷7に電力を供給する。
These pulses are transmitted through transistors Tr 1 , Tr 2 ,
It becomes a pulse voltage that switches the main transistors Tr 3 and Tr 4 via the transformer T 1 , and the main transistors Tr 3 and Tr 4 switch the DC power supply E,
The current flowing through the transformer T 2 is made into an alternating current, and the voltage induced in the transformer T 2 by this is changed to a diode.
Power is supplied to the load 7 after smoothing by D 1 , D 2 yoke L and capacitor C 3 .

しかし演算増幅器1の出力が雑音により第3図
Aの2のイ,ロ,ハに示す如く変動すると、第3
図Aの1に示す鋸歯状波電圧はイ点にてAの2の
電圧を越え、ロ点では以下となり、ハ点では又越
えることになる。
However, if the output of the operational amplifier 1 fluctuates due to noise as shown in 2 A, B, and C of Figure 3A, the 3rd
The sawtooth wave voltage shown at 1 in Figure A exceeds the voltage 2 at A at point A, becomes less than at point B, and exceeds it again at point C.

こうなるとアンド回路5及び6の出力は第3図
B,Cの示す如きパルスとなり、アンド回路5よ
り出力パルスは、1つ飛びの鋸歯状波電圧毎に出
力していたものが、2つの連続した鋸歯状波電圧
毎に出力するようになる。
In this case, the outputs of the AND circuits 5 and 6 become pulses as shown in FIG. output for each sawtooth wave voltage.

一方アンド回路6よりの出力パルスも、2つの
連続した鋸歯状波電圧毎に出力するようになるも
この場合は雑音により発するパルスはニに示す如
く幅が狭いので、トランスT2を偏磁する原因と
なり、ひいては主トランジスタTr3又はTr4を破
損することが起こる。
On the other hand, the output pulse from the AND circuit 6 is also output every two consecutive sawtooth wave voltages, but in this case, the pulses generated due to noise have a narrow width as shown in D, so the transformer T 2 is polarized. This may cause damage to the main transistor Tr 3 or Tr 4 .

このように2つの連続した鋸歯状波電圧毎にパ
ルスを発する現象をダブルパルス発生と称し、こ
の現象が起こると上記の如く主トランジスタを破
損する原因となるので、ダブルパルス発生を防止
する必要があるも、従来はこの対策がなされてい
ない問題がある。尚第1図のR1,R2は抵抗であ
る。
The phenomenon of emitting a pulse every two consecutive sawtooth wave voltages in this way is called double pulse generation, and if this phenomenon occurs, it will cause damage to the main transistor as described above, so it is necessary to prevent double pulse generation. However, there is a problem in which no countermeasures have been taken in the past. Note that R 1 and R 2 in FIG. 1 are resistances.

(d) 発明の目的 本発明の目的は上記の問題に鑑み、ダブルパル
スを発生させないパルス幅制御回路の提供にあ
る。
(d) Object of the Invention In view of the above problems, an object of the present invention is to provide a pulse width control circuit that does not generate double pulses.

(e) 発明の構成 本発明は、上記の目的を達成するためになされ
たもので、出力電圧と定格出力電圧の基準となる
参照電圧との誤差を負荷変動に対応する電圧とし
て演算増幅する演算増幅器と、該負荷変動に対応
する電圧とスイツチング動作周波数の基準となる
鋸歯状波電圧とを比較する比較器と、該比較器の
出力パルスを入力とし、互いに逆相の一対の反転
パルスを出力するフリツプフロツプ回路と、前記
比較器の出力パルスと該一対の反転パルスのそれ
ぞれとの論理積を反転する一対のナンド回路と、
該一対のナンド回路の出力パルスをそれぞれ微分
して前記比較器の負荷変動に対応する電圧に帰還
する一対の微分回路と、該一対のナンド回路の出
力パルスをそれぞれ反転して一対の駆動パルスを
出力する一対のインバータ回路とからなるパルス
幅制御回路を構成することにより、鋸歯状波電圧
が負荷変動に対応する電圧を越えた時、該時点か
ら長くとも該鋸歯状波電圧が該負荷変動に対応す
る電圧よりも低くなる迄の期間、該負荷変動に対
応する電圧を強制的に低下させるようにしたもの
である。
(e) Structure of the Invention The present invention has been made to achieve the above-mentioned object, and includes an operation for operationally amplifying the error between the output voltage and a reference voltage, which is the standard for the rated output voltage, as a voltage corresponding to load fluctuations. An amplifier, a comparator that compares the voltage corresponding to the load fluctuation with a sawtooth wave voltage that serves as a reference for the switching operating frequency, and receives the output pulse of the comparator as input and outputs a pair of inverted pulses with mutually opposite phases. a flip-flop circuit that inverts the logical product of the output pulse of the comparator and each of the pair of inverted pulses;
a pair of differentiating circuits that differentiate the output pulses of the pair of NAND circuits and feed back a voltage corresponding to the load fluctuation of the comparator; and a pair of drive pulses that invert the output pulses of the pair of NAND circuits, respectively. By configuring a pulse width control circuit consisting of a pair of output inverter circuits, when the sawtooth wave voltage exceeds the voltage corresponding to the load fluctuation, the sawtooth wave voltage will be adjusted to the load fluctuation at the longest from that point onwards. The voltage corresponding to the load change is forcibly lowered until the voltage becomes lower than the corresponding voltage.

即ち該鋸歯状波電圧と該負荷変動に対応する電
圧との差が小さく、雑音が乗つた場合ダブルパル
スを発する原因となるのは、該鋸歯状波電圧が該
負荷変動に対応する電圧を越えた時であるので、
この点で該負荷変動に対応する電圧を強制的に下
げて、該負荷変動に対応する電圧に雑音が乗つて
も、この雑音による電圧が該鋸歯状波電圧を越え
なくしてダブルパルスの発生を防止するようにし
たものである。
In other words, when the difference between the sawtooth wave voltage and the voltage corresponding to the load fluctuation is small and noise is added, double pulses are generated because the sawtooth voltage exceeds the voltage corresponding to the load fluctuation. Since it was a time when
At this point, the voltage corresponding to the load fluctuation is forcibly lowered, and even if noise is added to the voltage corresponding to the load fluctuation, the voltage due to this noise does not exceed the sawtooth voltage, thereby preventing the generation of double pulses. It is designed to prevent this.

(f) 発明の実施例 以下本発明の一実施例につき図に従つて説明す
る。
(f) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings.

第4図は本発明の実施例のスイツチングレギユ
レータの回路図、第5図は第4図の各部の波形の
タイムチヤートでB,Cは第4図のb,c点に対
応している。
Fig. 4 is a circuit diagram of a switching regulator according to an embodiment of the present invention, and Fig. 5 is a time chart of waveforms at various parts in Fig. 4. B and C correspond to points b and c in Fig. 4. There is.

第4図中第1図と同一機能のものは同一記号で
示し、5′,6′はナンド回路、8,9はインバー
タ回路、C4,C5はコンデンサ、R3,R4は抵抗を
示す。
Components in Figure 4 that have the same functions as those in Figure 1 are indicated by the same symbols. 5' and 6' are NAND circuits, 8 and 9 are inverter circuits, C 4 and C 5 are capacitors, and R 3 and R 4 are resistors. show.

第4図にて第1図と異なる点は、第1図のアン
ド回路5,6のかわりにナンド回路5′,6′を用
いて従来の場合と反転したパルスを出力し、又イ
ンバータ回路8,9を設け又反転して、このイン
バータ回路8,9の出力パルスを、従来のアンド
回路5,6の出力パルスと同じようにし、ナンド
回路5,6の出力と比較器2の入力との間に、コ
ンデンサC4、抵抗R3及びコンデンサC5、抵抗R4
よりなる直列回路を設けた点である。
The difference between FIG. 4 and FIG. 1 is that NAND circuits 5' and 6' are used instead of AND circuits 5 and 6 in FIG. . In between, capacitor C 4 , resistor R 3 and capacitor C 5 , resistor R 4
The point is that a series circuit consisting of the following is provided.

このようにすればナンド回路5′,6′の出力の
パルスは第5図B,Cに示す如く従来と反転され
た物となり、このパルスが“1”レベルより
“0”レベルとなると、比較器2の入力側より、
抵抗R3コンデンサC4又は抵抗R4コンデンサC5
介して、ナンド回路5′又は6′の出力側に電流が
引込まれ、比較器2の入力側の負荷7に対応した
電圧が、従来は第3図Aの2であつた物が、第5
図Dの2′の如く、鋸歯状波電圧が、負荷変動に
対応した電圧より上つた点で直ちに電圧が下り又
復旧する。
In this way, the output pulses of the NAND circuits 5' and 6' become inverted from the conventional ones as shown in FIG. From the input side of device 2,
A current is drawn into the output side of the NAND circuit 5' or 6' via the resistor R 3 capacitor C 4 or the resistor R 4 capacitor C 5 , and the voltage corresponding to the load 7 on the input side of the comparator 2 is The item 2 in Figure 3 A is the 5th item.
As shown at 2' in Figure D, at the point where the sawtooth wave voltage exceeds the voltage corresponding to the load fluctuation, the voltage immediately drops and recovers.

従つて第5図Dに示す如く、鋸歯状波電圧1が
負荷変動に対応する電圧2′を越えた時従来は差
が小さかつたものが、差が大きくなり、ホに示す
如く雑音が乗つてもダブルパルスを発生すること
が無くなる。尚この下つた電圧は、コンデンサ
C4抵抗R3及びコンデンサC5抵抗R4の値を選択し
鋸歯状波電圧が負荷変動に対応する電圧より下る
迄の間に復旧するようにすればよい。
Therefore, as shown in FIG. 5D, when the sawtooth wave voltage 1 exceeds the voltage 2' corresponding to the load fluctuation, the difference, which was previously small, becomes large, and the noise is multiplied as shown in E. This eliminates the possibility of generating double pulses even when Furthermore, this voltage drop is caused by the capacitor
The values of the C 4 resistor R 3 and the capacitor C 5 resistor R 4 may be selected so that the sawtooth wave voltage is restored before it falls below the voltage corresponding to the load fluctuation.

(g) 発明の効果 以上詳細に説明せる如く、本発明によれば、ダ
ブルパルスを発生させなく出来る効果がある。
(g) Effects of the Invention As explained in detail above, the present invention has the effect of preventing the generation of double pulses.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例のスイツチングレギユレータの
回路図、第2図第3図は第1図の各部の波形のタ
イムチヤート、第4図は本発明の実施例のスイツ
チングレギユレータの回路図、第5図は第4図の
各部の波形のタイムチヤートである。 図中1は演算増幅器、2は比較器、3は鋸歯状
波電圧発生器、4はフリツプフロツプ、5,6は
アンド回路、5′,6′はナンド回路、7は負荷、
8,9はインバータ路、Tr1〜Tr4はトランジス
タ、Eは直流電源、T1,T2はトランス、Vrefは
参照電圧を示す。
FIG. 1 is a circuit diagram of a conventional switching regulator, FIG. 2, FIG. 3 is a time chart of waveforms at various parts in FIG. 1, and FIG. 4 is a circuit diagram of a switching regulator according to an embodiment of the present invention. The circuit diagram and FIG. 5 are time charts of waveforms at various parts in FIG. 4. In the figure, 1 is an operational amplifier, 2 is a comparator, 3 is a sawtooth voltage generator, 4 is a flip-flop, 5 and 6 are AND circuits, 5' and 6' are NAND circuits, 7 is a load,
8 and 9 are inverter paths, Tr 1 to Tr 4 are transistors, E is a DC power supply, T 1 and T 2 are transformers, and Vref is a reference voltage.

Claims (1)

【特許請求の範囲】[Claims] 1 一対の主スイツチング素子を交互にオン、オ
フ制御して出力電圧を安定化するスイツチングレ
ギユレータにおいて、該出力電圧と定格出力電圧
の基準となる参照電圧との誤差を負荷変動に対応
する電圧として演算増幅する演算増幅器と、該負
荷変動に対応する電圧とスイツチング動作周波数
の基準となる鋸歯状波電圧とを比較する比較器
と、該比較器の出力パルスを入力とし、互いに逆
相の一対の反転パルスを出力するフリツプフロツ
プ回路と、前記比較器の出力パルスと該一対の反
転パルスのそれぞれとの論理積を反転する一対の
ナンド回路と、該一対のナンド回路の出力パルス
をそれぞれ微分して前記比較器の負荷変動に対応
する電圧に帰還する一対の微分回路と、該一対の
ナンド回路の出力パルスをそれぞれ反転して一対
の駆動パルスを出力する一対のインバータ回路と
から構成されることを特徴とするスイツチングレ
ギユレータのパルス幅制御回路。
1. In a switching regulator that stabilizes the output voltage by alternately controlling a pair of main switching elements on and off, the error between the output voltage and the reference voltage, which is the standard for the rated output voltage, is adjusted to correspond to load fluctuations. An operational amplifier that performs operational amplification as a voltage, a comparator that compares the voltage corresponding to the load fluctuation with a sawtooth wave voltage that serves as a reference for the switching operating frequency, and a a flip-flop circuit that outputs a pair of inverted pulses; a pair of NAND circuits that inverts the AND of the output pulse of the comparator and each of the pair of inverted pulses; and a pair of NAND circuits that respectively differentiate the output pulses of the pair of NAND circuits. and a pair of inverter circuits that respectively invert the output pulses of the pair of NAND circuits and output a pair of drive pulses. A switching regulator pulse width control circuit featuring:
JP10333784A 1984-05-22 1984-05-22 Double pulse generation preventing system Granted JPS60249867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10333784A JPS60249867A (en) 1984-05-22 1984-05-22 Double pulse generation preventing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10333784A JPS60249867A (en) 1984-05-22 1984-05-22 Double pulse generation preventing system

Publications (2)

Publication Number Publication Date
JPS60249867A JPS60249867A (en) 1985-12-10
JPH0424952B2 true JPH0424952B2 (en) 1992-04-28

Family

ID=14351336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10333784A Granted JPS60249867A (en) 1984-05-22 1984-05-22 Double pulse generation preventing system

Country Status (1)

Country Link
JP (1) JPS60249867A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4764997B2 (en) * 2001-08-28 2011-09-07 富士電機株式会社 Switching power supply control circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5318696A (en) * 1976-08-04 1978-02-21 Ube Ind Ltd Novel aromatic polyamides
JPS5469714A (en) * 1977-11-15 1979-06-05 Nec Corp Power unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5318696A (en) * 1976-08-04 1978-02-21 Ube Ind Ltd Novel aromatic polyamides
JPS5469714A (en) * 1977-11-15 1979-06-05 Nec Corp Power unit

Also Published As

Publication number Publication date
JPS60249867A (en) 1985-12-10

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