JPH04249449A - Interprocessor communication control system - Google Patents

Abstract

PURPOSE:To reduce software's load in an interprocessor communication control system for sending and receiving information between processors via transmission lines. CONSTITUTION:This interprocessor communication control system provided with a processor 11 for generating and processing sending and receiving data to be sent and received in opposite to a processor connected to the processor 11 via transmission line for appropriately returning received data to the opposite processor is provided with a storage means 13 including a sending buffer and receiving buffer for respectively storing sending and receiving data, and having a port accessible in precedent to the processor 11, and a control means 15 for dividing an access cycle into two cycles for every stored word length to access the sending/receiving data via the port, successively transferring the content of the receiving buffer to the sending buffer in one access cycle, and successively sending/receiving the data between these buffers and the transmission line in the other access cycle.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-processor communication control system in which processors connected to a predetermined transmission line exchange information between opposing processors via the transmission line.

0002

[Prior Art] In a multiprocessor system in which functions and loads are distributed among multiple processors, various types of information are sent and received via serial data transmission lines provided between each processor, and each processor communicates with each other according to the information. Synchronization control between the two, process start/stop control, initialization, and other controls are performed. For example, in a system where a specific processor is the master processor and multiple other processors (slave processors) perform processing according to commands sent from the master processor, these processors are placed on a common serial data transmission path. Some systems employ a time division multiple access (TDMA) method in which different time slots are assigned to individual processors and information is directly exchanged between the master processor and each slave processor via the time slots.

FIG. 9 is a diagram showing an example of the configuration of a conventional processor connected to a serial data transmission path. In the figure,
A processor (CPU) 91 uses an address/data bus 9
2, a write/read memory (RAM) (hereinafter referred to as "RAM") that stores and holds predetermined information.
93, serial data transmission line 94 and address/data bus 9
2, and a direct memory access controller (DMAC) (hereinafter referred to as "direct memory access controller") that exchanges data between the RAM 93 and the communication interface section 95 instead of the processor 91 and the communication interface section 95 that provides a communication interface with the RAM 93 and the communication interface section 95.
It's called a "DMA controller." )96. The communication interface section 95 includes a reception port 97 that converts serial reception data received from the serial data transmission path 94 into serial and parallel data and sends it to the address/data bus 92, and a reception port 97 that converts the serial reception data received from the serial data transmission path 94 into parallel and serial data and sends the data to the address/data bus 92. and a transmission port 98 that sends out serial transmission data to a serial data transmission line 94. Further, the serial data transmission line 94 is connected to another processor as a communication partner.

[0004] In a processor having such a configuration, when starting a reception operation, the processor 91 sets predetermined control information and the address of the buffer area of the reception data located on the RAM 93 in the DMA controller 96 (FIG. 9). ), and issues a reception activation command to the reception port 97 (
Figure 9 ■). When the reception port 97 receives serial reception data of a predetermined length, it sequentially gives a reception completion signal to the DMA controller 96 (FIG. 9). In response to the completion signal, the DMA controller 96 stores the received data in the receive buffer area on the RAM 93 indicated by the above-mentioned set address ((2), (2) in the figure).

[0005] Furthermore, when transmitting data to the serial data transmission line 94, the processor 91 transmits the data to be transmitted to the RA.
The data is stored in a predetermined area on the M93 (Fig. 9■), and the address of the area and predetermined control information are set in the DMA controller 96 (Fig. 9■), and a transmission activation command is issued to the transmission port 98 (Fig. 9■). 9■). The transmission port 98 sends a transmission data transfer request signal to the DMA controller 96 in response to the activation command (FIG. 9). The DMA controller 96 transfers the transmission data from the transmission buffer area of the RAM 93 indicated by the above-mentioned set address to the transmission port 98 in response to the request signal (FIG. 9). The transmission port 98 sequentially converts the transmission data provided in this manner into serial transmission data and transmits the data.

[0006] A series of communication control processes accompanying such transmission and reception include, for example, polling operations depending on the communication method, and RNR (Receive Not Ready), which requests the opposing processor to suspend the transmission operation. Control information is also exchanged in the same way.

[0007]

[Problems to be Solved by the Invention] However, in a processor having such a conventional configuration, all data sent and received via the serial data transmission path 94 is transferred between the RAM 93 and the communication interface section 95 by the DMA controller 96. If the amount of data is large and the amount of data is large,
Since the address/data bus 92 is frequently occupied by the DMA transfer, it becomes an effective software load.

Further, when the processor 91 receives the control information, it analyzes it, sets the control information or the next transmission data according to the analysis result on the RAM 93, and performs the transmission activation process. The same process must be performed even when the received information (control information) is returned as is, which increases the load on the software.

Furthermore, in recent years, there have been many systems configured with many slave processors arranged under a single master processor, and the master processor in such systems has to face each slave processor to exchange information. Because of the large amount of data, the amount of processing associated with communication control occupies a large proportion of the amount of processing specific to the processor, causing a significant reduction in its throughput.

SUMMARY OF THE INVENTION An object of the present invention is to provide an inter-processor communication control system that can reduce the software load associated with communication control.

[0011]

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. The present invention provides an inter-processor communication control system that includes a processor 11 that generates and processes transmission/reception data that is exchanged with a processor connected via a transmission path, and that returns received data to the opposing processor as appropriate. , a storage means 13 including a transmission buffer and a reception buffer for respectively storing transmission and reception data, and having a port that can be accessed with priority over the processor 11;
Access is made by dividing the access cycle into two for each stored word length of the transmitted/received data through that port, and in one cycle the contents of the receive buffer are sequentially transferred to the transmit buffer, and in the other cycle these are Control means 15 for sequentially transmitting and receiving data between the buffer and the transmission path
It is characterized by having the following.

0012

[Operation] According to the present invention, the control means 15 takes in received data from the transmission path, stores it in the storage means 13 via its preferentially accessible port, and controls the access cycle for each storage word length of the received data as described above. In one of the divided cycles, the data is sequentially stored in the reception buffer. moreover,
The control means 15 sequentially transfers the contents of the reception buffer on the storage means 13 to the transmission buffer in the other cycle obtained by dividing the above-mentioned port access cycle into two for each stored word length.

That is, the processing of storing received data in the receiving buffer for each storage word length and the processing of transferring the contents of the receiving buffer to be returned to the transmitting buffer are carried out by the processor 1.
1 and the storage means 13 automatically by the control means 15, so that the processor 11
The software load associated with communication control is reduced.

[0014]

Embodiments Hereinafter, embodiments of the present invention will be described in detail based on the drawings. FIG. 2 is a diagram showing an embodiment of the present invention. In the figure, components having the same configuration and function as those shown in FIG. 9 are denoted by the same reference numerals, and their description will be omitted here.

The feature of the present invention is that, in place of the RAM 93, there is a first port that can be directly accessed from the processor 91, and a second port that responds preferentially to that port and that can be accessed under the same interface conditions. A receiving RAM 21 for storing received data and a transmitting RAM 21 for storing transmitted data are used.
AM22 is provided, and further, in place of the DMA controller 96, necessary components are provided for transmitting/receiving data and controlling transfer between these RAMs and the serial data transmission line 94 via the above-mentioned second port. A frame counter 23, a transmission pointer 24, a reception pointer 25, a transfer pointer 26, an address selector 27, a tristate buffer gate 28, and a latch circuit 29 are provided for control.

That is, the address/data bus 92 is
It is connected to the first ports of the reception RAM 21 and the transmission RAM 22, the transmission pointer 24, the reception pointer 25, the transfer pointer 26, and the verification circuit 30. On the other hand, receiving RAM2
1 and the second port of the transmission RAM 22, the data terminal of the reception RAM 21 is connected to the output of the serial/parallel conversion circuit 33, and is connected to the data terminal of the transmission RAM 22 and the parallel/serial conversion circuit 32 via the tri-state buffer gate 28. Connected to input. The input of the serial-to-parallel conversion means 33 is connected to the opposing processor via the upstream (downstream) line of the serial data transmission path 94, and is also connected to the verification data input of the verification circuit 30. The output of the parallel-to-serial conversion means 32 is connected to the opposing processor via a downlink (uplink) line of a serial data transmission line 94.

The lower address of the receiving RAM 21 is given from the frame counter 23 via the latch circuit 29, and the lower address of the transmitting RAM 22 is given directly from the frame counter 23. The upper address of the reception RAM 21 is given from the reception pointer 25 via the latch circuit 29,
The address is also given to the address terminal of the verification circuit 30. The upper address of the transmission RAM 22 is given via a selector 27 that selectively selects the outputs of the transmission pointer 24 and the transfer pointer 26.

The decoder 31 sends the signal TMG, which serves as a reference for the timing of completion of the transmission/reception operation, to the transmission pointer 24,
It is applied to the transfer pointer 26 and the verification circuit 30. Transmission pointer 24 provides a transmission completion interrupt signal to processor 91, transfer pointer 26 provides a transfer completion interrupt signal to processor 91, and verification circuit 30 provides a reception completion interrupt signal to processor 91. A decoder 31 that decodes the count value of the frame counter 23 outputs a read/write control signal (including a chip select signal) corresponding to the second port of the reception RAM 21 and the transmission RAM 22 and a parallel/serial conversion means according to the decoding result. 32, gives signals to the serial/parallel conversion means 33 and the selector 27 to determine their operating modes and timings.

A predetermined write control signal is given from the processor 91 to the transmission pointer 24, reception pointer 25, and transfer pointer 26. Note that write/read signals (including chip select signals) corresponding to the decoding results of the upper bits of the address/data bus 92 are applied to chip select terminals corresponding to the first ports of the reception RAM 21 and the transmission RAM 22.

By the way, regarding the correspondence between this embodiment and the block diagram shown in FIG.
corresponds to the storage means 13, and includes a frame counter 23, a transmission pointer 24, a reception pointer 25, a transfer pointer 26,
The selector 27, the verification circuit 30, the tristate buffer gate 28, the latch circuit 29, the decoder 31, the parallel/serial conversion circuit 32, and the serial/parallel conversion circuit 33 are connected to the control means 15.
corresponds to

In this embodiment, full-duplex TDMA is adopted as the inter-processor communication system, and four processors are arranged on the serial data transmission line 94. FIG. 3 is a diagram showing the frame structure of this embodiment. FIG. 4 is a diagram illustrating a buffer configuration on the reception RAM and a reference method thereof. FIG. 5 is an operation timing chart of the second port of the reception RAM.

The reception operation of this embodiment will be explained below with reference to FIGS. 2 to 5. As shown in FIG. 3, the data sent and received via the serial data transmission path 94 consists of four time slots fixedly assigned to each processor, and each time slot consists of 256-byte information. configured. The frame counter 23 performs a bit-by-bit counting operation for each frame according to such a frame configuration. The decoder 31 decodes the count value, and decodes the start of each frame (Fig. 3) and the start of the time slot (here, the third time slot TS2X) assigned to the processor 91 of the circuit of this embodiment. (Fig. 3), a timing signal corresponding to the reception of each bit of serial reception data (serial transmission data) constituting the time slot is generated. Here, the appended number "X" indicates the appended number corresponding to each frame.

When receiving serial reception data from the serial data transmission path 94, the processor 91 uses the reception RAM 2
Select an available receive buffer area located on 1 and set the value of the pointer indicating that area (for example, ``
axxx”. ) is set in the reception pointer 25 (FIG. 2 (2), FIG. 4 (2)), and the reception pointer 25 notifies the verification circuit 30 of the value. This set value is given to the second port of the receiving RAM 21 as an upper address (FIG. 2). The verification circuit 30 starts determining the validity/invalidity of the serial reception data received from the serial data transmission line 94 in the corresponding frame.

On the other hand, based on the above-mentioned counting operation, the frame counter 23 stores the received data in units of 1 byte (hereinafter referred to as "word length") in the reception RAM 21, for example. As an address, the lower 3 bits of the count value (corresponding to the word length)
(Fig. 2■, Fig. 4■). The decoder 31 gives the serial/parallel conversion means 33 the timing to take in the serially received data bit by bit (Fig. 2) according to the decoding result described above. Issue a write command (Fig. 2 ■). As shown by the dotted line in FIG. 4, the reception RAM 21 has reception buffer areas 411 to 411 corresponding to the upper and lower addresses given to the above-mentioned second port according to the command.
413, the parallel received data obtained from the serial/parallel conversion circuit 33 is sequentially stored (FIG. 4). The decoder 31 is
When the end of the frame (allocated time slot) is recognized after such received data storage operation is repeated for each word length, a timing signal TMG is sent to the verification circuit 30. The verification circuit 30 uses its timing signal TMG
If the logic level of all the bits received by the time ? is not constant, the data is determined to be valid, and a reception completion interrupt signal IRQn corresponding to the reception buffer area pointer notified at the start of reception is sent out. Here,"
n” is the used reception buffer area 411 to 413
This corresponds to the appended numbers “1” to “3”. In response to this interrupt signal, the processor 91 receives the corresponding reception R.
Process received data on AM21.

Furthermore, as shown in FIG. 5, the memory access cycle of the reception RAM 21 is divided into two parts for each word length (byte) (Fig. 5, ■, ■), and the storage operation of each word included in the received data is divided into two according to the word length (byte). This is performed at the timing after the final bit constituting the word is received (Fig. 5). Figure 6 shows the transmission RAM
It is a diagram showing the above buffer configuration and its reference method.

FIG. 7 is an operation timing chart of the second port of the transmission RAM. Below, Figure 2, Figure 6 and Figure 7
The transmission operation for the serial data transmission path 94 will be explained with reference to FIG. As shown in FIG. 6, the processor 91 selects an available one (here, referred to as a transmission buffer area 611) from among the transmission buffer areas 611 to 613 arranged in a predetermined size on the transmission RAM 22, and Store the data to be sent in that area. Furthermore, the processor 91 determines the value (=pxxx) of the pointer indicating the area.
is set in the transmission pointer 24 (Fig. 2■, Fig. 6■). This setting value is used as the upper address of the transmission RAM 22 (FIG. 2).

On the other hand, based on its counting operation, the frame counter 23 calculates, for example, when the word length of the sending RAM 22 is the same as that of the receiving RAM 21, the lower 3 bits ( (corresponding to the word length).
22 (Figure 2■, Figure 6■). The decoder 31 recognizes the above-mentioned word length break according to the decoding result, and issues a command to read the transmission data to the transmission RAM 22 (FIG. 2). As shown by the dotted line in FIG. 6, the transmission RAM 22 sequentially reads the transmission data from the transmission buffer areas 611 to 613 corresponding to the upper and lower addresses given to the second port (FIG. 4), and converts the data to the parallel-to-serial conversion circuit. Give to 32. The parallel-to-serial conversion circuit 32 sends out the transmission data bit by bit to the serial data transmission line 94 in accordance with the control signal ((2) in FIG. 2) given from the decoder 31. Further, when the read operation of the transmission data is repeated for the time slot length (=256 bytes), the decoder 31 recognizes the end of the frame (the allocated time slot) and sends the timing signal TMG to the transmission pointer 24. . In response to the timing signal TMG, the transmission pointer 24 sends out a transmission completion interrupt signal IRQn corresponding to the transmission buffer area set at the start of transmission. Here,
"n" is the used reception buffer area 411 to 41
3 corresponds to the appended numbers "1" to "3". In response to this interrupt signal, processor 91 recognizes the completion of transmission of the corresponding transmission data.

Furthermore, the memory access cycle of the transmission RAM 22 is divided into two parts (■, ■) in FIG. ) is performed at the timing immediately after it is given (Fig. 7 ■). By the way, in the processing activated in response to the above-mentioned reception completion interrupt IRQn, the processor 91 analyzes the received data and performs the necessary processing, and then stores a predetermined value in the interrupt request release register corresponding to the interrupt request. Write control word.

FIG. 8 is a diagram showing the configuration of the interrupt request release register. In the figure, when viewed from the processor 91, the interrupt request release register is composed of separate areas corresponding to each receive buffer area, but physically it is distributed and overlapped in the transfer pointer 26 and verification circuit 30. Ru. The control word to be written is the return control bit placed in the most significant bit D7 and its lower bit D6.
It consists of the transfer pointer value located at ~D0.

The operation of transferring received data as is to the transmission RAM and returning it to the opposing processor will be described below with reference to FIGS. 2 to 8. The verification circuit 30 responds to the write operation to the interrupt request release register described above.
It simply restores the corresponding interrupt signal to its inactive level. In the transfer pointer 26, when the logic of the return control bit is "0", it recognizes that there is no need to return the corresponding received data and does not set any new pointer value, but when the logic of the return control bit is "1" and the transfer pointer value given at the same time (in the example shown in FIG. 8, "00000
01'') (Fig. 6 ■). At this time, since the set value of the reception pointer 25 is held at the same value as at the start of reception, the decoder 31 transfers the data to be returned to the reception RA.
In order to transfer data from M21 to transmission RAM 22, a predetermined control signal is sent to each part.

For example, if the control word "10000001" is written to the interrupt request release register in response to the reception completion interrupt signal IRQ1 given at the timing shown in FIG. Starting from the timing (■ in Figure 3), the upper address given from the reception pointer 25 and the frame counter 2
According to the lower address given from 3, the receiving RAM
21 is specified with the same address as in the reception operation in the previous frame, and the received data is read out sequentially (Fig. 5 ■)
. The tri-state buffer gate 28 is set to the tri-state state alternately with the serial-to-parallel conversion circuit 33 in response to the memory cycles of the reception RAM 21 which are divided into two (■, ■ in FIG. 5). The data given to the transmission RAM is switched between the two.

In the transmission RAM 22, as shown in FIG.
In conjunction with such a read operation of the reception RAM 21, the transmission buffer corresponding to the transfer pointer value indicated by the above-mentioned control word is The received data sequentially read out from the receiving RAM 21 is written and held in the area 611 (FIG. 7). Note that the upper address given to the transmission RAM 22 is given via the selector 27, and as shown in FIGS. The output of the pointer 24 and the output of the transfer pointer 26 are alternately switched.

Processor 91 transfers the data to be returned from reception RAM 21 to transmission RAM 2 according to the above-described procedure.
The transfer pointer 26
The completion of the transfer operation is recognized in response to the transfer completion interrupt signal output from the transfer completion interrupt signal. Note that this interrupt signal is
In the processor 91, the reception RAM 21 used at the time of transfer
Since the buffer areas of the buffer area and the transmission RAM 22 are self-explanatory, there is only one buffer area.

By the way, such a transfer operation of received data from the reception RAM 21 to the transmission RAM 22 is performed in the reception RAM 21 in the first half of the memory cycle (FIG. 5), and in the transmission RAM 22 in the second half of the memory cycle (FIG. 7). ). The latch circuit 29 matches the timing of serial reception data and serial transmission data on the serial data transmission path, and enables cascade connection of the serial data transmission path without using a frame aligner (phase corrector).
The address is given to the reception RAM 21 after being delayed by the above-mentioned timing difference (time corresponding to 0.5 bits).

Furthermore, the write signal (
Figure 7 ■) is the return control bit (
= 1) is generated corresponding to the time slot allocated to the processor 91 in the next frame (
Figure 7 ■). Note that the readout signal of the reception RAM 21 (Fig. 5
(2) can be generated by the same method as the write signal of the transmission RAM 22, but the active level may be continuously given during the time slot allocated to the processor 91 according to the output of the decoder 31.

As described above, according to this embodiment, the transmission/reception operations via the serial data transmission path and the block transfer operations between the transmission/reception buffers associated with the return of received data are performed as follows:
Since this is performed using dedicated hardware and without occupying the address/data bus of the processor, the software load associated with communication control of inter-processor communication is reduced. Note that in this embodiment, the reception buffer areas 411 to 412
Regarding acquisition processing of empty areas among the transmission buffer areas 611 and 612, in principle, excluding the buffer areas corresponding to pending reception interrupt requests and transmission interrupt requests, for example, regarding the reception buffer area, the reception buffer Area 411 →412 →
413, but the method is not limited to this method; for example, the method of acquiring and selecting transmitting and receiving buffer areas is as follows: Depending on the number of pages, responsiveness, maintainability, etc., for example, a cyclic selection method may be adopted. However, the determination of the transmission buffer area to which the return data is to be transferred and other matters are performed with priority given to the selection by the processor 91.

In addition, in this embodiment, the return data is transmitted
When transferring data to the AM 22, the upper address of the receiving RAM 21 is given from the output of the receiving pointer 25, but when receiving other serially receiving data in parallel with this transfer operation, the transmitting buffer that stores the returned data is A register that holds a pointer value indicating an area may be added, and a selector may be added that works in conjunction with the selector 27 to switch between the output of the added pointer and the output of the reception pointer 25.

Furthermore, from the reception RAM 21 to the transmission RAM 2
The timing at which the return data is transferred to the processor 2 is not limited to the time slot assigned to the processor 91 in the next frame. good. Further, although this embodiment is an example of inter-processor communication using TDMA, the communication method is not limited to this, and the present invention is also applicable, for example, to a case where two processors communicate face-to-face. Furthermore, the configuration of the transmission path is not limited to this embodiment, and may also be applied to a case where it is formed in a ring shape, for example.

[0039]

As explained above, in the present invention, the process of storing received data in the receive buffer and the process of setting the return data stored in the receive buffer in the transmit buffer can be performed by accessing the storage means in parallel with the processor. Since this can be done automatically by the control means through possible individual ports, the software load associated with communication control on the processor is reduced.

[0040] Therefore, the responsiveness in inter-processor communication can be improved, and the throughput of the processors can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing a frame configuration of this embodiment.

FIG. 4 is a diagram illustrating a buffer configuration on a reception RAM and a reference method thereof.

FIG. 5 is an operation timing chart of the second port of the reception RAM.

FIG. 6 is a diagram illustrating a buffer configuration on a transmission RAM and a reference method thereof.

FIG. 7 is an operation timing chart of the second port of the transmission RAM.

FIG. 8 is a diagram showing the configuration of an interrupt request release register.

FIG. 9 is a diagram showing an example of the configuration of a conventional processor connected to a serial data transmission line.

[Explanation of symbols]

11 Processor 13 Storage means 15 Control means 21 Reception RAM 22 Transmission RAM 23 Frame counter 24 Transmission pointer 25 Reception pointer 26 Transfer pointer 27 Selector 28 Tri-state buffer gate 29 Latch circuit 30 Verification circuit 31 Decoder 32 Parallel-to-serial conversion circuit 33 Serial-to-parallel conversion Circuits 411 to 413 Receive buffer areas 611 to 6
13 Transmission buffer area 91 Processor (CP
U) 92 Address/data bus 93 Write/read memory (RAM) 94
Serial data transmission line 95 Communication interface unit 96 DMA controller (DMAC) 97 Reception port 98 Transmission port

Claims (1)

[Claims] 1. A processor (11) that generates and processes transmission/reception data that is exchanged facing a processor connected via a transmission path, and returns the received data to the facing processor as appropriate. In the inter-processor communication control system, a storage means (13) including a transmission buffer and a reception buffer for respectively storing the transmission and reception data and having a port that can be accessed with priority over the processor (11); The access cycle is divided into two for each stored word length of the transmitted/received data, and in one cycle, the contents of the receive buffer are sequentially transferred to the transmit buffer, and in the other cycle, these are An inter-processor communication control system comprising: a control means (15) for sequentially transmitting and receiving the transmission/reception data between a buffer and the transmission path.