JPH0424860A - Controlling system for synchronization of plural processors - Google Patents

Abstract

PURPOSE:To simplify the synchronization processing among processors without forcing the load to a control program by providing a clock switch circuit between plural processors and their clocks, and switching these clocks in the synchronization processing. CONSTITUTION:When a processing request is given to a processor 1 from another processor 1, a clock switch instruction signal is informed to a clock switch circuit 2. Then the circuit 2 works to supply the clock 3 of either one of both processors to them in common. Thus both processors 1 performs their processing synchronously with each other. That is, the circuit 2 is provided between the processors 1 and their clocks 3 and these clocks 3 are switched for execution of the synchronization processing. Thus the synchronization processing is simplified among processors 1 without forcing the load to a control program.

Description

[Detailed Description of the Invention] [Summary] Synchronous control method for synchronously controlling multiple processors A clock switching circuit is provided between multiple processors and the clocks of each processor, and the clocks are switched and controlled when performing synchronous processing. The purpose is to easily perform synchronization processing between processors without imposing a burden on the program, and a clock switching circuit is provided between multiple processors and each clock of these multiple processors, so that the synchronization processing from one processor to another can be easily performed. At the time of a processing request, a clock switching instruction signal is notified to the clock switching circuit, the clock of one processor or another processor is switched to be commonly supplied to both processors, and the processing is performed synchronously.

[Industrial application field]

The present invention relates to a synchronous control method for synchronously controlling multiple processors.

[Prior art and problem to be solved by the invention: Conventionally, as shown in No. 50, in a system including a plurality of processors P + , P z . When P makes a processing request to processor P2 and uses a timer to monitor timeouts, the clocks of the two processors are different by 2, so the clock of the processor P2 receiving the processing request is based on 2. Timeout monitoring must be performed. If this was done by software in the processor P1 on the requesting side, the control program would become complicated, and furthermore, each time a request is made to a processor with a different clock, the MM? There was a problem in that the Wj program had to be changed.

The present invention provides a clock switching circuit between a plurality of processors and the clocks of each processor, switches the clocks when performing synchronization processing, and easily performs synchronization processing between processors without imposing a burden on a control program. The purpose is to

[Means to solve problems]

FIG. 1 shows the basic structure of the present invention.

In FIG. 1, processors 1 each have their own clock 3.

The clock switching circuit 2 is a circuit provided between the plurality of processors 1 and the clock 3 of each processor 1 to switch the clocks.

Clock 3 is a clock supplied to each processor 1.

[Effect]

As shown in FIG. 1, the present invention provides a clock switching circuit 2 when a processor 1 requests processing from another processor
A clock cutoff instruction signal is notified to the processor 1, and the clock 3 of one processor 1 or another processor 1 is switched to be commonly supplied to both processors 1, so that processing is performed synchronously.

Therefore, by providing a clock switching circuit 2 between a plurality of processors 1 and the clock 3 of each processor 1 and switching the clock 3 when performing synchronization processing, the processors can be synchronized without imposing a burden on the control program. It becomes possible to perform processing easily.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be explained in detail using FIGS. 1 to 4.

In FIG. 1, processors 1 each have their own clock 3. Here, processors P+, Pz...PR have clocks KI-Kz
...They each have Kll as a basic clock and operate.

The clock switching circuit 2 is a circuit that is provided between the plurality of processors 1 and the clock 3 of each processor 1 to switch the clock, and normally the clock switching circuit 2 is a circuit that is provided between the plurality of processors 1 and the clock 3 of each processor 1 and switches the clock.
The clocks K + , K z . . . , K are supplied to P and 1 as basic clocks, respectively. Based on the clock switching instruction signal, the instructed clocks K + , K z
. . K, , is supplied to the designated processor 1.

Next, under the configuration in Figure 2, processor P operates with a clock of 2, processor P2 operates with a clock of 2, and processor P operates with a clock of 1/2 times the period of 2. (i.e., the clock has one period of time T3, the clock has 2
TI X2 = 72), the second time in the order of the flowchart in Figure 3,
This will be explained in detail using FIG. Here, a case will be described in which processor P executes process A, requests process B to processor P2, monitors time-over, receives the result of process B, and executes process C.

In FIG. 3, ■ marks the end of process A. This means that the processor P1 ends the execution of the process A with a clock of 1 (the execution of the process A in FIG. 4 ends).

(2) relies on the processor P2 to perform processing B;

0 sets timer 4.

(2) Processor P2, which received the request for processing B in (2), notifies the clock switching circuit 2 that the clock switching instruction signal is ON, and (3) changes the clock supplied to processor P1 from (basic clock of processor P1) to the clock switching circuit 2. The clock is switched to the clock Kg (the basic clock of the processor P2) (to the clock switched at the position (■) in FIG. 4).

(2) starts processing B at clock 2 (basic clock of processor P2) (processing day in FIG. 4).

O ends processing B. Then, the processor P2 notifies the processor P of the completion notification together with the result.

[Phase] returns 2 to the clock to the clock, which returns 2 to the clock to the clock, as shown at +' to the clock at the position of Figure 4.

(2) is executed using process C as a clock. .

In addition, a timeout occurs in [phase]. this is,[
In the state in which the clock is switched from 1 to 2 in [phase], the timer 4 in FIG. 2 counts 2 to the clock, and 0 indicates that the set time has exceeded (time-over).

In this case, processor P2 is regarded as abnormal, and abnormality processing is performed.

As described above, processor P1 performs processing B on processor P
In response to the request to 2, the processor P2 notifies the clock switching circuit 2-1 of a clock switching instruction signal, and also supplies 2 to its own operating clock to the processor P1 that monitors the timer. By operating the clock at 2, it is possible to perform correct timer monitoring in a so-called synchronized state.

FIG. 4 shows a time chart according to the present invention.

Here, clock represents the basic tarock supplied to processor P.

The clock 2 represents the basic tarok supplied to processor P2.

For 1° to the clock, follow the flowchart in Figure 3.
Represents the clock supplied to processor P+.

The clock switching instruction signal represents a signal that the processor P notifies the clock switching circuit 2-1.

The time difference represents a change in the time difference due to the clock K supplied to the processor Pl.

The processing includes processing A (processor Pl), processing B (processor P2), which are executed by processor P1 and processor P2.
Represents processing C (processor Pl).

Here, ■ represents the position where the clock supplied to the processor P1 is switched from clock to clock 2 in the third time ■.

3 represents the position where the clock supplied to the processor P1 is switched from clock 2 to clock 1 in FIG. 3@.

〔Effect of the invention〕

As explained above, according to the present invention, the clock switching circuit 2 is provided between the plurality of processors 1 and the clock 3 of each processor 1, and when performing synchronization processing, the clock switching circuit 2 is provided between the plurality of processors 1 and the clock 3 of each processor 1.
Processor 1, which operates on its own basic clock,
When performing processing in synchronization with processors 1 that operate with different basic clocks, the synchronization processing between the processors can be easily performed without imposing a burden on the control program.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the principle configuration of the present invention, Fig. 2 is an explanatory diagram of the configuration of one embodiment of the present invention, Fig. 3 is a flowchart explaining the operation of the present invention, Fig. 4 is a time chart according to the present invention, Fig. 5 shows an explanatory diagram of the prior art. In the figure, ■ represents a processor, 2 represents a clock switching circuit, and 3 represents a clock.

Claims (1)

[Claims] In a synchronous control method that performs synchronous control of a plurality of processors, a plurality of processors (1) and a plurality of processors (1)
) clock switching circuit (2) between each clock (3) of
When a processor (1) requests processing from another processor (1), it notifies the clock switching circuit (2) of a clock switching instruction signal, and changes the clock of the processor (1) or the other processor (1). (3) is switched to be commonly supplied to both processors (1), and processing is performed synchronously.