JPH0424858B2 - - Google Patents

Info

Publication number
JPH0424858B2
JPH0424858B2 JP60163396A JP16339685A JPH0424858B2 JP H0424858 B2 JPH0424858 B2 JP H0424858B2 JP 60163396 A JP60163396 A JP 60163396A JP 16339685 A JP16339685 A JP 16339685A JP H0424858 B2 JPH0424858 B2 JP H0424858B2
Authority
JP
Japan
Prior art keywords
lsi
base material
film carrier
film base
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60163396A
Other languages
Japanese (ja)
Other versions
JPS6223124A (en
Inventor
Koki Taniguchi
Nobuhiko Myazaki
Nobutaka Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP16339685A priority Critical patent/JPS6223124A/en
Publication of JPS6223124A publication Critical patent/JPS6223124A/en
Publication of JPH0424858B2 publication Critical patent/JPH0424858B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/361—Assembling flexible printed circuits with other printed circuits

Description

【発明の詳細な説明】 ＜技術分野＞ 本発明はテープに一定ピツチでLSIを搭載して
なるフイルムキヤリアLSIに関するものである。[Detailed Description of the Invention] <Technical Field> The present invention relates to a film carrier LSI in which LSIs are mounted on a tape at a constant pitch.

＜従来技術＞ 従来のフイルムキヤリアLSIは、たとえば第６
図に示すように構成されている。すなわち、１は
ポリエステルあるいはポリイミド等のフイルム基
材、２はLSI検査用パツド、３はスリツト（又は
透孔）、４はカツトライン、５はスプロケツト用
の穴、６はLSIモールド部、７はLSIリード端子
部を示し、前記カツトライン４のところで切断し
てフイルム基材１からLSI素子を分離するように
形成されている。<Prior art> Conventional film carrier LSI, for example,
It is configured as shown in the figure. That is, 1 is a film base material such as polyester or polyimide, 2 is an LSI inspection pad, 3 is a slit (or through hole), 4 is a cut line, 5 is a hole for a sprocket, 6 is an LSI mold part, and 7 is an LSI lead. The terminal portion is shown and is formed so as to be cut at the cut line 4 to separate the LSI element from the film base material 1.

しかしながら、上記従来の場合はLSI素子を分
離したとき、スリツト（又は透孔）３のために
LSI素子の全てのリード端子はフイルム基材１の
端部から突出した状態となり、このためリード端
子のフアインピツチ化に伴つて端子間並びに端子
幅が非常に狭くなつた場合に、リード端子のフオ
ーミング時に切断し易くなり、かつリード端子の
半田付が著しく困難となるとともに、リード端子
が曲り易く工程でのハンドリングが困難になると
いう大きな問題を有していた。 However, in the above conventional case, when the LSI element is separated, the slit (or through hole) 3
All the lead terminals of the LSI device protrude from the edge of the film base material 1. Therefore, when forming the lead terminals, when the distance between the terminals and the width of the terminals become extremely narrow due to the fine pitch of the lead terminals. This has had major problems in that it becomes easy to cut, it becomes extremely difficult to solder the lead terminals, and the lead terminals are easy to bend, making handling in the process difficult.

＜目的＞ 本発明はかかる従来の問題点に鑑みて成された
もので、フイルム基材上のLSI素子のリード端子
に対向する領域を透孔を有する部分と透孔を有し
ない部分とに分けることにより、上記従来のフア
インピツチに伴なう問題点を解消することができ
るとともに、リード端子を大電流端子として又接
続にあたつて圧着できないような場合にも対処す
ることができるフイルムキヤリアLSIを提供せん
とするものである。<Purpose> The present invention has been made in view of such conventional problems, and it divides the area facing the lead terminal of an LSI element on a film base material into a part with a through hole and a part without a through hole. By doing so, we have developed a film carrier LSI that can solve the problems associated with the conventional fine pitch mentioned above, and can also handle cases where lead terminals can be used as high current terminals and cannot be crimped for connection. This is what we intend to provide.

＜実施例＞ 以下図にもとづいて本発明を詳細に説明する。<Example> The present invention will be explained in detail below based on the drawings.

第１図は本発明に係るフイルムキヤリアLSIの
平面図である。 FIG. 1 is a plan view of a film carrier LSI according to the present invention.

図において、１はポリイミド若しくはポリエス
テル等からなるフイルム基材、２はLSI検査用パ
ツド、３はフイルム基材１に設けた透孔であり、
この透孔は図中左側の端子間と端子幅とが比較的
広く形成されたリード端子群７−１に対向して設
けられている。４はカツトライン、５はフイルム
基材１を搬送するスプロケツトの爪に嵌り込む
穴、６はLSI素子のモールド部である。また７−
２はフアインピツチ化したもう一方のリード端子
群であり、このリード端子群７−２に対向するフ
イルム基材上の部分には上記したようなスリツト
（又は透孔）は設けられていない。すなわち、こ
のフイルムキヤリアLSIはカツトライン４のとこ
ろで切断したとき、リード端子群７−１の方はフ
イルム基材１の端部から突出し、今一つのリード
端子群７−２の方はフイルム基材１に一体化され
るように考慮されている。 In the figure, 1 is a film base material made of polyimide or polyester, etc., 2 is an LSI inspection pad, 3 is a through hole provided in the film base material 1,
This through hole is provided facing the lead terminal group 7-1 on the left side of the figure, in which the distance between the terminals and the terminal width are relatively wide. 4 is a cut line, 5 is a hole into which a pawl of a sprocket for conveying the film base material 1 is fitted, and 6 is a molded portion of the LSI element. Also 7-
Reference numeral 2 designates the other fine pitched lead terminal group, and the portion on the film base material facing this lead terminal group 7-2 is not provided with the above-mentioned slits (or through holes). That is, when this film carrier LSI is cut at the cut line 4, the lead terminal group 7-1 protrudes from the end of the film base material 1, and the other lead terminal group 7-2 protrudes from the film base material 1. It is designed to be integrated.

次に上記したフイルムキヤリアLSIの使用例に
ついて説明する。 Next, a usage example of the film carrier LSI described above will be explained.

第２図は本発明のフイルムキヤリアLSIをLCD
ドライバーとして使用した例、第３図はその断面
図である。 Figure 2 shows the film carrier LSI of the present invention on an LCD.
FIG. 3 is a sectional view of an example in which the device is used as a driver.

図中、８は液晶表示セル、９はフイルムキヤリ
アLSI（セグメント側）、１０はプリント配線基
板、１１はフイルムキヤリアLSI（コモン側）、１
２は有機フレキシブルEL１６の電極コネクター、
１３は同ELのシール部、１４は同ELの発光部、
１５は同ELの挿入用ガイドレールであり、この
例ではフイルムキヤリアLSIの幅及び間隔共に広
く形成され且つフイルム基材から突出したリード
端子群７−１はプリント配線基板１０の端子部に
半田付され、また他方のリード端子７−２は図に
示す如くフオーミングし、フアインピツチ化され
た液晶表示セル８の接続端子に金属粒子を含んだ
ヒートシール材で接続することが出来る。 In the figure, 8 is a liquid crystal display cell, 9 is a film carrier LSI (segment side), 10 is a printed wiring board, 11 is a film carrier LSI (common side), 1
2 is the organic flexible EL16 electrode connector,
13 is the seal part of the same EL, 14 is the light emitting part of the same EL,
Reference numeral 15 denotes a guide rail for inserting the EL, and in this example, the lead terminal group 7-1, which is formed wide in both width and spacing of the film carrier LSI and protrudes from the film base material, is soldered to the terminal part of the printed wiring board 10. The other lead terminal 7-2 can be formed as shown in the figure and connected to the connection terminal of the finely pitched liquid crystal display cell 8 using a heat sealing material containing metal particles.

すなわち、まずリード端子群７−２の方をフオ
ーミングして液晶表示セル８に接続したのち、リ
ード端子群７−１の方をストローク調整し圧力が
余りかからないようにした治具又は平付にてプリ
ント配線基板１０の端子に半田接続する。この場
合、リード端子群７−１はフイルム基材１の端部
から突出しているので熱の伝わりが良く、このた
め液晶及びELに大きな圧力を加えることなく接
続可能である。なお、１７は裏側偏光板、１８は
表側偏光板である。 That is, first, the lead terminal group 7-2 is formed and connected to the liquid crystal display cell 8, and then the lead terminal group 7-1 is formed with a jig or a flat plate with stroke adjustment so as not to apply too much pressure. Solder connection to the terminals of the printed wiring board 10. In this case, since the lead terminal group 7-1 protrudes from the end of the film base material 1, heat conduction is good, and therefore connection can be made without applying large pressure to the liquid crystal and EL. Note that 17 is a back side polarizing plate, and 18 is a front side polarizing plate.

第４図は有機フレキシブルELを有しない反射
型のLCDに使用した例であり（第５図は第４図
の断面図）、図中８−１は表側LCDガラス、 ８−２は裏側LCDガラス、１９は接着剤を示し、
特にフイルムキヤリアLSI９，１１の接続方法は
前述の例と同じである。 Figure 4 shows an example of a reflective LCD that does not have an organic flexible EL (Figure 5 is a cross-sectional view of Figure 4). In the figure, 8-1 is the front LCD glass, and 8-2 is the back LCD glass. , 19 indicates adhesive;
In particular, the method of connecting the film carrier LSIs 9 and 11 is the same as in the previous example.

＜効果＞ 以上詳細に説明したように、本発明のフイルム
キヤリアLSIはフイルム基材上のLSI素子のリー
ド端子に対向する領域を透孔を有する部分と透孔
を有しない部分とに分けて成るから次のような効
果を奏することが出来る。<Effects> As explained in detail above, the film carrier LSI of the present invention has a region on the film base material facing the lead terminals of the LSI element divided into a portion having a through hole and a portion having no through hole. The following effects can be achieved.

(イ) 接続すべき部分の端子がフアインピツチであ
るにもかかわらず接続が容易である。(a) Connection is easy even though the terminals of the parts to be connected are finely pitched.

(ロ) 工程でのリード端子のハンドリングが容易で
きる。(b) Lead terminals can be easily handled during the process.

(ハ) リード端子のフオーミングが容易である。(c) Forming of lead terminals is easy.

(ニ) リード端子の修理が容易である。(d) Lead terminals are easy to repair.

(ホ) 大電流端子として、又半田付によつて圧力を
加えることなく接続することが出来る。(e) Can be connected as a high current terminal or by soldering without applying pressure.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明に係るフイルムキヤリアLSIの
平面図、第２図は本発明フイルムキヤリアLSIを
LCDドライバーとして使用した例を示す図、第
３図は第２の断面図、第４図は本発明フイルムキ
ヤリアLSIを反射型LCDに使用した例を示す図、
第５図は第４図の断面図、第６図は従来のフイル
ムキヤリアLSIの平面図である。 １はフイルム基材、２はLSI検査用パツド、３
はスリツト（透孔）、４はカツトライン、６は
LSIモールド部、７−１，７−２はリード端子。 FIG. 1 is a plan view of a film carrier LSI according to the present invention, and FIG. 2 is a plan view of a film carrier LSI according to the present invention.
FIG. 3 is a second sectional view, and FIG. 4 is a diagram showing an example in which the film carrier LSI of the present invention is used in a reflective LCD.
FIG. 5 is a sectional view of FIG. 4, and FIG. 6 is a plan view of a conventional film carrier LSI. 1 is a film base material, 2 is a pad for LSI inspection, 3
is a slit (hole), 4 is a cut line, 6 is a
LSI mold part, 7-1 and 7-2 are lead terminals.

Claims (1)

【特許請求の範囲】 １ フイルム基材上に集積回路（LSI）素子を搭
載したフイルムキヤリアLSIに於て、 前記フイルム基材上の前記集積回路（LSI）素
子のリード端子に対向する領域を透孔を有する部
分と透孔を有しない部分とに分けて成ることを特
徴とするフイルムキヤリアLSI。[Claims] 1. In a film carrier LSI in which an integrated circuit (LSI) element is mounted on a film base material, a region facing the lead terminal of the integrated circuit (LSI) element on the film base material is transparent. A film carrier LSI characterized by being divided into a part with holes and a part without holes.
JP16339685A 1985-07-23 1985-07-23 Film carrier lsi Granted JPS6223124A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16339685A JPS6223124A (en) 1985-07-23 1985-07-23 Film carrier lsi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16339685A JPS6223124A (en) 1985-07-23 1985-07-23 Film carrier lsi

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP6170682A Division JP2509804B2 (en) 1994-07-22 1994-07-22 Display device

Publications (2)

Publication Number Publication Date
JPS6223124A JPS6223124A (en) 1987-01-31
JPH0424858B2 true JPH0424858B2 (en) 1992-04-28

Family

ID=15773092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16339685A Granted JPS6223124A (en) 1985-07-23 1985-07-23 Film carrier lsi

Country Status (1)

Country Link
JP (1) JPS6223124A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0712972Y2 (en) * 1987-02-13 1995-03-29 セイコーエプソン株式会社 Liquid crystal device
JPH0915355A (en) * 1995-07-03 1997-01-17 Toshiba Home Technol Corp Device with timer

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54124675A (en) * 1978-03-22 1979-09-27 Matsushita Electric Ind Co Ltd Semiconductor device and its mounting method
JPS5753951A (en) * 1980-09-17 1982-03-31 Hitachi Ltd Assembling method of semiconductor device
JPS59119477A (en) * 1982-12-27 1984-07-10 Omron Tateisi Electronics Co Transaction processor
JPS59159553A (en) * 1983-03-01 1984-09-10 Matsushita Electric Ind Co Ltd Film carrier
JPS59210419A (en) * 1983-05-13 1984-11-29 Seiko Epson Corp Liquid crystal display body device
JPS616832A (en) * 1984-06-20 1986-01-13 Matsushita Electric Ind Co Ltd Material to be loaded

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58188684U (en) * 1982-06-10 1983-12-15 セイコーエプソン株式会社 electronic display device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54124675A (en) * 1978-03-22 1979-09-27 Matsushita Electric Ind Co Ltd Semiconductor device and its mounting method
JPS5753951A (en) * 1980-09-17 1982-03-31 Hitachi Ltd Assembling method of semiconductor device
JPS59119477A (en) * 1982-12-27 1984-07-10 Omron Tateisi Electronics Co Transaction processor
JPS59159553A (en) * 1983-03-01 1984-09-10 Matsushita Electric Ind Co Ltd Film carrier
JPS59210419A (en) * 1983-05-13 1984-11-29 Seiko Epson Corp Liquid crystal display body device
JPS616832A (en) * 1984-06-20 1986-01-13 Matsushita Electric Ind Co Ltd Material to be loaded

Also Published As

Publication number Publication date
JPS6223124A (en) 1987-01-31

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