JPH0424839A - Fault processing system - Google Patents

Abstract

PURPOSE:To evade the hang-up of a central processor (SU) when a busy state is hung-up due to a fault caused in an additional device by starting the processing of an interruption of the SU after the processing is through with the additional device and a signal showing a processing mode is turned off. CONSTITUTION:An additional device VU which carries out an exclusive instruction received from an SU owns a signal (1) showing a processing mode. The interruption processing of the SU is started after the processing is through with the VU and the signal (1) is turned off. A hang-up detecting timer contained in the SU detects a time-out state of the busy signal (1) sent from the VU. Then an instruction is given to clear the VU and forcibly drop out the busy signal (1) when the time-out state is detected. At the same times, the SU starts the machine check interruption processing regardless of the signal (1). Thus the hang-up of the SU can be evaded.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology and Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Working Examples Effects of the Invention [Summary] Center It has a processing unit (SU) and an additional unit (VU) that is attached to the central processing unit (SU) and executes a dedicated instruction transferred from the central processing bag (SO).
U) has a signal ■ indicating that processing is in progress, and the central processing unit (
The SU) interrupt relates to a failure handling method in an information processing system in which the interrupt processing is controlled to start after waiting for the processing of the additional unit (VU) to be completed and the signal ■ indicating that the processing is in progress is turned off. The purpose of this is to prevent the central processing unit (SU) from hanging up when a failure occurs in the additional unit (VU) and the busy state hangs up. , a means for monitoring the processing completion waiting time of the additional device (VU), and a means for forcibly generating a signal (■) indicating that the processing of the additional device (VU) is in progress when the processing completion waiting time of the additional device (VU) times out. and a means for forcibly starting the machine check interrupt processing when the wait time for processing completion of the additional device F (VU) times out, so that when a failure occurs in the additional device (VU), Signal indicating that the above processing is in progress■
When the time monitoring means detects that the VU has hung up and timed out, the additional device (VU) is forcibly disconnected.
) to cause the central processing unit (SU) to enter interrupt processing.

[Industrial application field]

The present invention provides a central processing unit (SO) and a central processing unit (SO).
Central processing bag added to SU)? ! Additional equipment that executes dedicated instructions transferred from f (SU)! (VU), the additional device (VU) has a signal ■ indicating that processing is in progress, and interrupts from the central processing unit (SO) are handled by the additional device (VU).
A fault handling method in an information processing system that is controlled to start interrupt processing after waiting for the processing in progress (U) to be completed and the signal (■) indicating that the processing is in progress is turned off, especially when there is a fault in the additional unit (VU). The present invention relates to a processing method for avoiding hang-up of a central processing unit (SU) when a busy state hangs up due to occurrence of a problem.

In recent years, supercomputers consisting of a scalar unit (SO) and a vector unit (VU) have been used in a multiprocessing environment.
In parallel with jobs that perform vector operations in the VU), many users also run general jobs that do not perform vector operations (does not include vector instructions) in the above-mentioned scalar unit (SU). (VU)
A failure in which the busy signal indicating that the vector unit (VU) is being processed does not turn off
), the scalar unit (SO) requires at least a processing method that can continue to process the above-mentioned general jobs.

[Prior art and problems to be solved by the invention] Figure 2 is a diagram showing an example of the configuration of a supercomputer;
The figure is a time chart of vector instruction processing in a supercomputer, and FIG. 4 is a diagram showing an example of a conventional failure handling circuit.

A supercomputer capable of processing vector operations at high speed has a central processing unit 1 called a scalar unit (hereinafter referred to as SU) and a vector processing unit 2 called a vector unit (hereinafter referred to as VU).

SO1 can be used as a standalone computer for normal calculation processing, but
When a dedicated instruction for vector operations is read out, it is transferred to the VU 2 and processed by the VU 2. An instruction executed in SU 1 is called a scalar instruction, and an instruction executed in SU 1νU2 is called a vector instruction.

Once SU 1 transfers the vector instruction to V[J 2, it can independently process the subsequent scalar instruction. However, when an interrupt synchronized with a scalar instruction such as a program interrupt occurs in SU1, in order to guarantee the location where the interrupt occurs, it waits for the busy signal (VU-BUSY), which indicates that VU2 is processing, to fall. After that, interrupt processing starts.

At this time, it is also reported to SU1 whether there is a program interrupt factor in VU2. By doing this, if the vector instruction that appeared before the scalar instruction that caused the interrupt has completed, you can resolve the cause of the interrupt and start processing from that scalar instruction again (instruction If the order of the vector instruction is guaranteed, and if the vector instruction ended with an error, after the cause has been resolved, the process can be restarted from the beginning of the program block to which the scalar instruction and vector instruction belong, where the interrupt occurred. Aim to continue.

Similarly, if a SU 1 machine check occurs,
In order to confirm the location of the occurrence, wait until the busy signal (2), which indicates that VU 2 is being processed, falls.

However, in this case, if the instruction that caused the machine check can be identified after VU 2 processing is completed, and the register has not been changed or the memory updated yet, the error can be fixed by retrying that instruction in hardware. try to rescue.

If retry is not possible or if a predetermined number of attempts fail, a machine check interrupt is started. Even if a hardware retry of an instruction fails, there is generally a high possibility that the error can be corrected by a software retry as long as the order of the instructions can be guaranteed.

As mentioned above, by the busy signal ■, the SU
The means for making the interrupt processing of the VU 2 wait is important in order to guarantee the order of instructions, but as a result, the above-mentioned busy (b)
If a failure occurs that prevents the SUSY) signal from dropping, the SU
There is a problem in that the interrupt processing in step 1 cannot be started at all (or hangs up).

Some SU1s have a hang-up timer that monitors instruction execution time and generates a machine check interrupt when a timeout occurs.

It may be possible to treat the timeout of the above-mentioned busy signal ■ as a timeout of the instruction and to detect it using this timer, but the resulting machine check itself also waits due to the busy signal ■. and cannot be interrupted.

That is, since the busy signal does not fall, interrupt processing cannot be started.

As a means to solve this problem, there is a method of forcibly interrupting the processing of VU2 and turning off the busy signal (■) when a machine check of SO1 occurs. Since the completion of the second process is not guaranteed, the order of the instructions is not guaranteed and the instruction cannot be tried.

The above operation outline will be explained in more detail with reference to FIGS. 2 and 3.

Figure 2 shows the system configuration of a general supercomputer, where SU1 is a scalar unit VU2.
is a vector unit, and CHP is a channel control processor.

FIG. 3 is a time chart showing the processing of vector instructions in SO1. During the PROCESS state, SU1 sequentially executes a sequence of instructions on the memory. D-W in the diagram
indicates each stage of the pipeline of SU 1, and one instruction is processed in one set or several sets of DW pipeline flows.

When the SU 1 reads a vector instruction as shown in the figure, when the reading process is completed (for example, stage E of the last flow in FIG. 3), the vector instruction and data are
They are transferred to VU 2 together with control signals IV and DV, respectively. When the VU 2 starts a vector instruction, it turns on a signal ``VU-BUSY'' indicating that processing is in progress.

While VU2 is processing the vector instruction, SU1
Executes subsequent scalar instructions. Here, if a program exception (pgnχ) occurs in the subsequent scalar instruction, SU
1 transitions to the R51 state to start program interrupt processing. In the RS1 state, the pipeline in SU1 is cleared, and the EN for interrupt processing is cleared via the R5ID state, which indicates the end of the R51 state.
Transition to DPROC state. However, the above VU-BU
If SY■ is on, wait for VU-BUSY■ to turn off in state R51 in order to ensure ordering of instructions.

FIGS. 4(a) and 4(b) are circuit diagrams related to failure processing in the SU 1, and conventional signals not directly related to the present invention are omitted.

First, the hang-up timer 110 is a counter for detecting the timeout of one instruction, and is a counter for detecting the timeout of one instruction.
5TATE (stop state), +PSW WAIT (wait state bit of program status word), +END
It is reset to the initial value by a logical sum such as OP (1 instruction completed).

If the +END OP double signal remains off for a certain period of time and the counter value reaches a predetermined value, the timeout detection circuit will turn on +HANGUP DETE when the instruction is completed.
Turn on CT.

The +HANGUP DETECT is logically summed with other hard errors (+MCK DETECT) to cause a machine check interrupt (+MCK RUPT REQ) or retry (+SET RETRY), and
It is ORed with other interrupt factors (+RUPT REQ) and sets the latch (S/R type) 111 of R51 (R
51 state).

Output from retry control circuit 112 (+RETRY E
NBL) is a signal indicating that hardware retry is possible.

When the +R51 signal, which is the output of the R51 latch 111, is on, and the +VU BUSY■ is off, the R510 latch (D type) 113 becomes 1τ on (R510 state) when +5TPCBQ O, which will be described later, is on. .

This means that if +VU BUSY remains on, R5
This means that the ID latch 113 cannot be turned on.

When the RS10 latch 113 is turned on, the R51
The latch 111 of is reset. Above +5TPCBQ
O is.

This is a signal indicating that the stop counter 5TPC114 is zero. The 5TPC114 has the above +MCK D
This is the rising edge signal of ETECT (+SET 5TP
CALLI) initializes (and is set to all “1”s:
This is a counter that performs r-IJ until its value becomes zero.

This means that when a machine check (+MCK DETECT) occurs, the above RS is used during a period when other machine check factors may occur due to error propagation before starting machine check interrupt processing or retry.
This is a counter for waiting in state 1 (see the time chart in Figure 3).

As shown in the time chart of FIG. 3, the circuit 115 executes an instruction in SU1 in multi-flow, recognizes that it is a vector instruction, and starts VU2 (
+5TART VU IN5T), the above IV and DV indicating that the instruction and data are valid are set to V
This is a circuit for sending to U2.

Therefore, if the RS ID latch 113 continues to output the busy signal ■ on the VU 2 side, even if the stop counter 5TPC 114 detects all degrees 0, the time chart in FIG. The R51 state of the SU 1 becomes the superior of the R51 state, and the SU 1 is used for interrupt processing (ENDPRO
There was a problem that it became impossible to enter (C state).

In view of the above-mentioned conventional drawbacks, the present invention provides a central processing unit (SO)
and an additional unit (VU) that is attached to the central processing unit (SO) and executes a dedicated instruction transferred from the central processing unit 1 (SU), and the additional unit (VU) emits a signal indicating that processing is in progress. and the above central processing unit (SO) interrupt is
In an information processing system that is controlled to start interrupt processing after waiting for the processing of the additional device (VU) to be completed and the signal ``■'' indicating that the processing is in progress is turned off, if the additional device (VU) has a failure. An object of the present invention is to provide a fault handling method that can avoid a central processing unit (SU) from hanging up even when a busy state occurs and the SU hangs up.

[Means to solve the problem]

The above problems are solved by a failure handling method configured as follows.

The central processing unit f (SO) and the central processing unit f (SU)
It has an additional unit (VU) that executes dedicated instructions that are attached to the central processing unit (SU) and transferred from the central processing unit (SU).
VU) has a signal (■) indicating that processing is in progress, and the above-mentioned central processing unit (SU) interrupts after waiting for the processing of the above-mentioned additional unit (VU) to be completed and the above-mentioned signal (■ indicating that processing is in progress) being turned off. In an information processing system that starts interrupt processing from
) to monitor the processing completion wait time (hangup/
a timer), a means (VU clear means) for forcibly turning off a signal (VU clear means) indicating that the processing of the additional device (VU) is in progress when the processing end waiting time of the additional device (VTL) times out; By providing a means (stop counter (STPC) starting means) for forcibly starting machine check interrupt processing when the wait time for processing completion of VU (VU) times out, if a failure occurs in the additional bag W (VU), the above-mentioned When the time monitoring means detects that the signal (2) indicating that processing is in progress has hung up and has timed out, the additional unit (VU) is forcibly reset and the central processing unit (SU) is interrupted for processing. Configure it to enter.

[Effect] That is, according to the invention, a central processing unit (SU).

The central processing unit (S) is added to the central processing unit (SU).
An additional device (VU) that executes a dedicated instruction transferred from
), the additional device (VU) has a signal ① indicating that processing is in progress, and the interrupt of the central processing bag f (SO) is triggered by a signal indicating that the above processing is in progress after the processing of the additional device (VU) is completed. ■In an information processing system that starts interrupt processing after waiting for the central processing unit (SO
) for hang-up detection (1).
A timer that measures the instruction execution time is used to detect the timeout of the busy signal ■ from the VU side, and when a timeout is detected, VU is cleared and the busy signal ■ is forcibly released. In addition, the SU is configured to start machine check interrupt processing regardless of the busy signal (2), thereby avoiding a hang amplifier in the SU.

Therefore, even if a vU becomes a failure and leaves the busy signal ■, the vU will be forcibly cleared and the vU will be forcibly cleared.
By separating U from SU, SU can execute normal jobs via interrupt processing,
This has the effect of satisfying user requirements.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, in which VU 2
Even if a failure occurs on the side and a busy signal is sent, the SU 1 uses the timeout signal of the hang-up timer 110 to
The U clear circuit 12 clears V[I 2 and the vibe line in SU I, starts the stop counter 5TCP 114, and waits for a certain period of time until there are no errors caused by other machine checks, etc. ,
Means 1 for entering clear end (R510 state) for transitioning to interrupt processing (program status word (PSW) replacement: ENDPROC state)
1 is the means necessary to carry out the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, the failure handling method of the present invention will be explained with reference to FIG. 1 while referring to FIGS. 2 to 4.

Even if the present invention is implemented, when a program interrupt or machine check (MCK) occurs in SU 1, pipeline clear (RS 1 state), clear end (R510 state) 1 interrupt processing (ENDP
The series of basic operations for handling failures (such as ROC state) will not change, so we will omit the details.
Here, VU 2 has failed and is busy.
) The fault handling method of the present invention will be explained with a focus on the operation when a timeout is detected by the hang-up timer 110 of SU 1 when the signal (2) is output (VU BUSY) and is active.

FIGS. 1(a) and 1(b) are circuit diagrams showing an embodiment of the present invention, and correspond to the above-mentioned FIG. 4, and signals etc. not directly related to the present invention are omitted.

First, like the conventional method, the hang-up timer 110
is a counter for detecting instruction timeout, +5TOP 5TATE, +PSW WAIT,
It is reset to the initial value by a logical sum such as +END OP. If the +END OP times signal remains off for a certain period of time and the counter value reaches a predetermined value, the timeout detection circuit turns on +FIANGUP DE.
Turn on TECT.

The +HANGUP DETECT is logically summed with other hard errors (+MCK DETECT) to cause a machine check interrupt (+MCK RUPT REQ) or retry (+SET RETRY), and
It is ORed with another interrupt factor (+RUPT REQ) and sets the latch 111 of RS1. Further, the output (+RETRY ENBL) from the retry control circuit 112 is a signal indicating that hardware retry is possible.

In the present invention, the output signal of the R51 latch 111 is on, and the above +VU BUSY signal
If ANGUP DETECT is on, the above +5
If TPCEQ O is on, RS 10 latch 11
3 is configured so that 1τ is turned on.

This is the +VU BUSY signal above.
While GUPDETECT is off, R510 latch 11
3 does not turn on, and the hang-up timer 110 detects a timeout, and +HANGUP
When DETECT is turned on, it means that the R5ID latch 113 can be turned on regardless of the +VU BUSY signal (2) signal.

When the +R510 latch 113 is turned on, the R51 latch 111 is reset. That is, the RS1 state, which clears the pipeline, ends.

The +5TPCBQ O above is the stop counter (STP
C) is a signal indicating that 114 is zero.

In the present invention, the 5TPC 114 is the VU B
USY Nakanohasono hang up (+VU HANG
It is set to an initial value of all "1" by the logical sum (+SET 5TPCALLI) of P[JLSE) and the rising edge of +MCK DETECT, and operates as a counter that performs r-IJ until the value becomes zero.

This occurs when a machine check (+MCK DETECT) occurs and before starting machine check interrupt processing or retrying, during a period when other machine check factors may occur due to error propagation.

This is a counter for waiting in the R51 state (state where the pipeline is cleared).

In the case of the present invention, +VU HANG PULSE (i.e., VU
The signal indicating that the hang-up timer 110 has detected a timeout while SU 2 is busy is inserted in the machine check of SU 1 (+MCK DETE).
CT) occurs and the machine check interrupt processing or retry is made to wait in the RS 1 state due to VU BUSY. This is to make the RS1 wait in the RS1 state during a period when a hang-up is reported and a machine check may be detected on the Vtl2 side as a result.

Furthermore, in this embodiment, as is clear from the AND circuit 116 in the circuit 11 for starting interrupt processing,
+VU BUSY (7) +HANGUP DETCT
conditions have been met, and the retry permission signal (+RETRY
ENBL) is a deterrent condition. This is because the order of the instructions cannot be guaranteed because the vector instructions have not been completed.

The hang-up report to VU 2 mentioned above is 7029 above.
This is done by using the 7 circuit 12 and turning on +IV and +Dv simultaneously. +IV and +DV are 9. Normally, as explained in Figure 3, +5TART is used when sending a vector instruction.
By processing the VU IN5T signal 4), (7), and 7 (D), each of them turns on in turn by 2τ, and never turns on at the same time.

Therefore, like the VU checker circuit 12 of this embodiment,
VU 2 indicates that +IV and +DV were turned on at the same time.
is detected, VU 2 interrupts processing and +VU BU
It functions to turn off the SY signal ■.

With this configuration, SU 1 hang-up/
When a timeout is detected by the timer 110, the VL
By clearing I2 and resetting the hang-up condition, SU1 clears the pipeline via the pipeline clearing state (RS1) and the clearing end state (RS ID) in the same manner as before. and interrupt processing (E
NDPROC).

In this way, the present invention provides that even if the VLI 2 sends the busy signal due to a failure or the like, the SO1 is originally equipped with a hang-up timer 110.
Using the timeout signal of , the vU clear circuit 12 clears VU 2, clears the pipeline in SU 1, and clears the stop counter 5TCP 11.
4 is started, and after waiting for a certain period of time (until there are no errors caused by other machine checks, etc.), interrupt processing (program status word (PSW) replacement) is started.

〔Effect of the invention〕

As described above in detail, the fault handling method of the present invention includes a central processing unit (SU) and a dedicated instruction that is attached to the central processing unit (SO) and transferred from the central processing unit (SU). The additional device (VU) has an additional device (VU) that
U) has a signal ■ indicating that processing is in progress, and the central processing unit (
In an information processing system that is controlled to start interrupt processing after waiting for the processing of the additional unit (VU) to be completed and the signal ■ indicating that processing is in progress to be turned off, Means for monitoring the processing end waiting time of the additional device (VU) when the device (SU) interrupts; The additional device (V When the above-mentioned time monitoring means detects that a failure occurs in the VU, the signal indicating that the processing is in progress hangs up, and a timeout occurs, the additional device (VU) is forcibly restarted.
The central processing unit (SO) is configured to enter interrupt processing by resetting the CPU, so even if the VU becomes a failure and keeps emitting the busy signal, the additional unit (VU) will not be activated. Forcibly clear the corresponding additional device (VU)
) from the central processing unit (SU), the central processing unit W (SU) can now execute normal jobs via interrupt processing, which has the effect of satisfying user requests. There is.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing an example of the configuration of a supercomputer. FIG. 3 is a time chart diagram of vector instruction processing in a supercomputer. FIG. 4 is a diagram showing an example of a conventional fault processing circuit. It is. In the drawing, 1 is a central processing unit. 10 is a time monitoring means. 110 is a hang-up timer. 111 is R51 rashichi, 112 is or scalar unit (SU). try circuit. 113 is R510 latch. 114 is a stop counter (STPC). 116 is an AND circuit. 11 is a means for starting an interrupt. 12 is a means for forcibly turning off the signal (1) indicating that the additional device is processing, or a vU checker circuit; ■ is a signal indicating that processing is in progress, VU busy signal (VU BUS
Y). Or, BUSY end, or 10 VUSY. 2 is an additional device or vector unit 1-(VU). are shown respectively. The same figure shows an example of the configuration of a supercomputer.

Claims (1)

[Scope of Claims] A central processing unit (1) and an additional device (2) added to the central processing unit (1) to execute a dedicated instruction transferred from the central processing unit (1), the additional unit comprising: The device (2) has a signal ([1]) indicating that processing is in progress, and the interrupt of the central processing unit (1) is handled by the additional device (2).
) In an information processing system that starts interrupt processing after waiting for the processing in progress signal ([1]) to be turned off after the processing of the central processing unit (1) is completed, the above Additional equipment (
means (10) for monitoring the processing end waiting time of step 2), and forcing a signal ([1]) indicating that the processing of the additional device (2) is in progress when the end waiting time of the additional device processing (2) times out. and a means (11) for forcibly starting machine check interrupt processing when the wait time for completion of processing of the additional device (2) times out. When the time monitoring means (10) detects that a failure has occurred and the signal ([1]) indicating that the processing is in progress has hung up and timed out, the additional device (2) is forcibly switched off. Reset the central processing unit (
A fault handling method characterized by causing 1) to enter interrupt processing.