JPH04247705A - Integrated circuit device for voltage comparison - Google Patents

Abstract

PURPOSE:To prevent the resolution from being degraded by providing a first switch group leading the same potential reference voltage for the two inputs in the differential amplifier of the voltage comparison integrated circuit device and a second switch group leading the comparison symmetrical reference voltage. CONSTITUTION:Vin and VR1 are inputted in the noninverted input terminal of the differential amplifier DIF via switches S5 and S6, respectively. VR1 is inputted in the inverted input terminal via switches S7 and S8. In the standby period when the signal is in a high level, the switches S6, S8, S3, S4 closes and in the operation period when the inverted signal is in a high level, the switches S5 and S7 closes. Namely, in the both standby/operation periods, the number of switches passed when the signal is inputted in each input terminal is same. Therefore, if the impedances for these switches are set to the same condition, the resolution can be prevented from being degrated because the noise voltage by switches is inputted in the two input terminals symmetrically.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage comparison integrated circuit device that performs voltage comparison using a differential amplifier.

0002

2. Description of the Related Art A conventional voltage comparison integrated circuit device that performs voltage comparison using a differential amplifier has a circuit configuration of a so-called "DC restorer" type in order to compensate for the offset voltage of the differential amplifier.

FIGS. 1 and 2 show the structure of the conventional voltage comparison integrated circuit device. The operation of the conventional voltage comparator integrated circuit device will be explained according to these drawings.

[0004] In such a DC restorer, as shown in FIG. 3, two clock signals CL and CL/ ("/" means an inverted signal) having opposite phases are called a "standby period". It is input as a signal that defines the "operation period." FIG. 1 shows the standby period state, and FIG. 2 shows the operating period state. The circuits shown in FIGS. 1 and 2 consist of one differential amplifier DIF and a compensation circuit including a switch element (denoted as S) for compensating the offset voltage of DIF. This compensation circuit includes a switch S2 that short-circuits the non-inverting input and the inverting input of the DIF, capacitors C1 and C2 that store the offset output, and switches S3 and S4 that control the offset current during a storage operation. This DIF also has a switch S1 at its non-inverting input terminal for inputting an input signal only during the operating period.

The opening and closing operations of these switches S1 to S4 will be explained. The gate of the switch S1 is opened when the clock signal CL shown in FIG. 3 is at a high level (CL/ is at a low level), and the gate of the switch S2 is opened.
The gates of S4 to S4 are opened when the clock signal CL is at a low level (CL/ is at a high level). As a matter of course, when CL is at a low level, switch S1 is closed. FIG. 1 shows the open/closed state of the switch during the standby period, and FIG. 2 shows it during the operating period.

During the standby period when the signal CL is at a high level (signal CL/ is at a low level), the switches S2,
Since S3 and S4 are closed and switch S1 is open, reference voltage VR1 is input to both the non-inverting input terminal and the inverting input terminal of amplifier DIF. Therefore, DIF
An offset voltage (VOFF) is generated at the two output terminals of the capacitors C1 and C2.
is applied to one pole of each. On the other hand, capacitor C
The other terminals of 1 and C2 are connected to switches S3 and S4.
Since the capacitors C1 and C2 are closed, the reference voltage VR2 is applied, and therefore the potential difference V
A charge corresponding to R2-VOFF is charged. That is, the offset voltage of DIF is
is memorized.

During the operation period when the signal CL is at a low level (signal CL/ is at a high level), the switches S2,
Since S3 and S4 are open and switch S1 is closed,
Although G(Vin-VR1)+VOFF (here, G is the gain) appears at the output terminal of the amplifier DIF, VOFF is canceled due to the charging of the capacitors C1 and C2.

[0008]

SUMMARY OF THE INVENTION In such a conventional voltage comparator circuit, a standby period and an operating period are generated by inputting a control signal to a switch element.
The offset voltage is memorized during the standby period, and during the operation period,
This stored offset value is applied. However, in order to generate these waiting periods and operating periods, a switch is operated, and there is a risk that common mode noise may be generated due to the on/off operation of the switch.

[0009] In particular, since the amplifier DIF has a differential structure, in principle, the noise does not pose a problem as long as the noise is input in the common mode. However, as can be seen from FIGS. 1 and 2, the switch S1 is input only to the line of the non-inverting input terminal of the two input terminals. That is, since the signal source impedance and the reference source impedance are generally different, the noise voltages caused by the switches S1 and S2 are not input symmetrically to the two inputs of the differential amplifier. This asymmetry directly becomes noise and reduces the resolution of voltage comparison.

Furthermore, the conventional circuit configuration described above has the following problems. That is, in the application field of voltage comparison, the wider the range of the reference voltage (VR1), the wider the input dynamic range. However, in this conventional circuit, since VR1 is directly input, the dynamic range is determined by the common-mode input dynamic range of the differential amplifier.

SUMMARY OF THE INVENTION An object of the present invention was proposed to eliminate the problems of the prior art described above, and to propose a voltage comparison integrated circuit device with high resolution.

Still another object of the present invention is to propose a voltage comparator integrated circuit device that can provide a wide common-mode input dynamic range.

[0013]

[Means for Solving the Problems] A configuration of the present invention for achieving the above-mentioned problems is a voltage voltage circuit comprising a differential amplifier and an offset voltage sample and hold circuit for canceling the offset voltage of the differential amplifier. In the comparison integrated circuit device, two switch groups are provided at each of the two inputs of the differential amplifier, the first reference voltage being at the same potential as each of the two inputs of the differential amplifier. a first switch group consisting of first and second switches that lead to a second reference voltage, and third and fourth switches that lead to a comparatively symmetrical input voltage and a second reference voltage to each of the two inputs of the differential amplifier.
and a second switch group consisting of switches,
The two switch groups are characterized in that they open and close at opposite timings.

Since the two groups of switches are set symmetrically with respect to their inputs, the noise generated by the switches is the same for each input of the differential amplifier.

Still another configuration of the present invention is that, in addition to the above configuration, each of the switch groups includes, at a subsequent stage, respective capacitors for capacitor-coupling each of the two inputs of the differential amplifier and the differential amplifier. It further comprises a reference voltage circuit that can be opened and closed by fifth and sixth switches that supply a third reference potential to each input terminal of the amplifier, and the fifth and sixth switches
The switches are characterized in that they open and close at the same timing as the switches of the first switch group.

That is, the capacitor is charged with the difference between the first reference potential and the third reference potential.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Two preferred embodiments (first and second embodiments) to which the present invention is applied will be described below with reference to the accompanying drawings. The first embodiment (Figs. 4 and 5) aims to improve the resolution, and the second embodiment (Figs. 6 and 7) is an extension of the first embodiment, and the in-phase input dynamic This is an improved range.

Further, in these embodiments, the same reference symbols are given to the same components as in the conventional example shown in FIG.

Regarding the first embodiment, FIG. 4 shows the switch operation during the standby period, and FIG. 5 shows the switch operation during the operating period. That is, to the non-inverting input terminal of DIF, Vin via switch S5 and VR1 via switch S6 are input, and to the inverting input terminal, VR1 via switch S7 and VR1 via switch S8 are input. VR1 is input. During the standby period when the signal CL is at high level, switches S6, S8, S3, and S4 are activated.
is closed (FIG. 4), and during the operation period in which the signal CL/ is at a high level, switches S5 and S7 are closed (FIG. 5). That is, in both the standby period and the operation period, when a signal is input to each input terminal, the number of switches through which the signal passes is the same. Therefore, if the impedances of these switches are set to be the same, the noise voltage induced by the switches will be input symmetrically to the two input terminals, so that resolution will not be impaired.

Next, a second embodiment will be explained using FIGS. 6 and 7. This second embodiment further adds capacitors C3 and C4 and a switch S9 to the circuit of the first embodiment.
, S10 are added. That is, capacitor C3
, C4 are respectively provided to be AC coupled to the input line of DIF, and switches S9 and S10 are respectively provided to connect DIF to the input line of DIF.
A reference voltage VR2 is applied to the input terminal of the IF. Switch S
9 and S10 are controlled by the clock signal CL and are closed during the standby period.

Therefore, in this second embodiment, during the standby period, the switches S9 and S10 are closed and the same potential (VR2) is input to the input of DIF, so DIF outputs an offset voltage. , As a result, the offset voltage is stored in the capacitors C1 and C2. Further, when the switches S6 and S8 are closed, the capacitors C3 and C4 charge VR1-VR2, respectively.

The circuit operation when transitioning from standby mode to operation mode will be explained. At this time, capacitor C3
, C4 are the same as described above. When switches S6 and S8 open and switches S5 and S7 close, Vin+VR2-VR1 is input to the non-inverting input terminal of DIF, and VR1+VR2-VR1 is input to the inverting input terminal. In other words, the input signal Vin is converted into a voltage-based signal and input to DIF. Therefore, the in-phase input dynamic range is equivalently expanded. Since the dynamic range of the input signal Vin is limited only by the withstand voltage of capacitors C3 and C4 (this withstand voltage is much larger than the dynamic range of the differential amplifier), the conventional comparator circuit is limited to the common-mode input dynamic range of DIF itself. This is a several step improvement compared to what was done before.

The present invention can be modified in various ways without departing from its spirit.

For example, in the first embodiment shown in FIGS. 4 and 5, the reference voltage input to the two input terminals of DIF during the standby period was set to VR1 for comparison of Vin. Separate voltages may also be used.

For the same reason, in the second embodiment,
The reference potential VR2 of the switches S9 and S10 may be the same as VR1.

Various circuit configurations are possible for the switch. FIG. 8 is a circuit example of a switch that closes when the signal CL is high level and CL/ is low level (standby period).
FIG. 9 is a circuit example of a switch that closes when the signal CL is at a high level and CL is at a low level (operation period).

FIG. 10 is an example of a DIF circuit.

These switches and DIF can be constructed from MOS transistors.

[0029]

[Effects of the Invention] As explained above, the configuration of the voltage comparison integrated circuit device of the present invention includes a differential amplifier and an offset voltage sample and hold circuit for canceling the offset voltage of the differential amplifier. In the voltage comparison integrated circuit device, two switch groups are provided at each of the two inputs of the differential amplifier, the first reference having the same potential with respect to each of the two inputs of the differential amplifier. a first switch group consisting of first and second switches that conduct voltage; and third and fourth switches that conduct comparatively symmetrical input voltages and second reference voltages to each of the two inputs of the differential amplifier. and a second switch group consisting of switches, and the two switch groups are characterized in that they open and close at mutually opposite timings.

Therefore, since the switches in the above two groups are set symmetrically with respect to the inputs, the noise generated from the switches is the same for each input of the differential amplifier, so the resolution of the entire circuit increases. .

Still another configuration of the present invention is that, in addition to the above configuration, a respective capacitor for capacitor-coupling each of the two inputs of the differential amplifier and the differential amplifier are provided at the rear stage of each of the switch groups. It further comprises a reference voltage circuit that can be opened and closed by fifth and sixth switches that supply a third reference potential to each input terminal of the amplifier, and the fifth and sixth switches
The switches are characterized in that they open and close at the same timing as the switches of the first switch group.

That is, since the capacitor is charged with the difference between the first reference potential and the third reference potential, the common-mode input dynamic range of the entire circuit becomes dependent on the characteristics of the capacitor. is larger than the dynamic range of the differential amplifier. .

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the operation of a conventional circuit.

FIG. 2 is a diagram explaining the operation of a conventional circuit.

FIG. 3 is a timing chart of a clock signal used for timing control of the DC restorer.

FIG. 4 is a diagram explaining the circuit operation of the first embodiment.

FIG. 5 is a diagram explaining the circuit operation of the first embodiment.

FIG. 6 is a diagram explaining the circuit operation of the second embodiment.

FIG. 7 is a diagram illustrating the circuit operation of the second embodiment.

FIG. 8 is a diagram showing a circuit example of a switch that closes during a standby period.

FIG. 9 is a diagram showing an example of a circuit of a switch that closes during an operation period.

FIG. 10 is a diagram showing a circuit example of an amplifier DIF.

[Explanation of symbols]

DIF...Differential amplifier S...Switch C...Capacitor

Claims (3)

[Claims] 1. A voltage comparison integrated circuit device comprising a differential amplifier and an offset voltage sample-and-hold circuit for canceling the offset voltage of the differential amplifier, wherein each of two inputs of the differential amplifier two switch groups provided, two switch groups of the differential amplifier;
a first switch group consisting of first and second switches that lead a first reference voltage of the same potential to each of the two inputs of the differential amplifier; and a comparatively symmetrical input voltage to each of the two inputs of the differential amplifier. and a second switch group consisting of third and fourth switches that guide the second reference voltage and the second reference voltage.
A voltage comparison integrated circuit device characterized in that switch groups of a set open and close at mutually opposite timings. 2. A third reference potential is provided at a subsequent stage of each of the switch groups to respective capacitors for capacitor coupling each of the two inputs of the differential amplifier and to each input terminal of the differential amplifier. It further comprises a reference voltage circuit that can be opened and closed by a fifth and sixth switch, and the fifth and sixth switches open and close at the same timing as the switches of the first switch group. A voltage comparison integrated circuit device according to claim 1. 3. The voltage comparison integrated circuit device according to claim 1, wherein the first and second reference voltages are equal.