JPH04247522A - Parallel operation processor - Google Patents

Abstract

PURPOSE:To suppress following instructions to be aborted at a branch to a minimum by changing the number of instructions coming after a branching instruction and a branching destination address to be allocated to an operation execution part according to probability calculated from the branching history of the branching instruction. CONSTITUTION:When simultaneously processing the plural instructions and the branching instruction exists in a prefetched instruction group, the instruction is also fetched from the branching destination address where branching occurs according to the same branching instruction. Next, the probability for the branching instruction to execute branching is calculated according to the branching history of the branching instruction extracted from a storage device 1. Then, a ratio between the number of instructions coming after the branching instruction to be allocated to plural operation execution parts 13a-13h and the number of instructions coming after the branching destination address is decided according to the probability. Thus, the instructions are distributed to the operation execution parts 13a-13h while changing the ratio between the both numbers of instructions by using the probability of branching, and the instruction having no data depending relation with the instruction before the branching instruction at the branching destination is issued to the operation execution parts 13a-13h.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel arithmetic processing device that simultaneously performs a plurality of arithmetic operations in parallel using a pipeline processing method and a parallel processing method.

0003

2. Description of the Related Art In recent years, some arithmetic processing devices are performing parallel processing that allows multiple operations to be performed per machine cycle, examples of which include superscalar and VLIW. These devices have multiple arithmetic units and processing units within the arithmetic processing unit, and when they execute in parallel, CPI (clock per I)
structure) is made smaller. Further, the arithmetic unit and the processing unit usually perform processing in a pipeline, thereby providing higher processing power.

[0004] One of the problems when performing processing using a pipeline is that the pipeline is disrupted by execution of a branch instruction. Normally, when a branch occurs, subsequent instructions in the pipeline after the branch instruction are aborted, and the pipeline stages from fetching the branch destination instruction to execution are wasted. Therefore, various methods have been taken to reduce the number of operation instruction aborts caused by branches of branch instructions.

For example, in pipeline processing, during compilation, instructions that are not aborted even if a branch occurs after a branch instruction (instructions that are originally executed before a branch instruction, but whose operation result does not affect the branch) ) (delayed instruction). FIG. 7 shows an example of a delayed instruction. Assume that I0 and I1 are normal instructions, and I2 is a branch instruction. If the pipeline has a five-stage configuration and the branch decision is made in the third stage, when I2 reaches the third stage of the pipeline and a branch is executed, the instruction I2 that follows I2 is normally
3 and I4 are aborted (FIG. 7(a)). I3
If the instruction I4 is a delayed instruction, the instruction I4 is aborted, but the instruction I3 continues through the pipeline and is executed regardless of whether the branch instruction I2 branches. As a result, the number of stages to be aborted is reduced from two to one (Figure 7 (
b)).

[0006] In addition to the method using the above-mentioned delayed instruction,
When there is a branch instruction, the instruction to be executed following the branch instruction is set as the subsequent instruction of the branch instruction or as the branch destination instruction, depending on the history of whether or not the same branch instruction was executed in the past. There are branch prediction methods that determine whether the

The method using delayed instructions described above applies to devices that process one instruction per cycle, but there has not been a delayed instruction method for devices that process multiple instructions in parallel per cycle. Therefore, in parallel processing, when a group of instructions including a branch instruction are executed simultaneously, if a branch occurs, on a sequential model, the instruction before the branch instruction continues to execute, and the instruction after the branch instruction continues to execute. had to stop running.

[0008] Another problem is that in an arithmetic processing device such as a superscalar that can execute processes simultaneously, the number of instructions that can be executed simultaneously in a series of instructions is limited to 2 to 3 instructions due to data dependencies. There is also the problem that the calculation execution unit is often vacant, and the merits of parallel processing are halved due to wasted operation execution units.

[0009]

[Problems to be Solved by the Invention] As described above, in parallel arithmetic processing devices such as conventional pipelines or parallel processing devices, which have a mechanism that starts execution of instructions following a branch instruction before the branch is confirmed, there is always a large number of problems due to branching. There was a problem that subsequent instructions would be aborted.

[0010] The present invention has been made in view of the above-mentioned circumstances, and its purpose is to prevent instructions that are aborted by branch instructions even when processing multiple instructions in parallel in one cycle. An object of the present invention is to provide a parallel arithmetic processing device that can reduce the number of parallel operations to a minimum.

[Configuration of the invention]

0012

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a plurality of arithmetic execution units that operate in a pipeline and can operate simultaneously in parallel, and a fetched conditional branch instruction that has previously branched. history information holding means for holding history information on whether or not the conditional branch instruction was executed; a subsequent instruction group holding means for holding a group of instructions subsequent to the conditional branch instruction; and a branch destination holding a group of instructions after the branch destination address of the conditional branch instruction. an instruction group holding means, a probability generation means for calculating the probability of a branch occurring using the history information holding means, and a number of instructions to be issued from the subsequent instruction group holding means according to the probability obtained from the probability generation means. and an instruction distributing means for determining the number of instructions to be issued from the branch target instruction group holding means and allocating each instruction to the plurality of operation execution units.

[0013]

[Operation] With the above means, when multiple instructions are being processed simultaneously in an arithmetic processing unit that has a plurality of arithmetic execution units that can be executed simultaneously, a group of prefetched instructions for distribution to multiple arithmetic units is If a branch instruction exists, before the execution of the branch instruction, an instruction is also fetched from the branch destination address when a branch occurs with the same branch instruction, and the same branch is fetched from the storage device that holds the branch history of the branch instruction. From the branch history of an instruction, find the probability that the same branch instruction executes a branch, and calculate the ratio of the number of instructions after the branch instruction that are assigned to multiple arithmetic execution units to the number of instructions after the branch destination address based on the probability. decide. In this way, the ratio of the number of instructions after the branch instruction and the number of instructions after the branch destination address, which are allocated to multiple arithmetic execution units, is changed using the branch probability, and the number of instructions after the branch instruction is changed. , by distributing the instructions after the branch destination address to the arithmetic execution unit, and issuing to the arithmetic execution unit an instruction at the branch destination that has no data dependency with the instruction before the branch instruction, the instruction by the branch at the time of branch execution. Preventing aborts.

[0014]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a parallel arithmetic processing device of the present invention. In this embodiment, a superscalar type RISC processor that can execute eight instructions simultaneously will be taken as an example.

The parallel arithmetic processing device shown in FIG. 1 has an instruction memory 1 (hereinafter referred to as IM
), the instruction latch unit 2, the branch target instruction latch unit 3, and the instruction latch unit 2 by allocating and inserting the instruction fetched from the IM into the vacant part of the instruction latch unit 2 where an instruction has already been issued. an instruction allocator 4 for making sure that the instruction latch unit 2 is full; a branch destination instruction allocator 5 that operates in the same manner as the instruction allocator 4 in the branch destination instruction latch unit 3; 6. Branch destination program counter 7 containing the address of the instruction to be latched from the IM 1 to the branch destination instruction latch unit 3; the address of a branch instruction that specifies the use of the circuit of the present invention and the same branch instruction; The branch target buffer 8 (hereinafter referred to as BTB) stores the branch destination address, the instruction group of the branch destination, and the branch history of the branch instruction, and in which position of the instruction group in the instruction latch section 2 the branch instruction is placed. Based on the results of the non-abort instruction detection circuit 9 and the non-abort instruction detection circuit 9, which determine whether the instruction exists and calculate the number of instructions from the beginning of the instruction latch unit 2 to the branch instruction, and the branch history sent from the BTB 8. , a distributed instruction number calculation circuit 10 that generates a probability that a target branch instruction will branch, and determines the number of instructions after the branch instruction and the number of instructions after the branch destination address to be distributed to the arithmetic units; 10, the instruction distribution circuit 11 determines the instruction to be issued from the instruction latch unit 2 and the branch destination instruction latch unit 3, the latch unit 12 temporarily latches the instruction output from the instruction distribution circuit 11, and executes the operation. The data memory 14 (hereinafter referred to as DM) holds data necessary for the calculations.

[0016] Here, the branch instruction includes:
As an instruction to be executed following a branch instruction, there are two types of instructions: one in which a group of consecutive instructions is specified in the same branch instruction, and one in which a group of instructions at the branch destination of the same branch instruction is specified. There is an instruction specified to allocate a group of consecutive instructions and a group of branch destination instructions. In addition, for branch instructions specified not to use the distribution instruction number calculation circuit 10,
Branch probabilities are set in advance by the user.

It is assumed that the IM1 and DM14 can be accessed simultaneously by a plurality of ports or by a shared memory. The instruction latch unit 2 performs normal instruction prefetch from the IM1. The instruction allocator 4 includes a group of instructions to be latched from the IM 1 to the instruction latch unit 2;
A group of instructions that will be the output of the instruction latch unit 2 enters, and according to information from the distributed instruction count calculation circuit 10, the group of instructions from the instruction latch unit 2, excluding the instructions that have already been issued to the operation execution units 13a to 13h, is Instructions that have not yet been issued are shifted and filled in, the empty portion is filled with instructions from IM1, and the result is input to the instruction latch section 2.

The branch destination instruction latch unit 3 stores the branch instruction B.
When there is a hit (match) in TB8, a group of instructions after the branch destination sent from BTB8 via the branch destination instruction allocator 5 or a group of instructions sent from the branch destination instruction allocator 5 are latched. Like the instruction allocator 4, the branch destination instruction allocator 5 receives a group of branch destination instructions to be latched from the IM1 to the branch destination instruction latch unit 3 and a group of instructions to be output from the branch destination instruction latch unit 3, and determines the number of distributed instructions. Calculation circuit 10
Based on the information from the branch destination instruction latch unit 3, the instructions that have not yet been issued are shifted and filled in, excluding the instructions that have already been issued to the operation execution units 13a to 13h, and the IM1 is filled in the vacant part. , and the result is input to the branch destination instruction latch unit 3.

FIG. 2 is a diagram illustrating the operations of the instruction allocator 4 and the branch destination instruction allocator 5. At time t0, if there are 8 instructions from instruction I0 to instruction I7 in the instruction latch unit 2, and at time t1, instructions I0 to I2 are issued, instructions I3 to I7 are shifted to the left by three instructions. Then, the instruction read from IM1 is entered into the vacant three instruction portion.

The address of the program counter 6 is incremented by the number of instructions issued from the instruction latch section 2, which is calculated by the distributed instruction number calculation circuit 10. That is, the program counter 6 will have the address of the first instruction to be read into the instruction latch section 2 at the next clock.

Similar to the program counter 6, when BTB8 is hit, the branch program counter 7
The address obtained by adding the number of instructions issued from the branch destination instruction latch unit 3, which is output from the distribution instruction number calculation circuit 10, is entered into the branch destination address +8 output from B8, and in the next clock, the address that is currently held is entered. The value obtained by adding the number of instructions issued from the branch destination instruction latch unit 3 in the next clock is entered.

FIG. 3 shows a configuration diagram of the BTB 8. BTB8
The address tag of the branch instruction, an address tag match detection circuit (not shown), the branch destination address of the branch instruction,
It holds a group of branch destination instructions and a branch history of the branch instructions. The address tag holds the address where the past branch instruction was located. The BTB 8 uses an address tag match detection circuit to search for addresses for up to eight instructions from the address of the program counter 6.

[0023] The branch history holding unit holds the branch history of the branch instruction corresponding to the address tag in a decoded or encoded form. For example, one entry has a 6-bit structure, and the past six branch histories are stored in an unencoded form. If the branch instruction corresponding to the same tag has a history of "branch", "non-branch", "branch", "branch", "non-branch", and "branch" in the past, the branch history holding section ,”0
10010" is held. The leftmost part of these 6 bits is the oldest history, and new branch history is added to the right side.

If there is a branch instruction that uses the branch history held in the branch history holding unit in the instruction latch unit 2,
The address of the same branch instruction is compared with the address tag, and if there is a hit, the branch history is output. If there is no hit, the branch history with the probability set in the branch instruction by the user is output. For example, if the branch history is 6 bits,
If the probability that a branch occurs in a branch instruction is set to 1/2, "101010" or "010101" is issued.

Two clocks later, when the result of the branch instruction is determined, the branch history update unit (not shown) stores the past branch history “010010” in the branch history holding unit corresponding to the address tag of the branch instruction. is shifted to the left by 1 bit, and the rightmost part contains "0", which is the branch result, and becomes "100".
100" is updated in the branch history holding unit. However, in the case of a branch instruction that specifies a group of consecutive instructions and a branch instruction that specifies a group of instructions at the branch destination, the branch history is not used. , the output is changed to the branch history assuming that the history was all non-branching or all branching in the past.In the above example, "
000000” or “111111” is output,
It is not written back to the branch history holding unit.

When the BTB 8 is hit, the BTB 8 outputs the branch destination instruction 8 to the branch destination instruction latch section 3 and outputs the address of the branch destination address + 8 instructions to the branch destination program counter 7 .

The contents of the instruction latch section 2 are sent to the non-abort instruction detection circuit 9, and the contents are sent to the instruction latch section 2 by a method such as flagging a branch instruction by predecoding or recognizing a branch instruction by decoding. Recognizes the position of the branch instruction in the group of retained instructions and calculates the instructions before the branch instruction, that is, the number of non-abort instructions (including branch instructions) that will not be aborted due to the branch of the branch instruction. . The number obtained by subtracting the number of non-abort instructions from the number of arithmetic execution units 13a to 13h is the instruction group following the branch instruction,
This is the total number of instructions allocated to the operation execution units 13a to 13h from the instruction group after the branch destination address of the branch instruction.

The branch history retrieved from the BTB 8 and the number of non-abort instructions calculated by the non-abort instruction detection circuit 9 are sent to a distributed instruction number calculation circuit 10. The distribution instruction calculation circuit 10 determines the number of available arithmetic execution units, excluding the arithmetic execution units 13 to which non-abort instructions are distributed, from the number of non-abort instructions, and calculates the number of arithmetic execution units held in the instruction latch unit 2 based on the branch probability. The number of instructions to be distributed to the arithmetic execution unit 13 and the number of instructions to be distributed from the branch destination instruction latch unit 3 to the arithmetic execution unit 13 are determined among the instructions after the branch instruction. Operation execution unit 1 from instruction latch unit 2 and branch destination instruction latch unit 3
The instructions distributed to 3a to 13h are flagged by the instruction distribution circuit 11 to indicate four states: abort when branch is executed, abort when branch is not executed, branch executed, execution regardless of whether branch is executed, and execution abort. Arithmetic execution units 13a-1
3h, and each instruction is aborted using the same flag when a branch is established.

The non-abort instruction detection circuit 9 detects the position of the branch instruction among the eight instructions in the instruction latch unit 2. If there is a third branch instruction, "11100000" is output (FIG. 4).

The distributed instruction count calculation circuit 10 learns from the non-abort instruction detection circuit 9 that the number of arithmetic execution units 13 to which instructions can be assigned is "5", and determines that the branch history is "010010" from the branch history storage unit. Know Ako. In a branch instruction,
If the number of allocations is surplus or insufficient, no branching,
It is also defined which branch to select, and if the branch instruction is defined to select a non-branch, in the above example, "010010" is processed and "110000" is
”, take the rightmost 0 and make it “11000”, and replace “11000” in the “0” part of “11100000” above.
", generates "11111000" and outputs it to the instruction distribution circuit 11. Also, if it is defined to select a branch, take the leftmost 1 of "110000" and embed it as "10000". .

If there are 7 or more 0s out of the 8 bits output from the non-abort instruction detection circuit 9, if it is defined to select a non-branch, then "110000"
” is added to the leftmost part, and if a branch is defined to be selected, a 0 is added to the rightmost part and embedded.

[0032] The number of instructions output from the instruction latch unit 2;
The number of instructions output from the branch destination instruction latch section 3 is sent to the program counter 6 and the branch destination program counter 7, respectively. In the above example, the program counter 7 is “5”.
", but "3" is sent to the branch destination program counter 7 (FIG. 5).

In the instruction distribution circuit 11, according to the value "11111000" obtained from the distribution instruction number calculation circuit 10, 5
Five instructions are distributed from the instruction latch unit 2 to the arithmetic execution units 13a to 13e, and three instructions are distributed from the branch destination instruction latch unit 5 to the three arithmetic execution units 13e to 13h. When instructions are distributed, the value obtained from the distribution instruction number calculation circuit 10 is used.
11111000" and the value "11100000" obtained from the non-abort number calculation circuit 9, one bit is each extracted and distributed to the operation execution units 13a to 13h at the same time as the instruction. That is, the three operation execution units 13a to 13h 13
A flag of “11” is set in each of the two arithmetic execution units 13 in c.
A flag of "01" is set in each of d and e, and the three arithmetic execution units 13f to 1 to which instructions are distributed from the branch destination instruction latch unit 5
A flag of "00" is distributed to 3h. Then, when the branch is confirmed, the calculation execution unit 13 to which the flag of "11" is distributed
a to 13c continue execution regardless of the result of the branch instruction,
The arithmetic execution units 13d and 13e to which the flag "01" has been distributed continue execution when there is no branch, abort the instruction when branched,
Arithmetic execution units 13f to 13 to which a flag of “00” is distributed
h aborts the instruction when a non-branch occurs and continues execution when a branch occurs (FIG. 6).

When a branch is executed, the program counter 6 stores the number of instructions issued by the instruction distribution circuit 11 among the branch destination instructions sent from the distribution instruction number calculation circuit 10 to the branch destination program counter 7. The address obtained by adding 2 is entered, and the instruction group remaining in the branch destination instruction latch section 3 is moved to the instruction latch section 2.

Normally, when a plurality of instructions are to be executed simultaneously, the probability that all the instructions in the instruction queue can be executed simultaneously is small due to data dependencies. In the above example, a block for data dependence analysis is not attached, but when actually building a circuit and performing data dependence analysis, the circuit should be attached to the distribution instruction number calculation circuit 10 and connected to the instructions already being executed, such as on a scoreboard. By installing a circuit that analyzes data conflicts and data conflicts between instructions in the instruction latch unit 2 and branch destination instruction latch unit 3 due to data conflict and decoding, and masks issued instructions, instruction issuance can be stopped due to data dependence.

In the above example, the branch probability is 4/6, and if the number of instructions that can be executed simultaneously is 2 for each of the instructions after the branch instruction and the instructions after the branch destination address, then the conventional simple In branch prediction control, instructions after the branch destination address are allocated after the branch instruction.
h becomes empty. In this case, the number of effective instructions when the branch is determined is 2×4/6, which means that the probability is 1.33 instructions. In the case of the control according to the present invention, three instructions are selected from the branch destination address and two instructions are selected from the instructions following the branch instruction, and the number of instructions assigned to each of the operation execution units 13d to 13g is two instructions. In this case, the number of valid instructions when the branch is confirmed is
2×4/6+2×2/6, which is 2 instructions.

In the above example, the branch instruction appears for the first time, and B
Although there are many cases where TB8 is not hit, the reason why BTB8 was used in the above example is that it takes a considerable amount of time to calculate the branch destination address, and when actually building the circuit, it takes 1
This is because calculation may not be possible in clock cycles. Therefore, if the branch destination address and branch destination instruction group of the BTB 8 are not used, there will be no problem if the number of instruction fetch phases is increased by one to provide time for address calculation. In addition, if the interval between branch instructions is short, branch instructions appear in the instruction group of the branch destination, and the number of branch destination instructions increases in a tree structure, multiple instructions may be This problem can be solved by providing a buffer and providing a circuit for selecting the buffer input and buffer output.

Furthermore, due to problems such as data dependence, either the instruction group following the branch instruction or the instruction group at the branch destination cannot issue the instruction to the operation execution units 13a to 13h assigned according to the probability, and the operation execution is delayed. If space is available in the sections 13a to 13h, it is possible to further change the instruction allocation ratio and build a circuit for executing the other instruction.

[0039]

As described above, according to the parallel arithmetic processing device of the present invention, when there is a branch instruction, the information after the branch instruction is allocated to the arithmetic execution unit based on the probability determined from the branch history of the branch instruction. The number of instructions after the branch destination address and the number of instructions after the branch destination address are changed. As a result, even when a plurality of instructions are processed in parallel in one cycle, it is possible to minimize the number of subsequent instructions that are aborted due to branches, and it is also possible to reduce the waiting time of the arithmetic execution unit caused by data dependencies and the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of operations of an instruction allocator and a branch destination instruction allocator shown in FIG. 1;

FIG. 3 is a configuration diagram of the branch target buffer shown in FIG. 1;

FIG. 4 is an explanatory diagram of the operation of the non-abort instruction detection circuit shown in FIG. 1;

FIG. 5 is an explanatory diagram of the operation of the distribution instruction number calculation circuit shown in FIG. 1;

FIG. 6 is a configuration diagram of the instruction distribution circuit shown in FIG. 1;

FIG. 7 is a diagram for explaining a conventional delayed instruction.

[Description of symbols] 1 IM (instruction memory) 2 Instruction latch section 3 Branch destination instruction latch section 4 Instruction allocator 5 Branch destination instruction allocator 6 Program counter 7 Branch destination program counter 8 BTB (branch target buffer) 9 Non-abort instruction detection circuit 10 Distribution instruction number calculation circuit 11 Instruction distribution circuit 12 Latch sections 13a to 13h Arithmetic execution section 14 DM (data memory)

Claims (1)

[Claims] 1. A plurality of arithmetic execution units that operate in a pipeline and can operate simultaneously in parallel; a history information holding unit that holds history information as to whether or not a fetched conditional branch instruction has branched in the past; A subsequent instruction group holding means holds a subsequent instruction group of a conditional branch instruction, a branch destination instruction group holding means holds a group of instructions after the branch destination address of the conditional branch instruction, and the history information holding means is used to execute a branch. a probability generating means for determining the probability of occurrence, and determining the number of instructions to be issued from the subsequent instruction group holding means and the number of instructions to be issued from the branch target instruction group holding means according to the probability obtained by the probability generating means. and an instruction distributing means for allocating each instruction to the plurality of operation execution units.