JPH04205625A - Parallel processing computer - Google Patents

Abstract

PURPOSE:To execute processing in high speed by means of making the most use of a rich software property by aborting the execution of respective instructions by means of the relation of aborting condition flags added to the respective instructions based on delayed branch instructions or squash branch instructions and the success or failure of the branch instructions. CONSTITUTION:Plural instructions fetched by a fetching circuit 1 are transmitted to an instruction buffer 2 and are latched and the instructions latched by the instruction buffer 2 are transmitted to an instruction feeder 3 and are transmitted to a conditions abort generation circuit 4. The instructions feeder 3 respectively supplies the instructions transmitted from the instruction buffer 2 to respective execution units 5 and a branch execution unit 6. Here, the execution of respective instructions are aborted by the relation of the abort condition flags added to the respective instructions based on the delayed branch instructions or the squash branch instructions and the success or failure of the branch instructions. Thus, high-speed processing is executed by making the most use of a rich software property.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Industrial Field of Application) The present invention relates to a parallel processing computer capable of simultaneously executing a plurality of instructions.

(Prior Art) -1- Conventionally, RISC type processors with fast instruction execution processing have been used as parallel computing computers that execute multiple instructions at the same time, and recently, RISC type processors with faster instruction execution processing have been used. A superscalar type processor has been developed and is currently commercialized, such as Intel's 8096OCA.
It has been known.

In this case, since RISC processors have a wealth of past software assets, in order to make effective use of these software, when developing a superscalar processor, it is necessary to make object compatibility with previous software. It has become necessary to develop a processor with this ability.

By the way, some RISC processors employ a delayed branch method or a squash branch method in order to reduce losses due to unnecessary operations when executing branch instructions.For example, Sun Microsystems' R2000 and R3000 It has been known. Here, in the delayed branch method, if there is a branch instruction,
The instruction next to this breech instruction is executed before the branch destination instruction is executed. Also, in the squash branch method, when there is a breech instruction, when the branch is not ticked, the next instruction after the branch instruction is executed. Execute the next instruction without executing the instruction, and when branch ticking,
The instruction following the branch instruction is executed to execute the instruction at the branch destination.

However, although superscalar processors have fast instruction execution speeds, their control methods are complex, making it difficult to directly execute RISC machine injection code that uses the above-mentioned delayed branch method or squash branch method. However, it has not been possible to maintain object compatibility with programs of RISC processors that execute these delayed branch instructions and squash branch instructions.

By the way, Intel's superscalar processor 8
0960CA is the company's RISC type processor 8096
Although the 80960KA maintains object compatibility with the 0KA, the current situation is that the 80960KA does not employ a delayed branch method or a squash branch method.

(Problems to be Solved by the Invention) As described above, superscalar processors, which have recently been considered to replace RISC processors, cannot execute delayed branch instructions or squash branch instructions as they are, so they It has a drawback that it cannot maintain object compatibility with programs of RISC type processors that can execute instructions.

The present invention has been made in view of the above circumstances, and provides a superscalar processor that can execute both delayed branch instructions and squash branch instructions, and that maintains object compatibility with programs of RISC processors. The purpose of the present invention is to provide a parallel processing computer with the following features.

[Configuration of the Invention (Means for Solving the Problem) The parallel processing computer of the present invention is capable of simultaneously executing a plurality of instructions, and is capable of executing a delayed branch instruction or a squash branch instruction from among the plurality of instructions. and flag adding means for adding a flag indicating an abort condition to each instruction based on the result of this judgment, and execution of each instruction based on the flag indicating the abort condition added to each instruction and the success or failure of each branch instruction. It consists of an abort execution means that performs an abort.

(Operation) As a result, according to the present invention, the execution of each instruction can be aborted based on the relationship between the abort condition flag added to each instruction based on the delayed branch instruction or the squash branch instruction and the success or failure of the branch instruction. RISC processors with rich software assets can now execute both delayed branch instructions and squash branch instructions.
Object compatibility with type processor programs can be maintained.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example in which the present invention is applied to a superscalar machine with a five-stage pipeline that executes four instructions simultaneously. The pipeline here consists of fetch (F), decode (D)
), execution (E), memory access (M), write (W)
It consists of stages.

In the figure, 1 is a fetch circuit, and this fetch circuit 1
accesses an instruction cache memory (not shown) to fetch a plurality of instructions.

A plurality of instructions fetched by the fetch circuit 1 are sent to an instruction buffer 2 and latched. Also,
The instructions latched in instruction buffer 2 are
It is sent to the instruction supply unit 3 and also to the conditional abort generation circuit 4.

The instruction supplier 3 supplies the instructions sent from the instruction buffer 2 to each execution unit 5 and branch execution unit 6, respectively. In this case, the execution unit 5 consists of decode (D), execution (E), memory access (M), and write (W) stages.

The condition abort generation circuit 4, the details of which will be described later, generates a condition abort flag for the execution unit 5 and the fetch circuit 1, and sends an E stage condition abort signal 481 and a D stage condition abort signal 482 to the execution unit 5. is given, and an F stage condition abort signal 483 is given to the fetch circuit 1.

FIG. 2 shows a specific circuit of the execution unit 5.

In this case, the instructions supplied from the instruction supplier 3 are sent to the decoder 51 of the decode (D) stage. The decoder 51 decodes the command supplied from the command supply device 3 to generate an "alit signal 521" for the (D) stage. This signal is input to this input terminal.

This AND circuit 53 enables the valid signal 521 to be negated based on the output content of the abord determination circuit 54 applied to the other input terminal.

The abord determination circuit 54 determines an abord based on the relationship between the (D) stage condition abord signal 482 latched in the latch 551 and the barnch-taken 522 indicating whether or not to branch.

The output of the AND circuit 53 is latched by the latch 552 of the (E) stage and sent to one input terminal of the AND circuit 55 as the (E) stage valid signal 523. This AND circuit 55 also enables the (E) stage invalidation signal 523 to be negated by the output content of the abord determination circuit 56 applied to the other input terminal.

This abord determination circuit 56 also determines abort based on the relationship between the (E) stage condition abord signal 481 latched in the latch 553 and the barnch-taken 522 indicating whether or not to branch, in the same way as the abord determination circuit 54 described above. I have to.

The output of this AND circuit 55 is given as a write enable signal EW to the register file 57 via a latch 554 in the (M) stage and a latch 555 in the (W) stage.

The contents of the register file 57 are operated by the arithmetic unit 58 via the latches 556 and 557 of the E stage, and the result of the operation is sent to the latches 558 and 558 of the (M) stage.
(W) It is designed to be written via the latch 559 of the stage.

FIG. 3 shows a specific circuit of the conditional abort generation concave path 4. In FIG.

In this case, a plurality of (four in this case) instructions latched in the instruction buffer 2 are sent to the branch instruction decoder 44.

The branch instruction decoder 44 decodes the instruction provided from the instruction buffer 2 and determines whether it is a delayed branch instruction, a squash branch instruction, or another instruction.

The results determined by the branch instruction decoder 44 are sent to abort condition generation circuits 45, 46, and 47, respectively.

Here, the abort condition generation circuit 45 generates abord conditions for four instructions including a branch instruction. Further, the abort condition generation circuit 46 generates the next four abort conditions for the four instructions including the branch instruction. Further, the abort condition generating circuit 47 generates the next four abort conditions following the four instructions including the branch instruction.

The output of the abort condition generation circuit 45 is outputted as an E stage condition abort signal 481 and 1
, multiplexer 49], the D stage condition abort signal 482, and the multiplexer 492, the F stage condition abort signal 483 can be output. signal 482,
The output of the abort condition generation circuit 47 can be output as the F stage condition abort signal 483 through the multiplexer 492, and the output of the abort condition generation circuit 47 can be output as the F stage condition abort signal 483 through the multiplexer 492.

In this case, the multiplexers 491 and 492 are controlled by the control circuit 50 based on the signal 501 indicating that a fetch has been performed, and the control algorithm for the multiplexers 491 and 492 here is as follows. .

The E-stage conditional abort signal 481 outputs the conditional abort flags of four instructions including the branch instruction generated by the abort condition generation circuit 45 as they are. □ Also, the conditional abort signal 482 of the D stage causes the multiplexer 491 to be activated if no fetch is performed at least once during branch determination (from when the branch instruction is decoded at the D stage until execution is completed at the E stage). The conditional abort flags of four instructions including the branch instruction generated by the abort condition generation circuit 45 are outputted through the multiplexer 491, and when a fetch is performed once during branch determination, the conditional abort flags are generated by the abort condition generation circuit 46 through the multiplexer 491. The next four conditional abord flags for the four instructions containing the branch instruction are output. Further, the F stage conditional abort signal 183 outputs conditional abort flags of four instructions including the branch instruction generated by the abort condition generation circuit 45 via the multiplexer 492 if no fetch is performed at the time of branch determination. When a fetch is performed once at the time of branch determination, the next four conditional abord flags of the four instructions including the branch instruction generated by the abort condition generation circuit 46 are outputted via the multiplexer 492, When the fetch is performed twice, four conditional abort flags following four instructions including a branch instruction generated by the abort condition generation circuit 47 are outputted via the multiplexer 492.

Next, the operation of the embodiment configured as above will be explained.

First, a case will be described in which a delayed branch instruction using the delayed branch method is executed.

Here, a conditional abort flag is added to an assembler code using a delayed branch instruction, for example, as shown below.

Step assembler code abort flag 1
addi rl ro l alex2
addj r2 ro 2 alex
3 addj r3 ro 3 al
ex4 beq r29r20 xi
alex5 addi r4 ro 4
alex6 addi r5 ro
5 brad7 addi rat
ro 6 brad8 addi r7
ro 7 brad9 addi
r8 ro 8 bradl 0 ad
di rlOro 10 brad In other words, here, the conditional abort flag alex (always executed) is added to the instructions in steps 1 to 3, and step 4
When the delayed branch instruction beq is given in step 5, the conditional abort flag alex is set until the delayed instruction in step 5.
(always execute) is added, and a conditional abort flag brad (abort if branched) is added to instructions after step 6. As a result, when the delayed branch instruction beq is given, the next step instruction is executed, and then the branch destination instruction is executed.

FIG. 4 shows a specific example of the operation performed by the superbus machine in response to a delayed branch instruction.

In this case, among a series of instructions, instruction 2 is a branch instruction, instruction 13 is a branch destination instruction, instruction 3 is a delay instruction, and the conditional abort flags for instructions 1 to 3 are alex
(always executed), and the conditional abort flags for instructions 4 to 12 are brad (abort if branched).

In this case, the plurality of instructions fetched by the fetch circuit 1 are latched into the instruction buffer 2 and sent to the instruction supply device 3 and the conditional abort generation circuit 4.

The conditional abort generation circuit 4 decodes a plurality of instructions using a branch instruction decoder 44 and determines that instruction 2 is a delayed branch instruction. This determination result is then sent to the abort condition generation circuits 45, 46, and 47.

Then, the abort condition generation circuit 45 generates conditional abord flags for instructions 1 to 4 as abord conditions for the four instructions including the branch instruction, and the abort condition generation circuit 45 generates the condition abord flags for instructions 1 to 4 as the abord conditions for the four instructions including the branch instruction. Conditional abord flags for instructions 5 to 8 are generated as the next four abord conditions, and the abort condition generation circuit 47
Then, conditional abord flags for instructions 9 to 12 are generated as the next four abord conditions for the four instructions including the branch instruction.

Then, instruction 1 generated by the abort condition generation circuit 45
The abord flags of instructions 5 to 4 are output to the first stage pipeline as the E stage condition abort signal 481, and the abord flags of instructions 5 to 8 generated by the abort condition generation circuit 46 are output to the D stage via the multiplexer 491. The abort flags for instructions 8 to 12, which are output as stage condition abort signals 482 to the second stage pipeline and generated by the abort condition generation circuit 47, are sent to the multiplexer 49.
3 as F stage condition abort signal 483 via 2
Output to the pipeline stage.

On the other hand, from the instruction buffer 2, the instruction supplier 3
When a plurality of instructions are given to the execution unit 5, the instruction supply device 3 supplies the instructions to each execution unit 5.

Then, in each execution unit 5, the instruction is decoded by the decoder 51 of the D stage, and the (D) stage valid signal 521 is sent to the AND circuit 53 of the (D) stage.
The E) stage valid signal 523 is now given to the AND circuit 55 of the (E) stage.

In this case, in the execution unit 5 corresponding to instruction 1, the abord flag of the E stage condition abort signal 481 is set to al
ex (always executed), barnch-tak at this time
Since en522 indicates that there is no branch, the output of the abord determination circuit 56 at this time causes the (E) stage valid signal 523 to be output as is through the AND circuit 55, and is given to the register file 57 as a write enable signal. The calculation based on the contents of 57 is executed in the calculation unit 58 of the (E) stage.

Also, the execution unit 5 corresponding to the branch instruction of instruction 2
Also, the abord flag is alex (always run)
At this time, the barnch-1aken 523 indicates that there is no branching, so the calculation at the (E) stage is executed in the same manner as described above. Furthermore, for execution unit 5 corresponding to the delay instruction of instruction 3, the abord flag is alex (always executed), and barnc at this time is
Since h-taken 522 indicates that there is no branch, the operation at stage (E) is executed in the same manner as described above. Then, in execution unit 5 corresponding to instruction 4, the abord flag is brad (abort if branched)
Since the barnch-taken 522 at this time indicates that the branch is to be taken, the AND circuit 55 negates the (E) stage valid signal 523 based on the output of the abord determination circuit 56 at this time, so that the execution of the instruction is aborted. Become.

Hereinafter, in the same way as described above, instructions 5 to 8 are also aborted in each execution unit 5 based on the relationship between the abord flag of the D stage condition abort signal 482 and barnch-taken 522, and further instructions 9 to 12 are aborted.
Regarding the F stage condition abort signal 483, the abord flag and barnch-1aken.

523, the execution of instructions in each execution unit 5 is aborted, allowing the superscalar machine to execute a delayed branch instruction.

Next, FIG. 5 shows another example of operation in response to a delayed branch instruction by the superbus machine.

In this case, among a series of instructions, instruction 4 is a branch instruction, instruction 13 is a branch destination instruction, and instruction 5 is a delay instruction, and the conditional abort flags for instructions 1 to 5 are alex
(always executed), and the conditional abort flags for instructions 6 to 12 are brad (abort if branched).

Even in this case, the delayed branch instruction can be executed by the superfluous machine in the same way as described above.

Further, FIG. 6 shows still another example of operation in response to a delayed branch instruction by a superfluous machine.

In this case, among a series of instructions, instruction 3 is a branch instruction, instruction 13 is a branch destination instruction, instruction 4 is a delay instruction, and the conditional abort flags for instructions 1 to 4 are alex
(always executed), and the conditional abort flags for instructions 5 to 12 are brad (abort if branched). Also, here, instruction 3 is a branch order, but there is a dependency between instruction 3 and instruction 4, and instruction 4
will be executed after one cycle.

In this case, the abord flag generated by the abort condition generation circuit 45 is output as the E stage condition abort signal 481 and is also outputted as the D stage condition abort signal 482 via the multiplexer 491, and the abort flag generated by the abort condition generation circuit 46 is The generated abord flag is outputted as the F stage condition abort signal 483 via the multiplexer 492.

Even in this case, the delayed branch instruction can be executed by the superscalar machine in the same way as described above.

Next, a case will be described in which a squash branch instruction using the squash branch method is executed.

Again, the execution sequence for the assembler code using delayed branch instructions is given as follows, for example.

Step assembler code abort flag 1
addlrl ro 1 alex2
addi r2 ro 2 alex3
addi r3 ro 3 ale
x4 5beq r29 r20 xi
alex5 addi r4 ro 4
brex6 addi r5 ro 5
brad7 addi re rO
B brad8 addi r7 r
o 7 brad9 addi r8
ro 8 bradl 0 ad+Hr
lOro 10 bradIn other words, here, the conditional abort flag a is set for instructions from steps 1 to 3.
lex (always execute) is added and a squash branch instruction 5beq is given in step 4, step 5
Conditional abort flag old ex (run after branching)
is added, and a conditional abort flag brad (abort if branched) is set for instructions after step 6.

As a result, when a squash branch instruction 5beq is given, when branch not ticked, the next next instruction is executed without executing the instruction after the branch instruction, and when branch ticked, the branch instruction is executed. The next instruction will be executed and the branch destination instruction will be executed.

FIG. 7 shows a specific example of the operation of the superscalar machine in response to a squash branch instruction.

In this case, among a series of instructions, instruction 2 is a squash branch instruction, instruction 13 is a branch destination instruction, instruction 3 is a delay instruction, and the conditional abort flags of instructions 1 and 2 are ale.
x (always executed), and the conditional abort flag of instruction 3 is b
rex (execute if branched), and the conditional abort flags for instructions 4 to 12 are brad (abort if branched).

In this case as well, in the execution unit 5 corresponding to the instruction 1 and the squash branch instruction 2, the abord flags of the E stage condition abort signal 481 are all alex (always executed), and the barnch-t
Since the aken 522 indicates that there is no branching, the output of the abord determination circuit 56 at this time causes the reand circuit 55 to output the (E) stage valid signal 523 as it is, and gives it to the register file 57 as a write enable signal. The calculation based on the contents of is executed in the calculation section 58 of the (E) stage.

As for the execution unit 5 corresponding to the delayed instruction of instruction 3, the abord flag is blex (execute if branched), so the barnch-tak at this time is
If cn522 indicates a branch-not-tick that does not branch, do not execute instruction 3 and proceed to instruction 4. On the other hand, if barnch-taken522 indicates a branch-tick that does not branch, execute instruction 3. Then proceed to instruction 4. Then, in the execution unit 5 corresponding to instruction 4, the abord flag is brad (abort after branching), and at this time barnc'h-1ake
Since n522 indicates branching, the corresponding output of the abord determination circuit 56 causes the AND circuit 55 to execute (E).
The stage valid signal 523 is negated, and execution of the instruction is aborted.

Hereinafter, in the same way as described above, instructions 5 to 8 are also aborted in each execution unit 5 based on the relationship between the abord flag of the D stage condition abort signal 482 and barnch-taken 522, and further instructions 9 to 12 are aborted.
Also, due to the relationship between the abord flag of the F stage condition abort signal 483 and the barnch-1aken 522, the execution of instructions in each execution unit 5 is aborted, and the squash branch instruction can be executed by the superpower machine.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be implemented with appropriate modifications without changing the gist.

[Effects of the Invention] The parallel processing computer of the present invention is capable of executing a plurality of instructions at the same time. a flag adding means for adding a flag indicating an abort condition to each instruction, a flag indicating an abort condition added to each of the above instructions, and an abort execution means for aborting the execution of each instruction depending on the success or failure of each of the above branch instructions. Therefore, it is now possible to abort the execution of each instruction based on the relationship between the abort condition flag added to each instruction based on a delayed branch instruction or a scanned branch instruction and the success or failure of the branch instruction. Even in a superscalar type processor, You can perform delayed branches and squash branches,
Since it is possible to maintain object compatibility with programs of RISC type processors, it is possible to effectively utilize abundant software assets and achieve high-speed processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing an execution unit used in the embodiment, and FIG. 3 is a block diagram showing a conditional abort used in the embodiment. Block diagrams showing the determination circuit, FIGS. 4 to 7, are diagrams for explaining the same embodiment. 1... Fetch circuit, 2. Instruction huffer, 3... Instruction supplier, 4... Condition abort generation circuit, 44... Branch instruction decoder, 45.46.4
7... Abort condition generation circuit, 491.492... Multiplexer, 50... Control circuit, 5... Execution unit, 51... Decoder, 52], 523... Alit signal, 52.55... Oand circuit, 54
．． 56...Abort judgment circuit, 57...Register file. Applicant's agent, patent attorney Takehiko Suzue! Abort flag lex lex dan1eX 1+raj br<J ri rad br6 br仄Δ rJ brnecessary branch destination instruction Figure 7

Claims (1)

[Claims] In a parallel processing computer that can execute multiple instructions simultaneously, a delayed branch instruction or a squash branch instruction is determined from among the multiple instructions, and an abort condition is indicated to each instruction based on the result of this determination. The present invention is characterized by comprising a flag adding means for adding a flag, and an abort execution means for aborting the execution of each instruction based on the relationship between the flag added to each of the instructions indicating an abort condition and the success or failure of each of the branch instructions. Parallel processing computer.