JPH08339299A - Pipeline processor - Google Patents

Abstract

PURPOSE: To eliminate the disturbance of a pipeline by calculating a branching address before a branching position. CONSTITUTION: This pipeline processor is provided with a counter part 4 for holding a counter value. The counter value is initialized to an instruction number to the change point of control supplied by a preliminarily announced branching instruction. The counter value is decreased synchronized with the increase of a program counter 2. The counter part 4 compares the counter value with a prescribed threshold value. Corresponding to a compared result by the counter part 4, one of the address of a successive instruction and the branching destination address of the preliminarily announced branching instruction is selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline processor capable of pipeline processing a plurality of instructions.

[0002]

2. Description of the Related Art Almost all processors currently in practical use pipeline a plurality of instructions. The pipeline processing is to process a plurality of instructions in parallel by dividing the instruction execution process into a plurality of stages and overlapping the plurality of stages. This improves the performance of the processor.
A processor that performs such pipeline processing is called a pipeline processor.

In order to execute a branch instruction, the pipeline processor recognizes that the instruction is a branch instruction by fetching and decoding the instruction, and determines the condition for branching. After calculating the address of the branch destination, it is necessary to change the address of the instruction to be fetched next. However, when changing the address of the next instruction to be fetched for a branch instruction, the sequential instruction following that branch instruction has already been fetched, and the instruction fetched by mistake is discarded and the instruction at the branch destination is fetched. I have to do it. The number of cycles spent until the instruction fetched by mistake is discarded and the instruction at the branch destination is fetched again is the delay caused by the execution of the branch instruction.

Branch instructions that modify the flow of control significantly degrade the performance of pipeline processors. Branch instructions impede smooth instruction supply to the pipeline,
This is because it causes turbulence in the pipeline.

In a general application program, the proportion of branch instructions in all instructions is 20% to 30%.
Is. 3 by executing one branch instruction
Given the loss of cycles, the total performance of a pipeline processor is 6
The deterioration is 0% to 90%. This is because the pipeline is disturbed by the execution of the branch instruction.

As described above, the delay (penalty) associated with the execution of the branch instruction is a major factor that deteriorates the performance of the pipeline processor.

There are roughly two approaches to prevent pipeline turbulence. One is an approach to prevent turbulence in the pipeline by eliminating the delay in condition judgment. The other is an approach to prevent the pipeline from being disturbed by eliminating the delay in the calculation of the branch destination address.

Various branch prediction methods are known as methods for eliminating the delay in condition judgment. However, there are few effective methods for eliminating the delay in the calculation of the branch destination address.

As one method of eliminating the delay in the calculation of the branch destination address, the branch target buffer (B
Ranch Target Buffer; BT
(Abbreviated as B). In this method, the branch destination address calculated previously is stored in the BTB, and the branch destination address is reused. According to this method, it becomes possible to acquire the branch destination address of the branch instruction before decoding the branch instruction.

FIG. 11 shows the configuration of a conventional processor using BTB. As shown in FIG. 12, BTB10
Has an area 41 for storing a tag, an area 42 for storing a branch destination address, and an area 43 for storing a branch history. When the branch instruction is executed, the upper bits of the address of the branch instruction in the instruction memory 1 are stored in the area 41, the branch destination address of the branch instruction is stored in the area 42, and the branch history of the branch instruction is stored in the area 43. Stored in.
The row positions of the areas 41, 42 and 43 in the BTB 10 are determined according to the lower address of the branch instruction.

The program counter 2 stores an address of an instruction to be fetched next (hereinafter referred to as a PC address). Lower bits of PC address (for example,
BTB10 is referred to by using (8 bits) as an index, and the upper bits of the PC address and the area 41 of BTB10
Is compared to the tags stored in.

A match between the upper bits of the PC address and the tag stored in the area 41 of the BTB 10 indicates that the branch instruction corresponding to the PC address has been executed before. The branch destination address of the branch instruction is BTB10.
Are stored in the corresponding area 42 in the. Therefore,
When the upper bit of the PC address matches the tag stored in the area 41 of the BTB 10, the branch destination address stored in the area 42 of the BTB 10 is output to the instruction memory 1 instead of the PC address. It should be noted that the branch history stored in the area 43 of the BTB 10 is taken into consideration in determining whether to output the branch destination address stored in the area 42 of the BTB 10 to the instruction memory 1 instead of the PC address. Good. The branch history can be used to predict whether a branch will occur.

When the upper bits of the PC address do not match the tag stored in the area 41 of the BTB 10, the PC address is output to the instruction memory 1 in the same manner as the normal instruction fetch cycle.

As described above, when the upper bits of the PC address and the tag stored in the area 41 of the BTB 10 match, the branch destination address of the branch instruction can be acquired in the same cycle as the instruction fetch cycle. it can. This means that the calculation of the branch destination address is completed before the instruction decoding cycle.

Another method for eliminating the delay in the calculation of the branch destination address is architecturally a delayed branch (D
There is a method of defining an emissive branch).
This method eliminates the delay in the calculation of the branch destination address by executing a predetermined number of instructions following the branch instruction regardless of whether the branch actually occurs.

[0016]

In the method using the BTB described above, the BTB requires a large amount of memory. BTB should be at least 10 for practical effect.
It requires 24 entries. This corresponds to a memory of 6 to 7 kilobytes and occupies a very large area on the chip. Further, in order to prevent the disturbance of the pipeline, it is necessary to access the BTB within one cycle. This is a major factor limiting the operating speed of the processor.

In the delay branch method described above, the performance of the delay branch depends on how many valid instructions the compiler can fill the delay slot. An instruction that fills the delay slot is an instruction that is executed regardless of whether or not there is a branch, so it must not be an instruction that affects the branch condition. In general, it is not easy for a compiler to find such an instruction. This is because it is difficult to determine whether or not the instruction affects the branch condition before actually executing the instruction.

When the number of cycles required to fetch one instruction is 1, it is possible to fill about 90% of the delay slots with valid instructions. However, as the number of cycles required to fetch one instruction increases, it becomes difficult to fill the delay slot with valid instructions. This is because the number of instructions that should fill the delay slot increases. Therefore, it is difficult to apply the delayed branch method to a multi-stage pipeline processor or superscalar machine.

If the delay slot cannot be filled with valid instructions, then the compiler fills the delay slot with N
Fill with OP instruction. This redundantly increases the program size.

An object of the present invention is to provide a pipeline processor which does not cause a delay due to the execution of branch instructions without affecting a large amount of memory or operating speed. Another object of the present invention is to provide a pipeline processor that does not cause a delay due to execution of a branch instruction even when the number of cycles required to fetch one instruction increases.

[0021]

Means for Solving the Problems The pipeline of the present invention
The processor is a pipeline processor that executes a predictive branch instruction that defines the number of at least one instruction that should be executed subsequent to the predictive branch instruction before changing control flow, and the processor A program counter for holding an address, an instruction memory for outputting an instruction corresponding to an address held by the program counter, an instruction register for fetching and holding an instruction output from the instruction memory, and an instruction register for holding the instruction register An instruction decoding unit that identifies whether the instruction is the advance notice branch instruction by decoding the instruction, and a counter unit that holds a counter value and compares the counter value with a predetermined threshold value. And the counter value is initialized to the number of instructions defined by the advance branch instruction,
The counter value is decremented in synchronization with the increment of the program counter;
Comparison of the adder that increments the address held by the program counter and provides the incremented address as a sequential instruction address, the branch destination address register that provides the branch destination address of the advance notice branch instruction, and the counter unit A selector for selecting one of the sequential instruction address and the branch destination address of the advance notice branch instruction according to the result is provided, thereby achieving the above object.

The advance notice branch instruction is executed after the advance notice branch instruction until the control flow is changed, an area for storing an operation code for identifying the type of the instruction, an area for specifying the branch destination address. At least one to be done
And an area for storing the number of one instruction.

The predetermined threshold is equal to the number of cycles required to fetch one instruction.

The counter unit may output a selection signal for selecting a branch destination address of the advance notice branch instruction to the selector when the counter value matches the predetermined threshold value.

The counter section outputs a selection signal for selecting a branch destination address of the advance notice branch instruction to the selector when the number of instructions defined by the advance notice branch instruction is smaller than the predetermined threshold value. May be.

The counter section outputs a signal for canceling the instruction held in the instruction register to the instruction register when the number of instructions defined by the advance branch instruction is smaller than the predetermined threshold value. May be.

The pipeline processor further includes a condition judging unit for judging whether or not to change the control flow for the advance notice branch instruction, and the counter unit sets the counter value to a predetermined value. When it reaches, a signal defining the timing for determining whether to change the control flow for the advance notice branch instruction may be output to the condition determining unit.

When the condition judging unit judges that the control flow of the advance notice branch instruction is not changed, the condition judging unit outputs a signal for canceling the instruction held by the instruction register to the instruction register to decode the instruction decode. A signal for canceling the instruction decoded by the unit may be output to the instruction decoding unit.

The operation will be described below.

According to the pipeline processor of the present invention, the actual change of the control flow does not occur immediately at the time of fetching and decoding the instruction indicating the change of the control flow, but indicates the change of the control flow. It occurs after the number of instructions up to the change in control flow encoded in the instruction. On the other hand, the control change destination address can be calculated at the time when the instruction for changing the control flow is decoded, and is already prepared at the time when the actual control is changed. Therefore, at the time of changing the control flow (that is, changing the fetch destination), the fetch destination can be changed promptly, and a sequential instruction that has already been erroneously fetched, such as a conventional branch instruction, is discarded and the branch destination is discarded. It is not necessary to fetch the instruction of.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the structure of a pipeline processor 100 according to the present invention.

The program counter 2 holds the address 101 of the instruction to be fetched next. The program counter 2 outputs the held address 101 to the instruction memory 1. The instruction memory 1 stores a plurality of instructions. Of the multiple instructions stored in the instruction memory 1,
The instruction 102 designated by the address 101 output from the program counter 2 is fetched into the instruction register 8 and held there.

Various types of instructions can be stored in the instruction memory 1. Those instructions are classified into sequential instructions and branch instructions.

In this specification, the "sequential instruction" is defined as an instruction that does not change the control flow. Therefore, after the sequential instruction, the instruction corresponding to the address next to the address of the instruction memory 1 in which the sequential instruction is stored is executed. A "branch instruction" is defined as an instruction that changes the flow of control. Therefore, "branch instruction" means conditional branch instruction, unconditional jump instruction, subroutine call instruction,
Including a return instruction.

FIG. 2 shows the pipeline processor 100.
Shows the format of the branch instruction used in. In this specification, the branch instruction shown in FIG. 2 is referred to as a “preliminary branch instruction”. The "predictive branch instruction" is an instruction that executes a predetermined number of instructions from the predictive branch instruction and then branches to the branch destination address. The predetermined number is given as an operand of the advance notice branch instruction.

For example, the "predictive branch instruction that branches to the instruction X after executing two instructions" is expressed as "Branch after 2 to X" in the program code. The address of the instruction X is calculated in the pipeline processor 100 as the branch destination address of the branch instruction.

The advance notice branch instruction has an area 21 for storing an operation code, an area 22 for designating a branch destination address, and at least one that should be executed following the advance notice branch instruction by the change point (branch point) of the control flow. Area 23 for storing the number of one instruction.

The operation code is a code for identifying the type of instruction. The opcode is usually composed of multiple bits.

The branch destination address is designated in the direct addressing mode or the indirect addressing mode.

In the direct addressing mode, the branch destination address is designated by the absolute address. in this case,
The area 22 stores a code indicating the direct addressing mode and an absolute address.

In the indirect addressing mode, the branch destination address is designated by the relative address with respect to the base address. In this case, the area 22 stores a code indicating the indirect addressing mode and a relative address (displacement from the advance branch instruction to the branch point). An address held in the program counter 2 is typically used as the base address. However, an address held in another register may be used as the base address.

The number of instructions from the currently executed instruction to the change point (branch point) of the control flow is designated by 0 or a positive integer. 0 or a positive integer is given as the operand of the advance notice branch instruction. For example, the advance notice branch instruction may be “Branch after 2 to X” in program code.
2 ”is stored in the area 23.

Referring again to FIG. 1, the instruction 102 held in the instruction register 8 is supplied to the instruction decoding unit 3 and the branch destination address calculating unit 7 as the output 103 of the instruction register 8.

The instruction decoding unit 3 identifies the type of the instruction 103 by decoding the instruction 103. Instruction 1
The 03 type identification is achieved by identifying the opcode stored in the head area of the instruction 103.

When the instruction decoding unit identifies that the instruction 103 is a sequential instruction, the information 106 indicating the type of the instruction 103 is supplied to the executing unit 11, and the information 107 indicating the register designated in the instruction 103 is registered. It is supplied to the file 12. The value of the register designated by the information 107 is supplied to the execution unit 11 as the information 108. For example, when the instruction 103 is an instruction “add the value of register 2 to the value of register 1 and store the addition result in register 1”, as the information 106 indicating the type of instruction 103, “add instruction The information indicating "
1 is supplied to the register file 12 as the information 107 indicating the register designated by the instruction 103.

The execution unit 11 executes the instruction based on the information 106 from the instruction decoding unit 3 and the information 108 from the register file 12. The execution result by the execution unit 11 is output to the register file 12 as the output 109, if necessary.

When the instruction decoding unit 3 identifies that the instruction 103 is the advance notice branch instruction, the instruction decoding unit 3
The initial value setting signal 104 is supplied to the counter unit 4, and the value stored in the area 23 of the advance notice branch instruction is supplied to the counter unit 4 as the initial value 105. The initial value setting signal 104 has a high level in the cycle for setting the initial value 105 in the counter unit 4, and has a low level otherwise.

The counter section 4 holds the count value.
The count value is used to define the branch timing of the advance notice branch instruction. The count value is, for example, an integer. The count value held in the counter unit 4 is initialized to the initial value 105 in response to the initial value setting signal 104.
The initial value 105 is a value stored in the advance notice branch instruction area 23. The count value held in the counter unit 4 is decremented by 1 in response to the signal 110 from the program counter 2. The signal 110 is output to the counter unit 4 in synchronization with the value of the program counter 2 being incremented by 1.

The counter section 4 compares the counter value held in the counter section 4 with a predetermined threshold value. When the counter value and the predetermined threshold value match, the counter unit 4 outputs the high-level selection signal 111 to the selector 5 and the high-level cancel signal 116 to the instruction register 8. In other cases, the counter unit 4
Outputs a low-level selection signal 111 to the selector 5, and outputs a low-level cancel signal 116 to the instruction register 8. The selection signal 111 is used to change the address of the instruction to be fetched next to the address of the branch destination. The cancel signal 116 is used to cancel the instruction fetched in the instruction register 8.

The selector 5 selects one of the output 112 of the adder 9 and the output 113 of the branch destination address register 6 according to the level of the selection signal 111. Selection signal 1
When the level of 11 is high level, the selector 5
Selects the output 113 of the branch destination address register 6.
When the level of the selection signal 111 is low,
The selector 5 selects the output 112 of the adder 9. The output 115 of the selector 5 is supplied to the program counter 2.

The branch destination address register 6 is supplied with the calculation result (that is, the branch destination address of the advance notice branch instruction) 114 by the branch destination address calculator 7. The branch destination address register 6 supplies the calculation result 114 as the output 113 to the selector 5. The branch destination address register 6 is
The branch destination address of the advance notice branch instruction is provided to the program counter 2 via the selector 5.

The adder 9 increments the value of the program counter 2 by 1 and supplies the incremented value to the selector 5 as the output 112. Adder 9
Is used to calculate the address of the instruction following the sequential instruction.

Program counter 2 to address 101
Command 1 corresponding to the address 101 after
The process until 02 is fetched into the instruction register 8 is called “instruction fetch”.

The process executed by the instruction decoding unit 3 is called "instruction decoding". The process from the start of the calculation of the branch target address by the branch target address calculation unit 7 until the calculation result is stored in the branch target address register 6 is called “branch target address calculation”. pipeline·
The processor 100 executes "instruction decoding" and "calculation of branch destination address" in the same cycle.

The process in which the execution unit 11 executes an instruction based on the information 106 and the information 108 is called "instruction execution". In addition, the process in which the execution unit 11 stores the information 109 in the register file 12 is called “write back”.

In this way, the pipeline processor 1
The process at 00 is executed by repeating “instruction fetch”, “instruction decode”, “instruction execution”, and “writeback”.

FIG. 3 shows the configuration of the counter section 4. The counter unit 4 includes a down counter 3 that holds a counter value Z.
Contains 1.

An initial value 105 and an initial value setting signal 104 are input to the down counter 31. The counter value Z held in the down counter 31 is the initial value setting signal 10
When the level of 4 is a high level, it is initialized to the initial value 105. As described above, the initial value 105 is equal to the number of instructions from the advance notice branch instruction to the branch point stored in the advance notice branch instruction area 23. Hereinafter, it is assumed that the initial value 105 is equal to the value B.

The signal 110 is further input to the down counter 31. The counter value Z held in the down counter 31 is decremented by 1 in response to the signal 110. The counter value Z is output to the comparator 33.

In the comparator 33, the counter value Z is the threshold value A.
It is determined whether or not. The threshold value A is supplied from the threshold value setting unit 32. The threshold value A is set in the threshold value setting unit 32 in advance so as to be equal to the number of cycles required to fetch one instruction (hereinafter referred to as the instruction fetch cycle number). The comparator 33 supplies a high level signal to one input of the OR circuit 36 when the counter value Z is equal to the threshold value A, and supplies a low level signal to one input of the OR circuit 36 otherwise. Supply to the input of. The other input of the OR circuit 36 is connected to the AND circuit 3
7 outputs are provided.

The subtractor 34 subtracts the threshold value A from the initial value B. The subtraction result Y is supplied to the determination unit 35 and the control signal generation unit 38.

The judging section 35 judges whether the calculation result Y is smaller than 0 or not. The determination unit 35 supplies a high level signal to one input of the AND circuit 37 when the operation result Y is smaller than 0, and otherwise supplies a low level signal to one input of the AND circuit 37. Supply. The initial value setting signal 104 is supplied to the other input of the AND circuit 37.

In this way, (B <A) or (Z =
Only in the case of A), the output of the OR circuit 36 becomes high level, and in other cases, the output of the OR circuit 36 becomes low level. As a result, (B <A) or (Z =
Only in the case of A), the output 113 of the branch destination address register 6 is output from the selector 5. In other cases, the selector 112 outputs the output 112 of the adder 9.

The control signal generator 38 uses the initial value setting signal 1
The cancel signal 116 is generated according to 04 and the subtraction result Y.

FIG. 4A shows a configuration example of the control signal generator 38 when the number of instruction fetch cycles is three. Even if the number of instruction fetch cycles is other than 3,
The control signal generation circuit 38 can be configured in the same manner as the control signal generation circuit 38 shown in FIG.

The control signal generating section 38 includes counters 51-5.
3, a logic circuit 54, and a selector 55.

The counters 51 to 53 have the initial value setting signal 1
A signal is output in response to 04. The outputs of the counters 51 to 53 are input to the input terminals Y _{1 to} Y ₃ of the selector 55 via the logic circuit 54, respectively.

The selector 55 outputs one of the three signals input to the input terminals Y _{1 to} Y ₃ according to the value of the subtraction result Y input from the subtractor 34. Selector 55
Outputs a signal input to the input terminal Y ₁ when Y = 1, outputs a signal input to the input terminal Y ₂ when Y = 2, and outputs Y = 3 Input terminal Y
Outputs the signal input to ₃ . The output of the selector 55 is supplied to the instruction register 8 as the cancel signal 116.

FIG. 4B shows the output waveforms of the counters 51 to 53 and the output waveform of the selector 55. In the cycle in which the output of the selector 55 becomes high level, the instruction held in the instruction register 8 is canceled.

FIG. 5A shows an example of a program code string including a notice branch instruction. In FIG. 5A, I ₁ ,
I ₂ , I ₄ , I ₅ , and I ₆ indicate sequential instructions, I ₃ indicates a notice branch instruction “Branch after 3 to X”, and X indicates a branch destination instruction of the notice branch instruction.

FIG. 5B shows the pipeline processor 100 when executing the advance notice branch instruction I _{3 in} which the number of instruction fetch cycles is 2 and the number of instructions from the current execution instruction to the branch point is 3. 3 is a time chart showing the operation of FIG. In this case, A = 2 and B = 3.

In FIG. 5B, IF _{1 to} IF ₂ indicate instruction fetch cycles, ID indicates instruction decode cycles, EX indicates instruction execution cycles, and WB indicates write back cycles.

In cycle C ₃ , the predictive branch instruction I ₃ is decoded by the instruction decoding unit 3. As a result, the value (B = 3) stored in the area 23 of the advance notice branch instruction I ₃ is input to the down counter 31 (FIG. 3) as the initial value 105. Counter value Z held in the down counter 31
Is initialized to 3. The counter value Z held in the down counter 31 is decremented by 1 in each cycle C _{4 to} C ₆ .

In cycle C ₄ , down counter 31
The counter value Z held in the table and the threshold value (A = 2) set in the threshold value setting unit 32 (FIG. 3) match. As a result, in cycle C ₄ , the selection signal 111 becomes high level, and the output of the selector 5 switches from the output 112 of the adder 9 to the output 113 of the branch destination address register 6.

In FIG. 5B, S indicates that the output 115 of the selector 5 is the output 112 (sequential instruction address), and B indicates that the output 115 of the selector 5 is the output 113 (branch destination address). Show.

FIG. 6 shows the operation of the pipeline processor 100 when executing the advance notice branch instruction I _{3 in} which the number of instruction fetch cycles is 3 and the number of instructions from the current execution instruction to the branch point is 3. It is a time chart shown. In this case, A = 3 and B = 3.

In FIG. 6, IF _{1 to} IF ₃ indicate instruction fetch cycles, ID indicates instruction decode cycles, EX indicates instruction execution cycles, and WB indicates write back cycles.

In cycle C ₃ , down counter 31
The counter value Z held in (FIG. 3) is initialized to 3. The counter value Z held in the down counter 31 is
It is decremented by 1 in each cycle C _{4 to} C ₆ .

In cycle C ₃ , down counter 31
The counter value Z held in the threshold value and the threshold value (A = 3) set in the threshold value setting unit 32 (FIG. 3) match. As a result, in cycle C ₃ , the selection signal 111 becomes high level, and the output of the selector 5 switches from the output 112 of the adder 9 to the output 113 of the branch destination address register 6.

In FIG. 6, S is the output 11 of the selector 5.
5 indicates the output 112 (sequential instruction address), and B indicates that the output 115 of the selector 5 is the output 113 (branch destination address).

In this way, the pipeline processor 1
According to 00, when A ≦ B, no delay occurs due to the execution of the branch instruction. Therefore, the pipeline is not disturbed.

FIG. 7 shows the operation of the pipeline processor 100 when executing the advance notice branch instruction I _{3 in} which the number of instruction fetch cycles is 3 and the number of instructions from the current execution instruction to the branch point is 2. It is a time chart shown. In this case, A = 3 and B = 2.

In FIG. 7, IF _{1 to} IF ₃ indicate instruction fetch cycles, ID indicates instruction decode cycles, EX indicates instruction execution cycles, and WB indicates write back cycles.

The value (B = 2) given as the initial value 115 in the cycle C ₃ is smaller than the number of instruction fetch cycles (A = 3). As a result, in cycle C ₃ , the selection signal 111 becomes high level, and the output of the selector 5 switches from the output 112 of the adder 9 to the output 113 of the branch destination address register 6.

In FIG. 7, S is the output 11 of the selector 5.
5 indicates the output 112 (sequential instruction address), and B indicates that the output 115 of the selector 5 is the output 113 (branch destination address).

In this way, the pipeline processor 1
According to 00, when A> B, a delay occurs due to the execution of the advance notice branch instruction. However, in the example shown in FIG. 7, the number of delayed cycles is one. On the other hand, A
= 3, the number of cycles delayed by the execution of the conventional branch instruction is 3 (see FIG. 8).

In this way, the pipeline processor 1
According to 00, the delay caused by the execution of the predictive branch instruction can be made smaller than before. This minimizes pipeline turbulence.

Next, the timing for determining the branch condition of the advance notice branch instruction will be described. As shown in FIGS. 5B, 6, and 7, the counter value Z held in the down counter 31 (FIG. 3) becomes 0 in the instruction execution (EX) cycle of the advance notice branch instruction I ₃ . It is the next cycle of the cycle.
This means that the timing for judging the branch condition of the advance notice branch instruction I ₃ is postponed according to the number of instructions (B) from the current execution instruction to the branch point. Accordingly, even if the sequential instruction following the advance notice branch instruction has an influence on the determination of the branch condition of the advance notice branch instruction, the branch condition can be accurately determined.

The timing for judging such a branch condition can be defined by providing the judgment circuit 39 (FIG. 3) in the counter section 4.

The determination circuit 39 determines whether or not the counter value Z held in the down counter 31 matches 0. The determination circuit 39 outputs a high level signal 117 when the counter value Z held in the down counter 31 matches 0, and otherwise outputs a low level signal 1.
17 is output. The signal 117 is supplied to the condition determination unit 13.

FIG. 9 shows the structure of the condition judging unit 13. The condition determination unit 13 determines whether or not to change the flow of control for the advance notice branch instruction (that is, whether to branch to the branch destination address).

The condition judging unit 13 includes a condition code 61 and a branch condition judging unit 62 for judging the value of the condition code 61 according to the branch condition defined by the operation code stored in the advance notice branch instruction area 21. ,
AND circuit 63.

The execution section 11 updates the value of the condition code 61 according to the execution result 109. For example, the condition code 61 is Z (1 bit), N (1
Bit), V (1 bit), and C (1 bit). Z indicates a zero flag, N indicates a negative flag, V indicates an overflow flag,
C indicates a carry flag. Each of these flags has a value of 0 or 1, for example. The values of these flags are updated by the execution unit 11.

The operation code stored in the area 21 of the advance notice branch instruction is input to the branch condition judging section 62 from the instruction decoding section 3.

Table 1 shows the types of opcodes stored in the advance branch instruction area 21. In this example, the opcode consists of 3 bits. Of course, the opcode is 3
It may be composed of bits other than bits.

[0097]

[Table 1]

For example, the operation code "100" is "Br
anch on not equal (branch to a branch address if the condition that the value of the zero flag Z of the condition code 61 is not zero is satisfied) ”. When the branch condition judging unit 62 receives the operation code “100” from the instruction decoding unit 3, the branch condition judging unit 62 judges whether the value of the zero flag Z of the condition code 61 is zero. When the value of the zero flag Z is not zero (that is, when the branch condition defined by the operation code “100” is satisfied), the branch condition determination unit 62 supplies a high level signal to the inverting input of the AND circuit 63. . When the value of the zero flag Z is zero (that is, when the branch condition defined by the operation code “100” is not satisfied), the branch condition determination unit 62.
Supplies a low level signal to the inverting input of the AND circuit 63.

A signal 117 defining the timing for judging the branch condition is supplied from the judgment circuit 39 of the counter section 4 to the input of the AND circuit 63.

In this way, the output of the AND circuit 63 is at a high level when it is the timing for judging the branch condition and the branch condition is not satisfied, and is at the low level otherwise.

The output of the AND circuit 63 is supplied to the instruction register 8, the instruction decoding unit 3 and the execution unit 11 as a signal for canceling the instruction in the pipeline. In the cycle in which the output of the AND circuit 63 becomes high level, each of the instruction register 8, the instruction decoding unit 3, and the executing unit 11 cancels the instruction.

In the example shown in FIG. 9, the condition judging section 13 uses the condition code 6 for the sake of simplicity of explanation.
It is configured to judge whether to branch based on 1. It is also possible to configure the condition determination unit 13 so as to determine whether or not to branch based on other conditions. For example, the condition determination unit 13 may determine whether to branch based on the value of a specific register in the register file 12.

The position of the advance notice branch instruction in the program code will be described below.

FIG. 10A shows an example of program code including a conventional branch instruction. In FIG. 10A, S
_{1 to} S ₃ and S _{4 to} S ₇ indicate sequential instructions, and B ₁ and B ₂ indicate branch instructions.

FIG. 10B shows an example of the program code including the advance notice branch instruction. In FIG. 10B, S ₁
˜S ₃ , S ₄ ˜S ₇ indicate sequential instructions, B ₁ indicates a notice branch instruction branching after executing three instructions, and B ₂ indicates a notice branch instruction branching after executing four instructions. Figure 10
The order in which the instructions are executed in the program code shown in (b) is the same as the order in which the instructions are executed in the program code shown in FIG.

The optimum placement of the advance notice branch instruction in the program code is to place the advance notice branch instruction immediately after the immediately preceding branch point (the position where the actual branch should occur) (see FIG. 10 (b)). Such a notice branch instruction arrangement
It does not adversely affect the condition judgment of the advance notice branch instruction. The timing to judge the branch condition of the advance notice branch instruction is
The delay is appropriately postponed based on the counter value Z held in the down counter 31. Therefore, even if the sequential instruction following the advance notice branch instruction affects the determination of the branch condition of the advance notice branch instruction, the branch condition can be determined based on the result of the influence.

The pipeline processor 100 described above
Has a soft fair advantage in addition to a hard fair advantage. That is, the pipeline processor 100 improves the portability of program code.

For example, the pipeline processor 100
Can also execute program code containing conventional branch instructions. Advance branch instruction "Branch af
This is because the “ter 0 to X” (preliminary branch instruction that branches to the instruction X after executing 0 instructions) is equivalent to the conventional branch instruction. This guarantees continued use of program code created in the past.

When the pipeline processor 100 is implemented by two pieces of hardware having different instruction fetch cycles, the same program code can be executed by both pieces of hardware. This also guarantees continuous use of the program code created in the past. The delayed branch approach does not guarantee continuous use of the program code. For example, it is impossible to execute the program code generated with the delay slot = 2 on the hardware corresponding to the delay slot = 3 (or
Performance will deteriorate significantly). In this respect, the method of the present invention and the delayed branching method make a sharp contrast.

The number of instruction fetch cycles tends to increase, and the hardware must be updated accordingly. However, updating software requires enormous cost compared to updating hardware. Therefore, ensuring the continued use of programs created in the past is of great significance.

[0111]

According to the pipeline processor of the present invention, it is possible to prevent a delay from occurring due to execution of a branch instruction without affecting a large amount of memory or operating speed. Further, even if the number of cycles required to fetch one instruction increases, it is possible to prevent the execution of the branch instruction from causing a delay.

Moreover, the pipeline processor of the present invention does not require any special hardware.

According to the pipeline processor of the present invention, the branch target address can be calculated before the branch position. Therefore, the completion of the calculation of the branch target address is waited for in the switching operation of the fetch from the sequential instruction to the branch target instruction. There is no. As a result, it is possible to eliminate the disturbance of the pipeline caused by the execution of the branch instruction.

[Brief description of drawings]

FIG. 1 is a pipeline processor 100 according to the present invention.
It is a figure which shows the structure of.

2 is a diagram showing a format of a branch instruction used in the pipeline processor 100. FIG.

FIG. 3 is a diagram showing a configuration of a counter section 4.

FIG. 4A is a diagram showing a configuration of a control signal generation unit 38,
(B) is a diagram showing a waveform of a signal in the control signal generation unit 38.

5A is a diagram showing an example of a program code string including a notice branch instruction, and FIG. 5B is a time chart showing the operation of the pipeline processor 100 when A = 2 and B = 3.

FIG. 6 is a time chart showing the operation of the pipeline processor 100 when A = 3 and B = 3.

FIG. 7 is a time chart showing the operation of the pipeline processor 100 when A = 3 and B = 2.

FIG. 8 is a time chart showing the operation of the conventional pipeline processor 100 when A = 3.

FIG. 9 is a diagram showing a configuration of a condition determination unit 13.

10A is a diagram showing an example of a program code including a conventional branch instruction, and FIG. 10B is a diagram showing an example of a program code including a notice branch instruction.

FIG. 11 shows a configuration of a conventional processor using BTB.

FIG. 12 shows a configuration example of BTB.

[Explanation of symbols]

 1 Instruction Memory 2 Program Counter 3 Instruction Decode Unit 4 Counter Unit 5 Selector 6 Branch Destination Address Register 7 Branch Destination Address Calculation Unit 8 Instruction Register 9 Adder 10 BTB 11 Execution Unit 12 Register File 13 Condition Judgment Unit 100 Pipeline Processor

Claims (8)

[Claims] 1. A pipeline processor for executing a predictive branch instruction that defines the number of at least one instruction that should be executed following the predictive branch instruction before changing control flow, to be fetched. A program counter for holding an address of an instruction, an instruction memory for outputting an instruction corresponding to an address held by the program counter, an instruction register for fetching and holding an instruction output from the instruction memory, and an instruction register An instruction decoding unit that identifies whether or not the held instruction is the advance notice branch instruction by decoding the held instruction, and a counter that holds a counter value and compares the counter value with a predetermined threshold value. The counter value is initialized to the number of instructions defined by the advance branch instruction, and the counter value is A counter unit that is decremented in synchronization with the program counter being incremented, an adder that increments the address held by the program counter and provides the incremented address as a sequential instruction address, and the advance notice branch instruction. And a selector for selecting one of the sequential instruction address and the branch destination address of the advance notice branch instruction according to the comparison result of the counter unit. Line processor. 2. The advance notice branch instruction follows an advance notice branch instruction until an area for storing an opcode for identifying the type of the instruction, an area for specifying the branch destination address, and the control flow is changed. And a region for storing the number of at least one instruction to be executed by the pipeline processor. 3. The pipeline processor of claim 1, wherein the predetermined threshold is equal to the number of cycles required to fetch an instruction. 4. The counter unit outputs a selection signal for selecting a branch destination address of the advance notice branch instruction to the selector when the counter value matches the predetermined threshold value. Pipeline processor described in. 5. The counter unit, when the number of instructions defined by the advance notice branch instruction is smaller than the predetermined threshold value, sends a selection signal for selecting a branch destination address of the advance notice branch instruction to the selector. The pipeline processor according to claim 1, which outputs. 6. The counter unit sends a signal to the instruction register to cancel the instruction held by the instruction register when the number of instructions defined by the advance notice branch instruction is smaller than the predetermined threshold value. Output,
The pipeline processor according to claim 1. 7. The pipeline processor further includes a condition determination unit that determines whether or not to change the control flow for the advance notice branch instruction, and the counter unit has a predetermined counter value. The pipeline processor according to claim 1, wherein when the value is reached, a signal defining a timing for determining whether to change the control flow for the advance notice branch instruction is output to the condition determining unit. 8. The condition judging unit, when judging that the control flow is not changed for the advance notice branch instruction,
The pipeline according to claim 7, wherein a signal for canceling an instruction held by the instruction register is output to the instruction register, and a signal for canceling an instruction decoded by the instruction decoding unit is output to the instruction decoding unit. -Processor.