JPH04246889A - Manufacture of thin film multilayered board - Google Patents

Abstract

PURPOSE:To enable a thin film multilayered board to be manufactured with a high yield. CONSTITUTION:Intermediate layer member manufacturing processes 31 and 32 are carried out independently of lamination and other processes 35-38, non- defective intermediate layer members are used in the lamination process 35, and the defective wiring layer pattern of a thin film layer board is hardly generated in a manufacturing process. Defective products are hardly generated in a carrier removing process 36, an adhesive layer via forming process 37, and a connection pattern forming process 38.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film multilayer substrate.

[0002] In recent years, with the demand for higher speed computer systems, there has been a demand for higher density printed wiring boards.

[0003] One of the products that satisfies this requirement is a thin film multilayer substrate. This thin-film multilayer substrate has a complicated structure and tends to be defective, so it has been desired to realize a manufacturing method that can produce it with high yield.

0004

20 shows an example of a conventional thin film multilayer substrate manufacturing method, and FIGS. 21(A) to 21(E) show the state after each step.

[0005] The conventional manufacturing method is a build-up method. Specifically, as shown in FIG. 21A, an insulating layer 14 is formed by spin-coating polyimide resin on the surface of a glass ceramic printed wiring board 13 on which vias 11 and lands 12 are formed. Formation step 1 and FIG. 21 (
Metal mask forming step 2 of forming the metal mask 15 as shown in B) and reactive ion etching (RIE)
As shown in FIG. 21(C), via forming step 3 of forming a via 16 in the insulating layer 14 and FIG. 21(D)(E) are performed.
As shown in FIG. 2, the wiring pattern is formed by repeating the connection wiring pattern forming step 4 of forming the connection pattern 17 in the region of the via 1 and forming the wiring pattern 17 in the region away from the via 15 as many times as necessary. .

[0006]

[Problem to be Solved by the Invention] Since the build-up method is adopted, the wiring pattern 18 and the connection pattern 1
If a defect occurs in an intermediate process such as the process of forming 7, the entire board will be defective.

On the other hand, as the patterns 18 and 17 become denser and the layers become more multilayered, defects are more likely to occur in the process, and the yield of thin film multilayer substrates is low.

In addition, since the build-up method is adopted, the wiring patterns are built in each layer one after another, making it impossible to form wiring patterns for all layers in parallel, which requires considerable manufacturing time. It took time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a thin film multilayer substrate, which enables improved yield and manufacturing efficiency.

0010

[Means for Solving the Problems] The invention as claimed in claim 1 is directed to manufacturing an intermediate layer member in which a wiring pattern and a land are formed on a carrier in advance, and then distributing the wiring pattern and land on the intermediate layer member. a step of stacking the land on the board via an adhesive layer so as to face the board; and removing the carrier of the stacked intermediate layer member while leaving the wiring pattern, the land, and the adhesive layer on the board. The step of forming a via at the land portion of the adhesive layer, and the step of forming a connection pattern at the formed via portion are repeated.

[0011] In the invention as claimed in claim 2, the carrier removing step in the claim includes a polishing step for removing most of the thickness of the carrier;
The invention according to claim 3 is characterized in that the intermediate layer member according to claim 1 is configured to include an etching step for removing the remaining carrier, and the intermediate layer member according to claim 1 is characterized in that the carrier is composed of a carrier body and a barrier layer on the surface thereof, and the wiring A pattern and a land are formed on the surface of the barrier layer, and the carrier removal step includes a polishing step for removing most of the thickness of the carrier body;
The structure consists of a first etching step for removing the remaining carrier body, and then a second etching step for removing the barrier layer.

According to a fourth aspect of the invention, in the intermediate layer member of the first aspect, the carrier comprises a carrier body, a polyimide layer on the surface of the carrier body, and a barrier layer on the surface of the polyimide layer,
A wiring pattern and a land are formed on the surface of the barrier layer, and the carrier removal step includes a polishing step for removing the entire carrier body, a peeling step for peeling off the polyimide layer, and a step for removing the barrier layer. The structure consists of an etching process.

According to a fifth aspect of the present invention, in the fourth aspect, the carrier body is a glass plate, and the barrier layer is an indium-tin oxide film.

[0014] According to a sixth aspect of the invention, the intermediate layer member according to the first aspect has a structure in which the carrier is formed by covering an invar core material with another metal layer.

[0015] The invention according to claim 7 is characterized in that the lamination step according to claim 1 is configured such that the substrate and the intermediate layer member are aligned with an ultraviolet curable adhesive interposed between them. .

[0016]

According to the first aspect of the present invention, by manufacturing each intermediate layer member on which a wiring pattern and a land are formed in advance, it is possible to manufacture and inspect each intermediate layer member individually. Laminating the intermediate layer members prevents the substrates manufactured up to an intermediate stage from becoming defective.

In the invention of claim 2, the combination of the polishing step and the etching step efficiently removes the carrier.

In the third aspect of the invention, the barrier layer protects the wiring pattern and the via from etching in the first etching step.

In the fourth aspect of the invention, the polyimide layer makes it possible to polish away the entire carrier body.

In the invention of claim 5, the glass plate and the indium-tin oxide film make the carrier transparent.

[0021] In the invention of claim 6, the structure in which another metal layer is applied to the invar core material makes it possible to match the thermal expansion coefficient of the carrier with that of the printed wiring board.

[0022] In the seventh aspect of the invention, the ultraviolet curing adhesive enables realignment.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the method for manufacturing a thin film multilayer substrate according to the present invention.

31 is a step of manufacturing the first intermediate layer member;
32 is a process for manufacturing the second intermediate layer member, which is performed independently and separately from the glass ceramic printed wiring board manufacturing process and the lamination process, which will be described later.

FIG. 2 shows a first intermediate layer member 50, in which wiring patterns 512 and vias 5 are formed by photography on the surface of a carrier 51 made of a thick glass plate with a thickness t1 of 3 mm.
A land 54 having a diameter of 3 is formed.

The carrier 51 is made of thick glass because
This is to ensure the safety of the dimensions of the wiring pattern 52 and the land 54.

The second intermediate layer member (not shown) also has substantially the same configuration as the first intermediate layer member 50.

Next to steps 31 and 32 are inspection steps 33 and 3.
4, and each intermediate layer member that is a good product is prepared in advance.

Even if a defect occurs in steps 31 and 32, only the intermediate layer member becomes defective.

Further, steps 31 and 32 can be performed in parallel, and steps 31 and 32 can also be performed in parallel with the lamination step, etc., which will be described later, and the thin film multilayer substrate is It is manufactured efficiently.

In FIG. 1, numeral 30 indicates a glass ceramic printed wiring board manufacturing process, and as shown in FIG. 3(A), via 1
A glass ceramic printed wiring board 13 having lands 1 and 12 is manufactured.

Next, a lamination step 35 in FIG. 1 is performed. In this step 35, as shown in FIG. 3(A), a bonding sheet 55 is interposed between the first intermediate layer member 5
0 are stacked with their wiring patterns 52 and lands 54 facing the printed wiring board 13 and positioned so that the vias 53 coincide with the lands 12. This allows the first
The intermediate layer member 50 is laminated on the printed wiring board 13 via an adhesive layer 56, as shown in FIG.

Next, a carrier removal step 36 in FIG. 1 is performed. In this step, the carrier 51 is removed as shown in FIG. 3(C).

When the carrier 51 is removed, the printed wiring board 13 has a land 54 having a via 53 and a wiring pattern 52 on its surface.

Details of how to remove the carrier 51 will be described later. Next, an adhesive layer via forming step 37 in FIG. 1 is performed.

In this step 37, first, FIG.
), a metal mask 57 is formed except for the via 53, and then reactive ion etching is performed to remove the via 5 from the adhesive layer 56, as shown in FIG. 3(E).
A via 58 is formed at a portion facing the land 12 and the land 12.

Thereafter, as shown in FIG. 4(A), the metal mask 57 is removed. Next, a connection pattern forming step 38 in FIG. 1 is performed.

This step 38 is performed through a plurality of steps as shown in FIGS. 4(B) to (D) and FIGS. 5(A) to (E), and the lower land 12 and the upper land 54 are separated. A connection pattern 59 to be connected is formed.

To explain the above step 38, first,
In order to remove the side etch 60 caused by the above-described reactive ion etching, a resist mask 61 is formed as shown in FIG. 4(B), and etching is performed.
As shown in FIG.
Remove 4a.

Next, as shown in FIG. 2D, the resist mask 61 is removed. After that, sputtering is performed to form a metal film 6 on the entire surface as shown in FIG. 5(A).
form 2.

Next, as shown in FIG. 6B, a resist mask 63 is formed on the surface of the metal film 62, leaving a portion corresponding to the original land 54.

Next, pattern plating is performed to obtain the pattern shown in FIG.
), a plating layer 64 is formed.

Thereafter, the resist mask 63 is removed as shown in FIG. 2D. Finally, perform etching and
The metal film 62 exposed on the surface is removed as shown in FIG. 5E, and a connection pattern 59 is left behind.

As a result, the printed wiring board 13 has the first layer wiring pattern 52 and the land 65 on the surface,
In addition, the land 65 is electrically connected to the lower land 12 via the connection pattern 59.

Next, steps 40 to 43 in FIG. 1 are performed. These steps 40 to 43 are performed except that the substrate is the printed wiring board 13A on which the first layer wiring pattern 52 and land 65 (54) are formed, and the material to be laminated is the second intermediate layer member. , is carried out in substantially the same manner as steps 35-38 above.

First, step 40 is performed, in which a second intermediate layer member that has been inspected and is a good product is laminated on the printed wiring board 13A via an adhesive layer.

Next, step 41 is performed to remove the carrier of the second intermediate layer member, followed by step 42,
Vias are formed in the adhesive layer, and finally step 43 is performed to form a connection pattern.

[0048] As a result, a second layer wiring pattern and land are formed. By repeating the above steps, a thin film multilayer substrate is manufactured.

As described above, even if a defect occurs in each intermediate layer member manufacturing process, only that intermediate layer member becomes defective, and the thin film multilayer substrate that breaks down during the manufacturing process does not become defective. In addition, the lamination steps 35 and 40, and the carrier removal step 3
6, 41, defects are less likely to occur in the adhesive layer via forming steps 37, 42 and the connection pattern forming steps 38, 42, so according to the manufacturing method of the above embodiment, thin film multilayer substrates can be manufactured with higher yield than conventional methods. be done.

Furthermore, manufacturing and testing of each intermediate layer member can be performed simultaneously and in parallel, and thin film multilayer substrates can be manufactured more efficiently than in the past.

Next, a first embodiment of the carrier removal step 36 in FIG. 1 will be described. As shown in FIG. 6, a surface polishing step 70 is first performed, and as shown in FIG. mechanically abrasive and remove.

Next, an etching step 71 is performed to remove the glass plate portion 73 remaining after polishing.

Etching is performed chemically using hydrofluoric acid or physically using plasma.

Next, a second embodiment of the carrier removal step 36 in FIG. 1 will be described. As shown in FIG. 8, a plane polishing step 80 is first performed to polish the glass plate, and then a first etching step 81 is performed to remove the portion of the glass plate remaining after polishing.
The carrier is removed by performing a second etching step 82 to remove the barrier layer.

FIG. 9(A) shows that the first intermediate layer member 90 shown in FIG. 10(C) is attached to the printed wiring board 13 via the adhesive layer 56.
The state shown is that it is stacked on top.

To manufacture the first intermediate layer member 90, first, as shown in FIG. 10(A), only the portion where alignment marks are to be formed is masked on the surface of the glass plate 72 as a carrier, and sputtering is performed. Cr film 91
Then, a Cu film 92 is formed.

The Cr film 91 and Cu film 92 constitute a barrier layer 93. Next, as shown in FIG. 10(B),
Remove the mask and apply C to the entire surface again by sputtering.
An r film 94 and a Cu film 95 are formed to form a power supply layer for pattern plating.

Next, a pattern is formed using a resist, pattern plating is performed, the resist is removed, and etching is performed to form a wiring pattern 52 and a land having a via (not shown) as shown in FIG. , and alignment marks 96 are formed.

[0059] In this way, the first intermediate layer member 90 is manufactured. As shown in FIG. 9(A), the first intermediate layer member 90
In order to remove the glass plate 72 in a stacked state, first perform the plane polishing step 80 shown in FIG.
The portion indicated by the two-dot chain line is mechanically polished and removed, leaving a slight thickness of 0 to 100 μm.

Next, a first etching step 81 is performed using hydrofluoric acid or plasma to remove the glass plate portion 73 remaining after polishing, as shown in FIG. 9(C).

If the etching becomes excessive at this time, the presence of the barrier layer 92 reliably prevents erosion of the polyimide adhesive layer 56, wiring pattern 52, and alignment mark 95.

Finally, a second etching step 82 is performed to remove the barrier layer 92 as shown in FIG. 9(D).

Next, a third embodiment of the carrier removal step 36 in FIG. 1 will be described. As shown in FIG. 11, the carrier is removed by first performing a surface polishing step 100 for removing the entire glass plate, then performing a step 101 for peeling off the polyimide layer, and finally performing an etching step 102 for removing the barrier layer. be done.

FIG. 12A shows that the first intermediate layer member 110 shown in FIG. 13 is attached to the printed wiring board 1 via the adhesive layer 56.
3 is shown stacked on top of each other.

The first intermediate layer member 110 includes a glass plate 72
It has a polyimide layer 111 on top, and this polyimide layer 11
1, has a barrier layer 112 of a Cu film 92 on this polyimide layer 111, and further has a wiring pattern 52 and an alignment mark 96 thereon.

The first intermediate layer member 110 is manufactured by first spin-coating a polyimide resin on the glass plate 72 to form a polyimide layer 111, and then following substantially the same steps as shown in FIG. Ru.

The reason why only the Cu layer 92 is used as the barrier layer 112 is to keep the adhesive force between the polyimide layer 111 and the barrier layer 112 low so that the polyimide layer 111 can be easily peeled off.

The thickness t3 of the polyimide layer 111 is set to a thickness that can absorb variations in flatness of the glass plate 72 and printed wiring board 72.

In order to remove the carrier from the stacked state shown in FIG. 12(A), first, step 100 of FIG. 11 is performed.
The glass plate 72 is polished until it reaches the polyimide layer 111, and the entire glass plate 72 is removed as shown in FIG. 12(B).

Next, step 101 is performed, and FIG. 12(C)
The polyimide layer 111 is peeled off as shown in FIG.

Finally, an etching step 102 is performed, and as shown in FIG. 12(D), the barrier layer 112 (Cu film 92
) to remove.

As shown in FIGS. 7 and 9B, the thickness t2 of the unpolished glass plate portion 73 is 50 to 100 μm, which is too thick to be removed by etching.
It takes a considerable amount of man-hours to remove it by etching.

In contrast, according to this embodiment, the entire glass plate 72 is removed by polishing, and etching is performed only on the extremely thin barrier layer 112, so that the carrier can be removed with fewer man-hours.

Next, a fourth embodiment of the carrier removal step 36 in FIG. 1 will be described. As shown in FIG.
1, it consists of a plane polishing process 120, a peeling process 121, and an etching process 122.

FIG. 15A shows a state in which the first intermediate layer member 130 shown in FIG. 16 is laminated on the printed wiring board 13 with the adhesive layer member 130 interposed therebetween.

The first intermediate layer member 130 has a polyimide layer 111 on a glass plate 72, as shown in FIG.
A barrier layer 132 of an indium-tin oxide film (ITO film) 131 is provided thereon, and a wiring pattern 52 and an alignment mark 96 are provided thereon.

Since the film 131 is transparent, there is no need to mask the periphery of the alignment mark 96 to expose it, and the alignment mark 96 can be formed directly on the film 131. This is easier than when it is opaque.

The peelability of the polyimide layer 111 from the film 131 is good. In order to remove the carrier from the stacked state shown in FIG. 15(A), first perform step 120 in FIG. 14 to polish the glass plate 72 until it reaches the polyimide layer 111, and then The entire glass plate 72 is removed.

Next, step 121 is performed, and FIG. 15(C)
The polyimide layer 111 is peeled off as shown in FIG.

Finally, an etching step 122 is performed to remove the barrier layer 132 (indium-tin oxide film 131), as shown in FIG. 15(D).

FIG. 17 shows a modification of the first intermediate layer member. The carrier 141 of the first intermediate layer member 140 has a core material 142 made of invar, and a core material 142 made of invar.
This configuration has Cu layers 143 and 144 on both sides of the substrate.

Thickness of core material 142 and Cu films 143, 14
The carrier 141 has a coefficient of thermal expansion equal to that of the glass ceramic printed wiring board 13.

Therefore, even after stacking as shown in FIG. 18(A), no positional shift occurs in the wiring pattern 52.

The carrier removal process after lamination is shown in FIG.
), the lower Cu layer 1 of the carrier 141
43, Cu layer 144 and invar core material 142
For example, the Cu layer 14 is removed by polishing, and then the remaining Cu layer 14 is removed.
3 is removed by etching as shown in FIG. 3(C).

Next, the structure and operation of the apparatus used in the lamination step 35 in FIG. 1 will be explained.

FIG. 19 shows the apparatus 1 used in the lamination step 35.
50 is shown. 151 is an intermediate layer member fixing frame, which is fixedly installed.

A table 152 is fixed to the upper end of the X-Y-θ correction shaft 153, and is corrected in the X, Y, and θ directions.

The carrier 51 of the first intermediate layer member 50 is vacuum-adsorbed onto the fixed frame 151. The printed wiring board 13 is attracted to the table 152.

Printed wiring board 13 and first intermediate layer member 5
0, a bonding sheet 55 is interposed between the
The camera 155 is placed at a gap g of 30 to 100 μm with an ultraviolet curing adhesive 154 interposed near the periphery.
, 156 to image the alignment marks 157 to 160 while slightly moving the table 152 to perform alignment.

When the alignment is completed, the table 152 is raised and the printed wiring board 13 is placed on the first intermediate layer member 50.
Closely contact.

In this state, it is confirmed whether the alignment is correct, and if the alignment is correct, the adhesive 154 is cured by irradiating ultraviolet rays, and the first intermediate layer member 50 is
and printed wiring board 13 are fixed together, and in the next step they are integrally molded by pressing.

[0092] If the position is shifted, alignment is performed again. Since the adhesive 154 has not yet hardened, repositioning is possible.

[0093] Therefore, defects are less likely to occur in the lamination step 35, and from this point of view as well, the thin film multilayer substrate can be manufactured with high yield.

[0094]

As explained above, according to the invention of claim 1, the intermediate layer members can be individually manufactured and inspected, and even if a defect occurs at this stage, the intermediate layer member can be inspected. The substrates manufactured up to that stage will not become defective, and the final product, the thin film multilayer substrate, can be manufactured with high yield. Further, since the thin film multilayer substrate is manufactured by sequentially stacking inspected intermediate layer members, defects are less likely to occur in this respect, and the yield can be improved.

According to the second aspect of the invention, carriers can be efficiently removed and thin film multilayer substrates can be efficiently manufactured.

According to the third aspect of the invention, the presence of the barrier layer makes it possible to reliably protect the wiring patterns and vias from etching in the first etching step, thereby improving the yield of thin film multilayer substrates. .

According to the fourth aspect, the entire carrier body can be removed by polishing, the number of steps required for removing the carrier can be reduced, and a thin film multilayer substrate can be manufactured efficiently.

According to the fifth aspect of the invention, since the carrier is transparent, masking is not required and the positioning mark can be easily formed.

According to the invention of claim 6, it is possible to prevent the wiring pattern from being misaligned with respect to the substrate after lamination, it is possible to prevent misalignment from occurring, and it is possible to manufacture thin film multilayer substrates with high yield. I can do it.

According to the seventh aspect of the invention, after the parts are partially aligned and brought into close contact, it is possible to align again, thereby preventing the occurrence of defects, and making it possible to manufacture thin film multilayer substrates with high yield. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the method for manufacturing a thin film multilayer substrate of the present invention.

FIG. 2 is a diagram showing a first intermediate layer member.

FIG. 3 is a diagram showing the state of each step in FIG. 1.

FIG. 4 is a diagram showing a state following FIG. 3;

FIG. 5 is a diagram showing a state subsequent to FIG. 4;

FIG. 6 is a diagram showing a first example of the carrier removal step in FIG. 1;

FIG. 7 is a diagram showing the state after the plane polishing process in FIG. 6;

FIG. 8 is a diagram showing a second example of the carrier removal process in FIG. 1;

9 is a diagram showing the state of each step in FIG. 8. FIG.

10 is a diagram illustrating manufacturing of the first intermediate layer member in FIG. 9. FIG.

11 is a diagram showing a third example of the carrier removal step in FIG. 1. FIG.

12 is a diagram showing the state of each step in FIG. 11. FIG.

FIG. 13 is a diagram showing the first intermediate layer member in FIG. 12(A).

14 is a diagram showing a fourth example of the carrier removal step in FIG. 1. FIG.

15 is a diagram showing the state of each step in FIG. 14. FIG.

FIG. 16 is a diagram showing the first intermediate layer member in FIG. 15(A).

FIG. 17 is a diagram showing a modification of the first intermediate layer member.

18 is a diagram illustrating the lamination step and carrier removal step in FIG. 1 when the first intermediate layer member of FIG. 17 is used.

19 is a diagram showing an apparatus used in the lamination process in FIG. 1. FIG.

FIG. 20 is a diagram showing an example of a conventional method for manufacturing a thin film multilayer substrate.

21 is a diagram showing the state of each step in FIG. 20. FIG.

[Explanation of symbols]

11 Via 12 Land 13 Glass ceramic printed wiring board 30 Glass ceramic printed wiring board manufacturing process 31 First intermediate layer member manufacturing process 32 Second intermediate layer member manufacturing process 33 Inspection process 34 Inspection process 35 First intermediate layer member lamination Steps 36 and 41 Carrier removal steps 37 and 42 Adhesive layer via formation steps 38 and 43 Connection pattern formation step 40 Second intermediate layer member lamination step 50 First intermediate layer member 51 Carrier 52 Wiring pattern 53 Via 54 Land 55 Bonding Sheet 56 Adhesive layer 57 Metal mask 58 Via 59 Connection pattern 60 Side etch 61 Resist mask 62 Metal film 63 Plating layer 65 Land 70 Surface polishing process 71 Etching process 72 Glass plate (carrier) 73 Remaining polished glass plate portion 80 Surface polishing process 81 First etching process 82 Second etching process 90 First intermediate layer member 91 Cr film 92 Cu film 93 Barrier layer 94 Cr layer 95 Cu layer 96 Alignment mark 100 Surface polishing process 101 Peeling process 102 Etching process 110 First Intermediate layer member 111 Polyimide layer 112 Barrier layer 120 Surface polishing process 121 Peeling process 122 Etching process 130 First intermediate layer member 131 Indium-tin oxide film 132 Barrier layer 140 First intermediate layer member 141 Carrier 142 Invar core material 143 , 144 Cu layer 150 Carrier 151 Intermediate layer member fixing frame 152 Table 153 X-Y-θ correction axis 154 Ultraviolet curing adhesive 155, 156 Camera

Claims (7)

[Claims] 1. An intermediate layer member (50) having a wiring pattern (52) and a land (54) formed on a carrier (51) is manufactured in advance, and the intermediate layer member (50) is A step (35) of laminating the wiring pattern (52) and the land (54) on the substrate (13) via an adhesive layer (56) so as to face the substrate (13); a step (36) of removing the carrier (51) of the laminated intermediate layer member (50), leaving the land (54) and the adhesive layer (56) on the substrate (13); A step (37) of forming a via (58) in the region of the land (54) in the layer (56), and a step (37) of forming a connection pattern (59) in the region of the formed via (58). 38) A method for manufacturing a thin film multilayer substrate, characterized by repeating 38). 2. The carrier removal step according to claim 1 is a polishing step (70) for removing most of the thickness of the carrier (72).
and an etching step (71) for removing the remaining carrier (73). 3. In the intermediate layer member according to claim 1, the carrier has a carrier body (72) and a barrier layer (93) on the surface of the carrier body (72).
Therefore, the wiring pattern (52) and land (54)
is formed on the surface of the barrier layer (93), and the carrier removal step includes a polishing step (80) for removing most of the thickness of the carrier body (72), and a polishing step (80) for removing most of the thickness of the carrier body (72). A first etching step (81) to remove
and, thereafter, a second etching step (82) for removing the barrier layer (93). 4. The intermediate layer member according to claim 1, wherein the carrier comprises a carrier body (72) and a polyimide layer (72) on the surface of the carrier body (72).
111) and a barrier layer (112) on the surface of the polyimide layer.
), the wiring pattern (52) and the land (54
) is formed on the surface of the barrier layer, and the carrier removal step includes a polishing step (100) for removing the entire carrier body, a peeling step (101) for peeling off the polyimide layer, and the barrier layer. A method for manufacturing a thin film multilayer substrate, comprising an etching step (102) for removing. 5. The method of manufacturing a thin film multilayer substrate according to claim 4, wherein the carrier body is a glass plate (72) and the barrier layer is an indium-tin oxide film (131). 6. In the intermediate layer member according to claim 1, the carrier has an invar core material (142) and another metal layer (143,
144) A method for manufacturing a thin film multilayer substrate, characterized in that the substrate is coated with a thin film multilayer substrate. 7. The lamination step of claim 1 includes applying an ultraviolet curing adhesive (154) between the substrate and the intermediate layer member.
1. A method for manufacturing a thin film multilayer substrate, characterized in that alignment is carried out with the intervening state.