JPH0424684Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a thermal printing head drive circuit in a thermal printing line printer.

(Prior Art) FIG. 3 is a circuit diagram of a conventional thermal printing head drive circuit in a thermal printing line printer.
This figure is a timing chart for explaining the operation of the thermal printing head drive circuit of FIG. 3. In FIG. 3, SR is a 512-bit shift register of serial input/parallel output type. The input section of this shift register SR is connected to a printing control circuit (not shown) as shown in Fig. 4b.
In the middle, serial print data indicated by D1 to D512 is given. This print data is handled in the print control circuit as n bits, for example, 8 bits, and is subjected to parallel/serial conversion processing in the print control circuit and then fed to the input section of the shift register SR. . Also, this print data
For example, 512 bits constitute pixel data on one horizontal scanning line of a television screen. The shift register SR shifts the print data applied to its input in response to the shift clock shown in FIG. 4a.

LA is a group of latch circuits. This latch circuit group
When all 512 bits of print data are input to the shift register SR, the LA receives the latch signal shown in Figure 4d from the print control circuit, thereby latching all the print data in the shift register SR. It's becoming like that. Latch circuit group LA is 512
It consists of several latch circuits.

AD is an AND circuit group, and this AND circuit group
AD has 512 AND circuits AD1, AD2...AD5
It consists of 12. Each AND circuit has the same number of latch circuits in the latch circuit group LA, and one input part of each AND circuit is connected to the latch circuit group LA.
individually connected to each latch circuit within the circuit. The other input section of each AND circuit is commonly supplied with the strobe signal shown in FIG. 4c. For example, when printing print data #1 (however, #0 indicates the previous print data), this strobe signal is activated when the latch circuit group LA finishes latching the print data #1. The AND circuit is opened and the print data in the latch group LA is output from the AND circuit.

R is a heat generating resistor group of the thermal printing head, and this heat generating resistor group R includes 512 heat generating resistors R1 and R2.
...It is composed of R512. And each heating resistor R1, R2...R512 is an AND circuit group
Individually connected to the output of each AND circuit in LA.

Since the thermal print head drive circuit having such a configuration handles serial print data, it is necessary for the print control circuit to convert the print data, which is parallel inside, into a serial form. Therefore, the circuit configuration on the printing control circuit side becomes very complicated. Also,
Since it is necessary to input 512 bits of print data to the shift register SR, this is extremely inconvenient for high-speed printing.

(Purpose of the invention) The present invention eliminates the need for parallel/serial conversion of print data on the print control circuit side, simplifying the configuration of the print control circuit, and making it possible to handle print data in parallel. The purpose is to enable high-speed printing by

(Structure of the invention) In order to achieve the above-mentioned object, the present invention provides a first latch circuit which receives print data composed of m bits in parallel and sequentially latches the print data in response to a first latch signal. and a second latch circuit comprising a plurality of latch circuits that individually latch the parallel print data sequentially applied from the first latch circuit in response to a second latch signal.
a group of latches; means for individually applying a second latch signal to each latch circuit in the second group of latches in response to a clock; and a number of latches equal to the number of latches in the second group of latches. Each latch circuit has an output section for m bits,
a third latch circuit group that latches the print data from the second latch circuit group in response to a third latch signal when each latch circuit in the second latch circuit group finishes latching the print data; Each of m AND circuits is connected to each output part of each latch circuit in the third latch circuit group, and print data latched in each latch circuit in response to a strobe signal is output. a group of AND circuits to output, and a thermal printing head for generating heat, each of which is composed of m resistors, and each resistor is individually connected to the output part of each AND circuit in the corresponding AND circuit group; It is equipped with a group of resistors.

(Example) Hereinafter, the present invention will be described in detail based on an example shown in the drawings. FIG. 1 is a circuit diagram of a thermal printing head drive circuit in a thermal printing line printer according to this embodiment, and FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG. In this embodiment, the number of print data corresponding to pixel data for one horizontal scanning line of the television screen is 512, as in the prior art, and these 512 print data are handled every 8 bits. Each print data is applied in parallel from a print control circuit built in a CPU (not shown) to a first latch circuit, which will be described below.

LA1 is sequentially given the parallel print data S1 to S64 shown in FIG. 2b, which is composed of 8 bits, and responds to the print data S1 to S64 in response to the first latch signal shown in FIG. 2d. This is the first latch circuit that latches sequentially.

LA2 transfers the parallel print data S1 to S64 sequentially given from the first latch circuit LA1 to the second latch circuit LA2, respectively.
A second group of latch circuits individually latches in response to a latch signal. Therefore, the second latch circuit group
LA2 consists of a total of 64 latch circuits A1 to A64. And each latch circuit A1
-A64 are each capable of latching 8 bits worth of print data in parallel, and parallel print data S1-S64 are individually applied from the first latch circuit LA1 via data buses D1-D64, respectively.

SR is a series input/parallel output that provides a second latch signal to each latch circuit A1 to A64 in the second latch circuit group LA2 via signal lines S1 to S64 in response to the shift clock shown in FIG. 2a. of
This is a 64-bit shift register. This shift register SR sequentially shifts and outputs a single output, and if it has the same function, other circuit means such as a ring counter that also sequentially shifts and outputs a single output. Good too.

LA3 is a third latch circuit group comprising latch circuits B1 to B64 of the same number and configuration as each of the latch circuits A1 to A64 in the second latch circuit group LA2.
Each latch circuit B in this third latch circuit group LA3
1 to B64 each have an output section for 8 bits, and when all the print data has been latched to each latch circuit A1 to A64 in the second latch circuit group LA2, the output part shown in FIG. The print data S1 to S64 from the second latch circuit group LA2 are latched in response to the third latch signal shown.

AD1 to AD64 are the first to 64th AND circuit groups, respectively, and have the same configuration. The first AND circuit group AD1 includes eight AND circuits a1
It starts from ~a8. This AND circuit a1-a
8 are individually connected to each output section (corresponding to each bit of one print data) of the latch circuit B1 in the third latch circuit group LA3, and
Print data S1 latched in latch circuit B1 in response to the strobe signal shown in FIG. 2c.
is now output. Also, 2nd to 64th
Similarly, the AND circuit groups AD2 to AD64 each consist of eight AND circuits, and the corresponding latch circuits B2 to B in the third latch circuit group LA3.
64 output sections individually.

R1 to R64 are each AND circuit group AD1 to AD6
This is a heat generating resistor group of the thermal print head, each of which is provided corresponding to each of the four resistors r1 to r8. For example, the heating resistor group R1
Each of the resistors r1 to r8 is an AND circuit group.
It is individually connected to each output part of each AND circuit a1 to a8 in AD1. Other heating resistor group R2...
...Each resistor in R64 is similarly individually connected to each AND circuit in each AND circuit group AD2 to AD64.

Next, the operation and effect will be explained. 8-bit parallel print data S1 to S64 shown in FIG. 2B are sequentially applied to the first latch circuit LA1. In this case, each of the print data S1 to S64 is sequentially latched into the first latch circuit group LA1 in response to the first latch signal shown in FIG. 2d. In this case, the second latch signal from shift register SR is on signal line S1
is applied to the latch circuit A1 in the second latch circuit group LA2 through the first print data S1.
is latched by latch circuit A1. Similarly, the next print data S2 is latched in the latch circuit A2 in the second latch circuit group LA2. Thereafter, each print data is sequentially latched in each latch circuit A3 to A64 in the same manner.

In this way, all the latch circuits A1 to A64 in the second latch circuit group LA2 are supplied with the current print data S1 to S64 (in FIG. 2, #0 is the previous print data, and #1 is the current print data). ) is completed, a third latch signal is applied to the third latch circuit group LA3. Then, as shown in FIG. 2e, the second latch circuit group
Each print data #1 (S
1 to S64) are simultaneously latched in each of the latch circuits B1 to B64 in the third latch circuit group LA3. In this way, the print data S is transferred to the third latch circuit group LA3.
When the latching operations 1 to S64 are completed, a strobe signal (the rising portion in FIG. 2) is applied to each AND circuit group AD1 to AD64. This results in
Each latch circuit B1~ in the third latch circuit group LA3
The print data latched in B64 is output from each AND circuit a1 to AD64 in each AND circuit group AD1 to AD64.
A8 is given separately. As a result, each of the resistors r1 to r8 of the heating resistor group R1 to R64 is given print data for each bit and generates heat.

Therefore, in this embodiment, since the print data is handled in parallel, there is no need to convert the print data into serial data in the print control circuit (not shown), which simplifies the circuit configuration of the print control circuit. It becomes possible. Furthermore, since print data is handled in parallel, high-speed printing is possible.

In the example, the number of latch circuits is 64, but it is not limited to this and may be n (n is any integer), and the number of AND circuits in the AND circuit group and the heating resistor Although the number of each resistor in the group is eight, it is not limited to this and may be n (n is any integer).

(Effects of the invention) As described above, according to the present invention, since it has the above-mentioned configuration, it is possible to handle print data in parallel, and it is not necessary to convert the print data from parallel to serial in the print control circuit. is eliminated, the circuit configuration of the printing control circuit can be simplified, and
Compared to the conventional case where print data is loaded into a shift register bit by bit, high-speed printing is possible because print data is handled every m bits.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2 is a timing chart for explaining the operation of the circuit in Figure 1, Figure 3 is a circuit diagram of a conventional example, and Figure 4 is a diagram of the circuit in Figure 3. This is a timing chart for explaining the operation. LA1 is the first latch circuit, LA2 is the second latch circuit group, LA3 is the third latch circuit group, AD1 to AD6
4 is an AND circuit group, and R1 to R64 are a heat generating resistor group.

Claims (1)

[Claims for Utility Model Registration] A first latch circuit to which print data composed of m bits is applied in parallel and sequentially latches the print data in response to a first latch signal; A second latch circuit includes a plurality of latch circuits that individually latch sequentially applied parallel print data in response to a second latch signal.
a group of latches; means for individually applying a second latch signal to each latch circuit in the second group of latches in response to a clock; and a number of latches equal to the number of latches in the second group of latches. Each latch circuit has an output section for m bits,
a third latch circuit group that latches the print data from the second latch circuit group in response to a third latch signal when each latch circuit in the second latch circuit group finishes latching the print data; Each of m AND circuits is connected to each output part of each latch circuit in the third latch circuit group, and print data latched in each latch circuit in response to a strobe signal is output. a group of AND circuits to output, and a thermal printing head for generating heat, each of which is composed of m resistors, and each resistor is individually connected to the output part of each AND circuit in the corresponding AND circuit group; comprising a group of resistors,
Thermal printing head drive circuit in a thermal printing line printer.