JPH04245454A - Method of forming insulator isolating region onto semiconductor wafer - Google Patents

Abstract

PURPOSE: To achieve a structure with a smaller occupation area of each island- shaped region as compared with a conventional method, in a method for forming an island region that is isolated by an insulator on a semiconductor wafer. CONSTITUTION: An insulator layer 11 is formed on a single crystal silicon substrate 10, and further an area on it is covered with a polycrystalline silicon layer 12. The non-covered surface of the single crystal silicon substrate is polished to create a thin film 10 made of a single crystal silicon, and further another single crystal silicon layer 13 is formed on it. A groove reaching the insulator layer through the single crystal silicon layer is dug by etching and is filled with an insulator, thus forming an island region that is completely isolated.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD This invention relates generally to isolation on semiconductor chips, and more particularly to an improved method for providing complete isolation with insulators.

0002

BACKGROUND OF THE INVENTION Forming island-like regions or similar bath-like regions on a semiconductor chip that are electrically isolated by an insulator reduces the degree of integration of circuits separated by an insulator. This also increases manufacturing costs compared to conventional circuits not separated by insulators.

The total area available for each electrically isolated island is specific to the process step used to form the isolation island on a wafer insulated by an insulator. determined by the allowable width. Typically, anisotropic wet etching of single crystal silicon wafers forms recesses large enough to accommodate the components. The recess made by anisotropic etching is 5
Since the walls have an inclination angle of 4 degrees, as a result, the area of the bottom of the recess is smaller than the area of the opening area on the wafer surface. The substrate is formed by coating these recesses with an insulating material and then filling the recesses. The formed substrate covers both the insulating material within the recess and the etched side of the wafer. This substrate, most often a polycrystalline silicon semiconductor material, is formed over an insulating material and serves as a support or base for structures formed in subsequent process steps. The surface topography of the substrate surface formed here is a rugged shape that closely resembles that of the etched surface of the underlying single crystal material. Since it is desirable to obtain a smooth surface in subsequent process steps, a substrate (bulk) removal process is performed to remove irregularities and smooth the substrate. Substrate removal is typically accomplished by a mechanical polishing or scraping process to remove substrate material until the irregularities are removed. Another substrate removal step is then used to remove most of the original single crystal silicon material until the bottom of the etched recess is exposed. Passive and active circuit components are then diffused into this exposed recessed section.

0004

Problem to be Solved: The anisotropic etch used to create isolation islands consumes large areas and creates large patches of unusable silicon surrounding individual isolated islands. . Typically, the width of the elongated region required to form the insulation around each island is about 35 microns. Because the regular walls of the island are slanted at an angle of 54 degrees, the island is much larger than would be required for a single component formed within it, and a large portion of the silicon area is sacrificed. It becomes. As a result of these, DIC circuits are less integrated than conventional circuits. These limitations, such as reduced integration and process complexity, have limited the use of DICs to a few applications, areas requiring improved performance or other features achieved through dielectric isolation.

It would therefore be desirable to have a method for forming wafers having insulator isolation regions that occupy a smaller percentage of the area than conventional insulation processing methods.

[0006]

SUMMARY OF THE INVENTION The objects and features of the present invention are achieved by coating one surface of a single crystal silicon wafer with an insulating material. This insulating material is then covered with a polycrystalline silicon material. A portion of the other side of the original silicon wafer is removed to form a thin layer of single crystal silicon. Another layer of single crystal silicon is then formed on the thinned surface of the single crystal silicon wafer. During etching, a trench is dug through the newly formed single crystal silicon and even through the original single crystal silicon wafer until it stops at the surface of the insulator layer. The trench is then filled with an insulating material to complete the formation of the isolation island.

[0007]

[Example] If it is possible to form island-like regions isolated by an insulator on a wafer without being affected by anisotropic etching that consumes chip area or bulk removal processes that are difficult to control, this will allow is the basis for producing densely packed wafers. The present invention makes it possible to create densely packed isolation islands with boundaries that are reliably defined and more controllable. In the method of the present invention, the isolation island region is formed as follows. First, an opening is formed completely through the planar single crystal silicon layer to the insulating material supporting the upper layer structure. These openings are then filled with an insulating material to form individual isolated islands of single crystal silicon.

This technique prevents the insulating material inherent in anisotropic etching of semiconductor materials from occupying large areas, and improves overall performance by creating precisely defined boundaries of isolation islands. It has the feature of space saving. As the area occupied by the insulator is reduced, more silicon islands can be used to form device elements, and the overall size of the islands is also reduced, allowing the islands to be placed closer together. becomes. All of these features combine to make isolation and
The packing density of isolation islands in an isolated wafer can be increased.

Various features of the invention will be described in more detail below with reference to the accompanying drawings. For ease of explanation, the invention will be described according to the example of layers of silicon and doping levels suitable for the fabrication of bipolar transistors. However, those skilled in the art will appreciate that layers of other materials, different doping levels, conductivity types, and geometries may be used to create different types of semiconductor devices. You'll understand.

FIG. 1 is an enlarged cross-sectional view of a wafer isolated by an insulator at an early stage of manufacture. Fabrication of dielectric isolated wafers according to the process of the present invention begins with a heavily doped single crystal semiconductor material 10 having a thickness sufficient to withstand subsequent process steps. Single crystal material 10 is heavily doped to favor the formation of bipolar transistors. Different doping levels can be used for other applications. The insulator layer 11 is made of single crystal material.
form on two sides. A substrate 12 is then formed on the surface of the insulating material. Substrate 12 serves as a base to support the entire structure isolated by insulators. In a preferred embodiment, silicon dioxide is grown over monocrystalline material 10 to form insulating layer 11 and polycrystalline silicon is grown over insulating layer 11 to form substrate 12. The substrate material 12 is formed to be thick enough to support the structure of the completed device and to withstand subsequent processing steps. The process of the present invention does not form recesses created by anisotropic etching on the wafer, as are formed with conventional insulator isolation circuit processing methods. As a result, the insulator 11 and the substrate 12
is formed as a planar structure, eliminating the need for bulk removal processes.

FIG. 2 shows an enlarged cross-sectional view of the structure obtained as a result of the next manufacturing process. The heavily doped single crystal material 10 is thinned to a predetermined thickness by chemical mechanical polishing or mechanical lapping. In a preferred embodiment, uniform single crystal material 10 provides a buried layer for a bipolar transistor structure. In this case, the monocrystalline material 10 serves as a buried layer contact to the collector region and as a conductor for the collector current. Since the thickness of this buried layer only needs to be thicker than the minimum thickness required for the buried layer as described above, there is no need to be very strict regarding polishing errors. Unlike traditional insulator isolation circuit processes, this thinning process does not have defined critical surfaces or locations.

FIG. 3 is an enlarged cross-sectional view of a dielectric isolated wafer after adding a new layer of single crystal silicon. After thinning the silicon material 10, a lower heavily doped single crystal material 13 is formed on the surface of the thinned heavily doped material. In a preferred embodiment, this material is epitaxially grown to form an epitaxial layer for forming the collector region of a bipolar transistor. The single crystal material 13 is doped to a lower concentration than the silicon material 10 so as to be suitable for forming bipolar transistors. Different doping levels can be used for other applications.

FIG. 4 is an enlarged cutaway sectional view of a wafer isolated with an insulator, showing the state before each independent island portion is isolated. Single crystal material 10, 13 is used to form the base of island 14. A deep narrow opening 16 with a wall 19 is formed by etching through both the monocrystalline semiconductor materials 13 and 10 and stopping at the insulating material 11, resulting in the formation of the base of the island 14. . Etching of materials 13 and 10 can also be performed by reactive ion etching or wet etching with KOH (potassium hydroxide) or equivalent material, which is conventionally used for etching dielectric isolation wafers. In a preferred embodiment, a mask defining the desired location of the opening is applied to the surface of material 13, and then materials 13 and 10 are etched by a reactive ion (plasma) etching process to form the surface of insulator 11. An opening with substantially vertical walls 19 is formed. Reactive ion etching does not significantly affect the insulating layer 11 of silicon dioxide, which acts as a protective layer against etching. This accommodates the unspecified etching time required to etch through material 10 having different thicknesses resulting from the thinning process described above.

FIG. 5 is an enlarged cutaway sectional view of a wafer isolated with an insulator, showing a state in which the periphery of each independent island-shaped portion is filled with an isolation material. The desired isolation is
This is achieved by filling the opening 16 with an insulating material and forming it so that it has a surface parallel to the single crystal material 13. In a preferred embodiment, the insulator consists of two major components. Silicon dioxide, the preferred insulating material, has a different coefficient of expansion than single crystal silicon, so using silicon dioxide alone will cause structural damage to the wafer. Therefore, the opening wall 19 is first oxidized to form a silicon dioxide film 17, and then the remaining portion of the opening is filled with polycrystalline silicon 18 to form an insulator. This two-step process forms a high quality insulator without damaging the wafer. Other materials with expansion coefficients approximating that of single crystal silicon, such as nitric oxide, polyimide, etc., can also be used to fill this opening.

The islands 14 are made of insulating materials 17 and 11, respectively.
It is completely surrounded by a combination of islands and completely electrically isolated from all other islands. Preparations for forming an active circuit or a passive circuit for each of the isolated island portions 14 are now complete.

It will therefore be appreciated that a novel method for forming individually isolated islands on an insulator isolated wafer has been provided. The isolated islands formed by the method of the present invention can be used to implement complete functional blocks such as high power radio frequency (RF) circuits, microwave bipolar transistors, high speed CMOS logic circuits, RF power amplifiers, etc. This is a suitable area for forming various circuits. This isolated area allows CMOS
Methods and means are provided for combining various types of components, such as combining a control circuit for a high power bipolar power amplifier. Individual islands produced by the method of the invention occupy less area than those produced by conventional methods. The effects of this reduction in occupied area ultimately result in improved manufacturing efficiency, lower costs, and smaller final products.

[Brief explanation of the drawing]

FIG. 1 is an enlarged cutaway cross-sectional view of an insulator isolated wafer illustrating a structure in which single crystal material is separated from a substrate by an insulator.

FIG. 2 shows the wafer of FIG. 1 after it has been thinned.

FIG. 3 shows the wafer of FIG. 2 with new layers added.

FIG. 4 shows the structure of the wafer of FIG. 3 after forming independent islands.

FIG. 5 shows the state of the wafer in FIG. 4 after filling the periphery of the island-shaped portion with isolation material.

[Explanation of symbols]

10 Single crystal semiconductor material 11 Insulating material 12 Polycrystalline semiconductor material 13 Single crystal semiconductor material 17 Insulating material 18 Insulating material

Claims (2)

[Claims] 1. A method of forming regions in a semiconductor wafer separated by an insulator, comprising: a uniformly highly doped single crystal semiconductor having a first conductivity type and having a first surface and a second surface; Preparing a material (10); forming a flat insulating material (11) having a first surface and a second surface on a second surface of the single crystal semiconductor material (10); forming a polycrystalline semiconductor material (12) on the second surface of the insulating material, one surface of the polycrystalline semiconductor material is in contact with a second surface of the heavily doped semiconductor material; removing a portion of a predetermined thickness from the first surface of the heavily doped semiconductor material (10) to make the thickness of the heavily doped semiconductor material uniform; reducing the amount of the semiconductor material (10) having the first conductivity type and the semiconductor material (10) on the first surface of the heavily doped semiconductor material (10);
0) forming a monocrystalline semiconductor material (13) doped to a lower concentration than that of 0), wherein one side of said lower heavily doped semiconductor material (13) remains exposed; From the exposed surface of said lower heavily doped semiconductor material (13) through said heavily doped semiconductor material (10) said insulating material (11)
) etching a deep narrow opening reaching a first surface of said lower heavily doped semiconductor material (13), said opening along said heavily doped semiconductor material (10); a wall surface and a bottom surface along the first side of the insulating material, the opening further opening at an exposed surface of the lower heavily doped semiconductor material (13); and filling said opening with an insulating material (17, 18). 2. A method of forming an electrically insulated semiconductor region, comprising: preparing a single crystal substrate (10) having a first surface and a second surface; the first surface of the single crystal substrate; covering the insulating material (11) with a layer of polycrystalline silicon (12); coating the second surface of the single crystal substrate with a layer of single crystal silicon (13);
) growing a layer of the single crystal silicon (13);
forming an insulated semiconductor region by etching a trench through the layer and the single crystal substrate (10);
and filling the trench with an insulating material.