JPH04243147A - Failure analyzing method of semiconductor device - Google Patents

Abstract

PURPOSE:To make a failure analysis possible with the aid of an electron beam tester by making a hole in the insulating film in the upper part of a ground wiring to let a part of lower conductor layer come to the surface and thereafter by burying tungsten in the hole covered with the insulating film and onto the insulating film of the surface. CONSTITUTION:A ground wiring 5 is formed by the use of a passivation film 6. By the use of a focused ion beam(FIB) apparatus, a hole 7 is made in the passivation film 6 and a metal film 8 is formed in the hole 7 and on the insulating film of the surface. Then, a hole is made in the metal film 8, the passivation film 6 is removed and a hole is made in a silicon nitride film 4. By the use of FIB, an oxide film is formed between the hole part and silicon nitride film 4, between the hole part and passivation film 6 and between the hole part and metal film 8 and in the top surface part of the metal film. The opening part is buried with tungsten and the electron beam of an electron beam tester is applied to the part. Thus, it is possible to measure potential without being affected by charging up through the passivation film 6.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for analyzing failures in semiconductor devices, and more particularly, to a method for analyzing failures in semiconductor devices using an electron beam tester.

0002

2. Description of the Related Art Conventionally, a failure analysis method for a semiconductor integrated circuit of this type has been performed by disposing an insulating film 13, a lower layer conductor wiring 14, an interlayer insulating film 15, and an upper layer conductor wiring 14 on a semiconductor substrate 12, as shown in FIG. 4(a). , an upper interlayer insulating film 15, and a passivation insulating film 16. When analyzed with an EB tester, as shown in FIG. A hole was made in the interlayer insulating film 14, a conductor pad 17 was formed on the hole, and the potential of the lower layer conductor wiring 14 was observed using an electron beam tester.

0003

[Problems to be Solved by the Invention] The conventional failure analysis method for semiconductor integrated circuits described above is difficult to solve because of local electrolytic Therefore, there was a drawback that failure analysis could not be performed using an electron beam tester. Another drawback is that failure analysis cannot be performed using an electron beam tester if charges are likely to accumulate in the passivation film around the conductor pads.

0004

[Means for Solving the Problems] A failure analysis method for a semiconductor device according to a first aspect of the invention is a failure analysis method for a semiconductor device having a diffusion region such as a semiconductor element, an insulating film for passivation, and a multilayer conductor wiring on a semiconductor substrate. In the analysis method, a first step of removing an insulating film on an upper part of a ground wire when analyzing a lower layer conductor wire among multilayer conductor wires on the semiconductor integrated circuit; a second step of forming a metal on the middle and surface insulating films and connecting it to the ground wiring, and forming the metal on the surface insulating film over and around the lower conductor wiring; a third step of removing the metal at the top of the layer; a fourth step of removing the passivation insulating film of the portion exposed by the third step; and an interlayer insulation layer of the portion exposed by the fourth step. a fifth step of partially making a hole in the interlayer insulating film so that the film is removed and a part of the lower conductor wiring is exposed to the surface; the periphery of the hole made in the fifth step and the side surface of the hole; a sixth step of forming an insulating film only on the surface of the hole; and a sixth step of forming a metal in the hole whose side surface is covered with an insulating film in the sixth step and on the insulating film on the surface and connecting it to the lower layer conductor wiring. In step 7, an electron beam is applied to the surface of the metal part and the potential is measured using a strobe scanning electron microscope (
and an eighth step of measuring and analyzing with an electron beam tester using an SEM).

A failure analysis method for a semiconductor device according to a second aspect of the invention includes means for partially making a hole in an insulating film above a ground wiring, forming a metal in the hole and on the insulating film on the surface, and means for forming metal on the surface insulating film over and around the lower conductor wiring; means for partially forming holes in the metal, insulating film, and interlayer insulating film over the lower conductor wiring; F as a means of forming an insulating film around the hole above the wiring and on the side of the hole, and a means of forming a metal in the hole whose side surface is covered with an insulating film and on the insulating film on the surface.
The system includes the use of an IB (focused ion beam) device.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. 1(a)-(c), FIG. 2(a)-(c), and FIG. 3 are cross-sectional views showing one embodiment of the present invention in the order of steps. This is an example applied to a method of failure analysis using a tester.

First, as shown in FIG. 1(a), a silicon oxide film 2 is formed on an n-type silicon semiconductor integrated circuit substrate 1, and a two-layer wiring of aluminum 3 is formed using a silicon nitride film 4 as an interlayer film. In the semiconductor integrated circuit in which the ground wiring 5 is formed using the passivation film 6, the first layer between the second layer wiring 3 made of aluminum is
When analyzing the layer wiring section 3, as shown in FIG. 1(b), the FI
Using a focused ion beam (B), a hole 7 is made in the passivation (insulating) film 6 so that the ground wiring 5 is exposed on the surface, and the hole 7 is made as shown in FIG. A metal film 8 is formed on the insulating film inside and on the surface, and connected to the ground wiring, and the metal film 8 is formed on the insulating film on the surface, over and around the lower layer conductor wiring.

Next, as shown in FIG. 2(a), a hole 9 is made in the metal film 8 so that the first layer aluminum wiring 3 on which failure analysis is to be performed is exposed, and a passivation (insulating) film 6 is formed.
is removed, and a hole 9 is made in the interlayer silicon nitride film 4. Next, as shown in FIG. 2(b), an FIB is used to determine the distance between the hole 9 and the interlayer silicon nitride film 4, and between the hole 9 and the passivation (insulating) film 6. Then, an oxide film is formed between the hole 9 and the metal 8 connected to the ground wiring and on the upper surface thereof. Next, as shown in FIG. 2C, the opening covered with the oxide film is filled with tungsten using FIB to form a tungsten pad 11.

Then, as shown in FIG. 3, this tungsten pad 11 is irradiated with an electron beam from an electron beam tester using a strobe device.

In this way, the second layer aluminum wiring 3
It is now possible to measure the potential of the first layer aluminum wiring 3, which is in close proximity, without being affected by local electric field effects, and to prevent failures using an electron beam tester without accumulating charges around the conductor pads. Can do analysis.

[0011]

[Effects of the Invention] As explained above, the present invention provides a semiconductor integrated circuit having multilayer conductor wiring, in which a hole is made in the insulating film above the ground wiring, and metal is formed in the hole and on the insulating film on the surface. , this metal is formed on the surface insulating film over and around the lower conductor wiring for which failure analysis is to be performed, and the metal, passivation film, and interlayer insulating film on top of the lower conductor wiring are removed, and the lower conductor wiring is removed. After exposing a part of the hole to the surface, cover only the area around the hole and the sides of the hole with an insulating film, and embed tungsten inside the hole whose sides are covered with the insulating film and on the insulating film on the surface. Form a tungsten pad.

Next, when the electron beam of the electron beam tester is applied to the tungsten pad, the entire surface of the surrounding passivation film is grounded, so the charge due to the electron beam is not accumulated, so there is no charge-up due to the passivation film. Not affected, and 1A
Since the influence of the electric field of L is blocked by the ground, the potential can be observed without being affected by local electric field effects, so there is an effect that failure analysis can be performed without changing the element characteristics.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(c) are cross-sectional views showing an embodiment of the present invention in the order of steps.

FIGS. 2(a) to 2(c) are cross-sectional views showing an embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view showing an embodiment of the present invention in the order of steps.

FIGS. 4(a) and 4(b) are cross-sectional views showing a conventional example.

[Explanation of symbols]

1 N-type silicon substrate 2 Silicon oxide film 3 Aluminum wiring 4 Silicon nitride film 5 Ground wiring 6 Passivation film 7 Opening by FIB 8 Metal film by FIB 9 Opening by FIB 10 Oxide film by FIB 11 Tungsten bud

Claims (2)

[Claims] 1. A failure analysis method for a semiconductor integrated circuit having a diffusion region for a semiconductor element or the like, an insulating film for passivation, and a multilayer conductor wiring on a semiconductor substrate, wherein a lower conductor of the multilayer conductor wiring on the semiconductor integrated circuit is provided. When analyzing the wiring, there is a first step of removing the insulating film on the top of the ground wiring, and a metal is formed in the hole opened in the first step and on the insulating film on the surface to connect to the ground wiring. a second step of forming the metal on the surface insulating film over and around the lower conductor wiring; a third step of removing the metal on the top of the lower conductor wiring; a fourth step of removing the passivation insulating film exposed in step 3; and a fourth step of removing the interlayer insulating film exposed in the fourth step so that a part of the lower conductor wiring is exposed to the surface. a fifth step of partially forming a hole in the interlayer insulating film; a sixth step of forming an insulating film only around the hole portion opened in the fifth step and on the side surface of the hole;
A seventh step of forming metal in the hole whose side surface is covered with an insulating film in the sixth step and on the insulating film on the surface thereof and connecting it to the lower layer conductor wiring, and forming an electron on the surface of the metal part. A beam is applied and the potential is measured using a strobe scanning electron microscope (S
an eighth step of performing measurement and analysis with an electron beam tester using EM). 2. Means for removing an insulating film on the upper part of the ground wiring, forming a metal in the hole and on the insulating film on the surface, and depositing the metal on the insulating film on the surface and on the lower layer conductor wiring. means for partially forming a hole in the metal, insulating film, and interlayer insulating film on the lower layer conductor wiring, and means for forming an insulating film around the hole and on the side surface of the hole; 2. The failure analysis method for a semiconductor device according to claim 1, wherein an FIB (focused ion beam) device is used as means for forming metal in the hole whose side surface is covered with an insulating film and on the insulating film on the surface.