JPH01135048A - Semiconductor device - Google Patents

Abstract

PURPOSE:To conduct precision analysis easily and rapidly with an EB tester by making a hole in the upper area of a measurement section of a multilayer interconnection formed on a semiconductor substrate so that it reaches the multilayer wiring and by burying an insulation film in the hole, of which etching speed is higher than that of its surrounding insulating film. CONSTITUTION:When analyzing by using an EB tester, a surface of a passivation film 6 is etched entirely by plasma etching. The surface of the passivation film 6 and the surface of an insulation film 7 which is buried in holes 3a, 5a are etched at the same time. Since the etching speed of siliconiteride which composes the insulation film 8 is higher than that of PSG which composes the passivation film 6 and an interlayer insulation film 4, the inner insulation film 7 of holes 3a, 5a is etched entirely while the surface of the passivation film 6 is etched a little. As a result, Al wirings 3, 5 of analysis area can be exposed while remaining the passivation film 6 and the interlayer insulation film 4 surrounding the holes 3a, 5a.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a technique that is effective when applied to a semiconductor device analysis technique using an electron beam tester.

[Conventional technology]

Analysis technology for semiconductor devices using an electron beam tester (hereinafter referred to as an EB tester) was discussed in the 93rd meeting of the 132nd Committee of the Japan Society for the Promotion of Science held on November 8 and 9, 1985.
125-130 of ``Research Conference Materials,'' which describes antistatic technology for insulating films.

In other words, operational analysis and failure analysis of semiconductor devices using an EB tester are performed by detecting secondary electrons emitted from the irradiated area when the surface of an operating chip is irradiated with an electron beam. If the insulator portion of the chip is charged by the electron beam, accurate observation of the potential contrast image will be hindered, so anti-static measures are essential.

Therefore, conventional methods include removing the protective film on the chip surface by etching, forming surface electrodes connected to internal wiring on the chip surface, and applying an antistatic agent to the chip surface.
Various antistatic technologies such as these have been put into practical use.

However, even if an antistatic agent is applied, it is not possible to effectively prevent the deterioration of analysis accuracy due to charging of the interlayer insulating film of multilayer wiring.Moreover, antistatic agents have the problem of causing contamination inside the EB tester. be.

Furthermore, the technique of forming a surface electrode electrically connected to an internal wiring on the surface of a chip hinders an increase in the degree of circuit integration, and therefore cannot be applied to highly integrated semiconductor devices.

Therefore, in order to accurately analyze a semiconductor device having multilayer wiring, it is effective to remove the protective film on the wiring by etching.

[Problem that the invention seeks to solve]

However, the inventor of the present invention has discovered that the technique for removing the protective film by etching has the following problems.

In other words, there are two methods for removing the protective film on the wiring: one is to etch the entire surface of the chip to expose the internal wiring, and the other is to selectively etch only the protective film at the measurement site. There are problems such as the parasitic capacitance of the insulating film being significantly reduced and even the necessary interlayer insulating film being etched.

On the other hand, in order to perform the latter selective etching, there are various methods such as photoresist/etching method (so-called spotrobo method), focused ion beam etching method, and laser beam etching method, but all of these methods only cover the protective film of the measurement area. Since the etching must be selectively etched, the etching speed becomes complicated and the throughput of the analysis process is reduced.

The present invention has been made focusing on the above problems,
The purpose is to provide a technology that allows an EB tester to perform accurate analysis simply and quickly.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a semiconductor device in which a hole reaching the multilayer wiring is formed above a measurement site of a multilayer wiring formed on a semiconductor substrate, and an insulating film having a higher etching rate than the surrounding insulating film is buried in the hole. It is.

[Effect]

According to the above method, by etching the entire surface during analysis using an EB tester, the insulating film inside the hole is etched more quickly than the insulating film around the hole, leaving the insulating film around the hole intact. The internal wiring of the measurement site can be exposed while the device is in place.

〔Example〕

FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view of a main part of this semiconductor device whose entire surface has been etched.

In the semiconductor device of this embodiment, a large number of circuit elements (not shown) are formed on a semiconductor substrate (hereinafter referred to as substrate) 1 made of a single crystal such as silicon, and each circuit element is connected by multilayer wiring. It is a MOS type semiconductor device.

The upper layer of the substrate l is made of PSG (phosphosil).
field oxide film 2 made of
is formed, and a first aluminum (Aβ) wiring 3 patterned into a predetermined shape is formed on the surface thereof.

The first AN wiring 3 is covered with an interlayer insulating film 4 made of PSG formed on the upper layer of the field oxide film 2, and the surface of this interlayer insulating film 40 is coated with a second aluminum (patterned into a predetermined shape). , to β) wiring 5 is formed.

The second Af wiring 5 and the circuit elements (not shown) are the same (
It is covered with a passivation film 6 made of PSG to protect it from the external environment.

Holes 3a and 5a reaching thereto are formed above predetermined locations of each /l wiring 3.5, respectively, and inside each hole 3a and 5a is an insulating film 7. made of silicon nitride (S13N1). 7 are buried.

Next, an example of the manufacturing process of the above semiconductor device will be explained.

First, according to the normal wafer process, an MO layer is placed on the substrate 1.
After forming the circuit elements of S, each circuit element and the second A
A passivation film 6 is obtained by depositing PSG on the surface of the f-wiring 5 by CVD.

Next, by photoresist/dry etching, holes 3a and 5a are formed above each predetermined location of the first Aβ wiring 3 and the second Af wiring 5, reaching the β wirings 3.5, respectively.

The locations where the holes 3a and 5a are drilled are each Aj? This is a location that is expected to be measured when the signal level of the current flowing through the wiring 3.5 is analyzed using an EB tester.

Finally, the holes 3a and 5 are
An insulating film 7 is obtained by embedding silicon nitride, which has a higher etching rate than PSG, into the inside of a.

The operating state of the semiconductor device manufactured in this way is
When analyzing with a tester, the entire surface of the passivation film 6 is etched by plasma etching.

Then, the surface of the passivation film 6 and the hole 3a.

The surface of the insulating film 7 embedded in the etching layer 5a is etched at the same time, but the etching rate of silicon nitride that makes up the insulating film 7 is about 10 times that of PSG that makes up the passivation film 6 and the interlayer insulating film 4. Therefore, while the surface of the passivation film 60 is slightly etched, the insulating film 7 inside the holes 3a and 5a is completely removed by etching (FIG. 2).

As a result, the passivation film 6 around the holes 3a and 5a
And A of the analysis part with the interlayer insulating film 4 left! By exposing the wiring 3.5 and directly irradiating each Af wiring 3.5 with an electron beam, their potential contrast images are clearly displayed on the image display section of the EB tester.

As described above, according to this embodiment, the following effects can be obtained.

(1) First and second Aβ formed on substrate 1
A1 wiring 3.5 is placed above the measurement site of wiring 3.5.
Holes 3a and 5a reaching the number 5 are drilled, respectively, and the number holes 3a,
By forming an MOS type semiconductor device in which an insulating film 7 made of silicon nitride, which has a higher etching rate than PSG constituting the passivation film 6 and the interlayer insulating film 4, is embedded inside the MOS semiconductor device 5a, silicon nitride can be removed by etching the entire surface. Since it is removed more quickly than PSG, it is possible to remove the AJ wiring at the measurement site while leaving the passivation film 6 and interlayer insulating film 4 around the holes 3a and 5a, without using selective etching, which requires a complicated process. 3
．． 5 can be exposed, and a decrease in the throughput of the analysis process can be effectively prevented.

(2), according to (1) above, A2 wiring 3.5 at the measurement site
Since the electron beam can be directly irradiated to the passivation film 6 and the interlayer insulating film 4, charge-up phenomenon due to charging of the passivation film 6 and the interlayer insulating film 4 is prevented, and a decrease in parasitic capacitance and necessary etching of the interlayer insulating film 4 are avoided, so the potential The observation accuracy of contrast images is improved, and defective locations can be detected quickly and accurately.

(3) The above (1) and (2) promote shortening of the development period of semiconductor devices.

As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.

For example, the material of the insulation film buried in the hole, the surrounding passivation film, and the interlayer insulation film is not limited to silicon nitride or PSG. The etching rate may be relatively higher than the etching rate of the film.

Further, the present invention can be applied not only to MOS type semiconductor devices but also to bipolar type semiconductor devices, and furthermore, it can be applied to these semiconductor devices having multilayer wiring of three or more layers. .

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, a semiconductor device in which a hole reaching the multilayer wiring is formed above a measurement site of a multilayer wiring formed on a semiconductor substrate, and an insulating film having a higher etching rate than the surrounding insulating film is buried in the hole. Therefore, by etching the entire surface during analysis with an EB tester, the insulating film inside the hole is etched more quickly than the insulating film around the hole, so measurements can be made with the insulating film around the hole left intact. The wiring of the part can be exposed.

As a result, defective locations can be detected quickly and accurately without reducing the throughput of the analysis process, and as a result, the product development period for semiconductor devices can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view of a main part of this semiconductor device whose entire surface has been etched. 1... Semiconductor substrate, 2... Field oxide film, 3.
5...AN wiring, 3a, 5a--hole, 4...FJ
interlayer insulating film, 6... passive vane film, 7... insulating film.

Claims (1)

[Scope of Claims] 1. A hole reaching the multilayer wiring is formed above the measurement site of the multilayer wiring formed on the semiconductor substrate, and an etching rate of the insulating film is lower than that of the insulating film surrounding the hole. A semiconductor device characterized by having a highly insulating film buried therein. 2. The semiconductor device according to claim 1, wherein the insulating film buried in the hole is silicon nitride, and the insulating film surrounding the hole is PSG. 3. The semiconductor device according to claim 2, wherein the semiconductor device is silicon nitride buried by a plasma CVD method. 4. The semiconductor device according to claim 1 or 2, which is a MOS type semiconductor device.