JPH04242460A - Communication controller - Google Patents

Abstract

PURPOSE:To obtain a communication controller which can prevent the conflict for acquisition of an internal bus and secure the high throughput accordant with a high transmission speed of a network. CONSTITUTION:A processor exclusive for each processing part where the communication protocol processing is carried out is provided to a host computer interface part 204, a circuit control part 206, and a protocol processing part 205 respectively. Then the protocol processing part buses 210-1 to 210-3 are provided for connection secured between each processor and a buffer memory part 207 in addition to the data buses 208-1 and 208-2 which secure the connection among those parts 204, 206 and 207.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a communication control device.
More specifically, the present invention relates to a communication control device that connects a computer and an information communication network.

0002

[Prior Art] As a conventional communication control device, there is a
Communication control devices described in Japanese Patent Application Laid-open No. 2-60044, Japanese Patent Application Laid-Open No. 62-60045, and Japanese Patent Application Laid-Open No. 62-279754 are known.

[0003] The communication control device described in Japanese Patent Application Laid-Open No. 62-60044 is designed to prevent memory contention from occurring when transmitting/receiving data and control information for transmitting/receiving are stored in the same memory. The memory for this and the memory for control information for transmission and reception are separate memories.

[0004] The communication control device described in Japanese Patent Application Laid-Open No. 62-60045 avoids access contention for the memory for transmitted and received data in the communication control device described in the above-mentioned Japanese Patent Application Laid-Open No. 62-60044. Therefore, an F with separate input and output lines is used as a memory for sending and receiving data.
It uses IFO.

The communication control device described in Japanese Patent Application Laid-Open No. 62-279754 aims to speed up communication protocol processing,
In order to improve the throughput of the communication control device, communication protocol processing is executed by hardware such as a matrix control circuit, an input event/state/address conversion circuit, an input event FIFO memory, and a state register.

[0006]

SUMMARY OF THE INVENTION The conventional communication control device described above uses separate memories, uses FIFO, and is provided with hardware for communication protocol processing.

However, since memory, FIFO, and hardware for communication protocol processing are connected to the same internal bus, there is a delay between data transfer for input/output of sent/received data and control information transfer for protocol processing. Causes internal bus acquisition contention. This means that communication protocol processing is interrupted during input/output of transmitted/received data, and parallel processing does not proceed. In other words, in the conventional communication control device,
There is a problem in that the throughput of the communication control device as a whole does not improve much due to competition for acquiring the internal bus.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a communication control device that prevents internal bus acquisition competition and provides high throughput commensurate with increased network transmission speed.

[0009]

[Means for Solving the Problems] In a first aspect, the present invention provides a host computer interface section that is located between a computer and a communication line and controls the interface with the computer, and a host computer interface section that is located between a computer and a communication line, and that controls the transmission and reception of data via the communication line. In a communication control device that includes a line control unit that performs transmission and reception, a protocol processing unit that executes communication protocol processing, and a buffer memory unit that stores transmitted and received data, a data bus that connects the line control unit and the buffer memory unit is A communication control device is provided, characterized in that it is provided with a protocol processing unit bus that connects a protocol processing unit and a buffer memory unit.

[0010] In a second aspect, the present invention provides a host computer interface unit that is located between a computer and a communication line and controls an interface with the computer, and a line control unit that transmits and receives data via the communication line. A communication control device that includes a protocol processing unit that executes communication protocol processing, and a buffer memory unit that stores transmitted and received data, executes communication protocol processing in each of the upper computer interface unit, line control unit, and protocol processing unit. A processor dedicated to each processing section is arranged, and a protocol processing section bus is provided that connects each processor and the buffer memory section separately from a data bus that connects the upper computer interface section, the line control section, and the buffer memory section. A communication control device is provided.

In a third aspect, the present invention provides transmission and reception communication between the processor of the host computer interface section and the processor of the protocol processing section and between the processor of the protocol processing section and the processor of the line control section in the above configuration. Provided is a communication control device characterized in that a FIFO is provided for the communication control device, and interface information is exchanged between processors via these FIFOs.

According to a fourth aspect, the present invention provides a command memory separate from the buffer memory for storing transmitted and received data in the above configuration, and stores the operations of each processor in a location on the command memory indicated by the interface information. A communication control device is provided, characterized in that a command descriptor for giving instructions is defined.

[0013]

[Operation] In the communication control device according to the first aspect, the data bus for data input/output and the protocol processing section bus for communication protocol processing are provided separately, so that the line control section accesses the buffer memory section. Access by the protocol processing unit to the buffer memory unit does not cause bus acquisition contention.

[0014] In the communication control device according to the second aspect,
Processors are placed in each section of the host computer interface section, protocol processing section, and line control section, and these processors are connected to a protocol processing section bus that is different from the data bus for data input/output. Accesses for data input/output of the interface section and line control section and accesses for communication protocol processing of each processor to the buffer memory section do not cause bus acquisition contention.

[0015] In the communication control device according to the third aspect,
Since inter-processor communication is performed using FIFO without using the protocol processing unit bus, the overhead for inter-processor communication is further reduced.

[0016] In the communication control device according to the fourth aspect,
Because the command memory was provided separately from the buffer memory,
Memory contention does not occur between data input/output processing and communication protocol processing, allowing these processing to proceed in parallel.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Note that the present invention is not limited thereby.

(First Embodiment) FIG. 2 is a configuration diagram showing an information communication network system 100. This information communication network system 100
is an end system consisting of a computer 101A and a communication control device 102A, and a computer 101B and a communication control device 10.
An end system consisting of a computer 2B and a computer 101C and a communication control device 102C are connected to a network 103. calculator 10
1A, 101B, and 101C have the same configuration,
The reference numeral 101 will be used below. Communication control device 102
A, 102B, and 102C each have the same configuration, and will be referred to as 102 below.

FIG. 3 shows a layered protocol in the information communication network 100. Taking OSI as an example, the structure of the layered protocol includes a physical layer L1, a data link layer L2 including an LLC sublayer and a MAC sublayer, a network layer L3, a transport layer L4, a session layer L5, and a presentation layer L6. , an application layer L7. Of these, physical layer L1
The communication control device 102 is in charge of four layers from the transport layer L4 to the transport layer L4, and the computer 101 is in charge of the three layers from the session layer L5 to the application layer L7.

FIG. 1 shows a computer 101 and a communication control device 10.
FIG. 2 is a block diagram showing the internal configuration of No. 2. FIG. Computer 101 includes a main memory 201, a main processor 202, and a system bus 203.

The communication control device 102 includes a host computer interface section 204 for interfacing with the computer 101, a line control section 206 for interfacing with the network 103, and a protocol processing section 205 for executing communication protocol processing. and a buffer memory section 207 for storing transmitted and received data.

The upper computer interface section 204 and the buffer memory section 207 are connected by a data bus 208-1 for inputting and outputting transmitted and received data. The line control section 206 and the buffer memory section 207 are connected by a data bus 208-2 for inputting and outputting transmitted and received data.

The upper computer interface section 204 and the protocol processing section 205 are connected by a protocol processing section bus 210-1 for processing communication protocols. Further, the host computer interface section 204 and the protocol processing section 205 have inter-processor information transmission means 209-1 for inputting and outputting transmission requests, reception notifications, etc. (hereinafter referred to as primitives).

[0024] Line control section 206 and protocol processing section 20
5 through a protocol processing unit bus 210-2 for communication protocol processing. In addition, the line control unit 2
06 and the protocol processing unit 205 have inter-processor information transmission means 209-2 for inputting and outputting primitives.

The protocol processing section 205 and the buffer memory section 207 are connected by a protocol processing section bus 210-3 for processing communication protocols.

FIG. 4 is a block diagram showing communication control device 102 in more detail. The upper computer interface unit 204 includes an upper interface processor 401, a local memory 402, a command memory 406, a command memory port control circuit 407, a DMAC 403, FIFOs 404 and 405, an upper interface bus 420, and a protocol processing bus. 210-4. The DMAC 403 is the main memory 201 of the computer 101.
Data transfer between the buffer memory section 207 and the buffer memory section 207 is performed. The FIFOs 404 and 405 are used for starting the communication control device 102 from the main processor 202 of the computer 101, and for notifying the main processor 202 of the computer 101 from the communication control device 102 of completion of processing.

The line control unit 206 is connected to the communication controller 4
15, MAC processor 413, and local memory 4
It consists of 14. The communication controller 415 sends and receives data to and from the transmission path of the network 103. The protocol processing unit 205 includes a protocol processing device 410.

The buffer memory section 207 includes a buffer memory 416 and a buffer memory access control section 417.

FIG. 5 is a block diagram showing the inside of the protocol processing device 410. Protocol processing device 410
is a data transfer processing unit 501A in charge of transport layer L4 processing, and a data link layer L2
It also includes a data transfer processing unit 501B in charge of network layer L3 processing, and a back-end processor 509.

The data transfer processing unit 501A includes a protocol processing circuit 502A and a reception output FIFO 503A.
, transmission input FIFO 504A, and reception input FIFO 5
05A, transmission output FIFO 506A, back-end processor (BEP) output FIFO 507A, and BEP
It consists of an input FIFO 508A. Reception output FIFO5
03A and transmission input FIFO 504A constitute inter-processor information transmission means 209-1.

Data transfer processing unit 501B has the same configuration as data transfer processing unit 501A. Reception input FIFO 505B and transmission output FIFO 506B
constitutes the inter-processor information transmission means 209-2. The back-end processor 509 includes a local memory 5
10 and a timer 511 are connected.

FIG. 6 is an expanded view of the buffer memory access control section 417 of the buffer memory section 207. The buffer memory access control unit 417 includes the bus selection circuit 6
01 and a buffer memory port control circuit 602.

The bus selection circuit 601 selects the data bus 208
-1, data bus 208-2, and data bus 208-
Connected to 3. Buffer memory port control circuit 6
02 is connected to the data bus 208-3, the protocol processing unit bus 210-3, and the buffer memory 416.

The bus selection circuit 601 selects the data bus 208
Arbitration is performed between an access request for data input/output to the buffer memory 416 via the data bus 208-1 and an access request for data input/output to the buffer memory 416 via the data bus 208-2.

The buffer memory port control circuit 602 includes:
Buffer memory 416 via data bus 208-3
Access requests for data input/output to the buffer memory 416 via the protocol processing unit bus 210-3
Arbitrates access requests for communication protocol processing. Inside the communication controller 415, there are a bus interface 603, a bus arbiter 604, and a MAC control circuit 605.

FIG. 7 shows the upper interface processor 4
01 is a conceptual diagram of a command descriptor that stores commands that instruct operations to the MAC processor 413 and the back-end processor 509 and information related thereto, and a buffer that stores transmitted data and received data. Command descriptors are defined on command memory 406. Buffers are defined on buffer memory 416.

The command descriptor has three entries E1, E2, and E3. Entry E1 is used for an interface between upper interface processor 401 and data transfer processing unit 501A. Entry E2
is used as an interface between the data transfer processing unit 501A and the data transfer processing unit 501B. Entry E3 is the data transfer processing unit 501B and MAC
It is used as an interface between processors 413.

Each entry E1, E2, E3 has a command field F1, a connection identification field F2, a data length field F3, and a buffer address field F.
Consists of 4. A command indicating a primitive between layers is set in the command field F1. For example, commands indicating primitives such as a connection setup request, connection establishment response, data transmission request, and connection release instruction are set. Connection identification field F
In 2? Transport class 4? Stores the connection identifier when using a connection-oriented protocol such as . The data length field F3 stores the data length in each layer L2, L3, and L4. The buffer address field F4 contains information for each layer L2,
Stores the start address of data in L3 and L4.

Next, an outline of the transmission operation and reception operation of the communication control device 102 will be explained with reference to FIGS. 4 and 5.

In the case of transmission, the computer 101 (its main processor 202) activates the upper interface processor 401 through the FIFO 404 (registers activation in the FIFO 404).

[0041] The upper interface processor 401 is
The DMAC 403 is activated to transfer commands from the computer 101 (its main processor 202) to the command memory 406 and analyze them. If the command is to send data,
Start up the DMAC 403 again.

DMAC 403 transfers transmission data from (main memory 201 of) computer 101 to buffer memory 416 via data bus 419-1 and buffer memory access control section 417.

[0043] The upper interface processor 401 is
A command descriptor is obtained from the command memory 406, necessary information is written therein, and its ID is registered in the transmission input FIFO 504A.

[0044] The protocol processing device 410 receives the transmission input F
The ID is taken out from the IFO 504A, and based on the ID, the command memory 406 is accessed via the protocol processing unit buses 210-1, 210-4 and the command memory port control circuit 407. It also accesses the buffer memory 416 through the upper interface bus 420, data bus 208-1, and buffer memory access control unit 417 to create a frame header and the like.

[0045] When the transmission protocol processing is completed, the protocol processing device 410 uses the ID of the command descriptor.
is registered in the transmission output FIFO 506B.

[0046] The MAC processor 413 has a transmission output FI
The communication controller 415 is activated based on the ID registered in the FO 506B.

The communication controller 415 connects the data bus 2
08-2 and the buffer memory access control unit 417, the transmission data is taken out from the buffer memory 416 and sent onto the network 103.

[0048] In the case of reception, the communication controller 415:
The frame on the network 103 is received, and the data bus 208-2 and buffer memory access control unit 417
The data is stored in the buffer memory 416 via the . and,
MAC processor 413 is activated.

The MAC processor 413 accesses the buffer memory 4 via the protocol processing unit buses 210-2 and 210-3 and the buffer memory access control unit 417.
16 to process the frame. It also accesses the command memory 406 via the protocol processing unit buses 210-2 and 210-4 and the command memory port control circuit 407 to create a command descriptor for frame reception. Furthermore, the ID of the command descriptor is registered in the reception input FIFO 505B of the protocol processing device 410.

The protocol processing device 410 accesses the buffer memory 416 via the protocol processing section buses 210-2 and 210-3 and the buffer memory access control section 417.
0-2 and 210-4 and the command memory port control circuit 407, the command memory 406 is accessed to execute protocol processing. Even during this protocol processing, the communication controller 415 can receive frames on the network 103 and store them in the buffer memory 416 via the data bus 208-2 and the buffer memory access control unit 417. this is,
This is because the internal buses used are different, and there is no bus acquisition conflict between protocol processing and frame input processing.

After completing the protocol processing, the protocol processing device 410 registers the ID of the command descriptor in the reception output FIFO 503A.

[0052] The upper interface processor 401
Command memory 406 via upper interface bus 420 and command memory port control circuit 407
access. Also, the DMAC 403 is activated. Further, a reception notification to the computer 101 is registered in the FIFO 405. The DMAC 403 takes out the received data from the buffer memory 416 via the buffer memory access control unit 417 and the data bus 419-1, and transfers it to (the main memory 201 of) the computer 101.

FIG. 8 is a transmission time chart showing the relationship between the operations of each processor during data transmission. calculator 1
When a data transmission request occurs at 01, the main processor 20
2 creates a command block and issues a data transmission request to the upper computer interface section 204 in the communication control device 102 (801).

Upon receiving the data transmission request, the upper interface processor 401 executes processing according to the command in the command block (this includes processing such as data copying using the DMAC 403 and division/assembly). Further, the upper interface processor 401 converts the command into a command descriptor format for starting the data transfer processing unit 501A, and converts the command into a command descriptor format for starting the data transfer processing unit 501A.
1A is activated (802).

The data transfer processing unit 501A executes data transmission processing using the command descriptor 701, and starts the data transfer processing unit 501B while requesting timer processing to the back end processor 509 (803).

The back-end processor 509 executes the requested timer processing (804). The data transfer processing unit 501B executes processing for data transmission (805). The MAC processor 413 uses the communication controller 415 (806) to send the transmission data onto the transmission path of the network 103 (807).

Next, the MAC processor 413 performs post-processing (808). That is, in order to release the transmission buffer and command descriptor, the command descriptor is input to the data transfer processing unit 501B (
809). Backend processor 509 releases the transmit buffer and command descriptor (810).

[0058] The AK packet from the other party is sent to network 1.
03 (811), the receiving process is performed in order (812-815).

FIG. 9 is a reception time chart showing the relationship between the operations of each processor when receiving data. When data is sent through the transmission path of network 103 (901
), the MAC processor 413 is notified.

After the MAC processor 413 performs reception processing such as associating the drive of the communication controller 415 and the command descriptor with the reception buffer (902
), the data transfer processing unit 501B is notified. The data transfer processing unit 501B performs predetermined processing (9
03), the data transfer processing unit 501A is notified.

The data transfer processing unit 501A performs predetermined processing (904) and notifies the upper interface processor 401. Also, backend processor 5
Request timer-related processing to 09. The upper interface processor 401 performs predetermined processing (905). The back-end processor 509 performs predetermined processing (9
06). Furthermore, after performing predetermined processing (904), the data transfer processing unit 501A notifies the data transfer processing unit 501B.

[0062] The data transfer processing unit 501B
Processing for packet transmission is performed (907), and the MAC processor 413 is notified. The MAC processor 413 processes the AK packet (908) and sends it to the transmission path of the network system 103 (909).

On the other hand, the upper interface processor 40
When the reception process (905) at computer 101 is completed, computer 101
The message is decrypted by the main processor 202 within the system (910). Furthermore, the buffer within the communication control device 102 is released (911, 912).

Next, the operation of each processor is shown in FIGS. 10 to 2.
This will be explained using the flowchart of 0.

FIG. 10 shows an overview of the transmission processing of the upper interface processor 401. If the message requested to be transmitted from the computer 101 is long, it must be divided into pieces that can be handled by the transport layer L4. Therefore, first, the message length and message start address are stored (1001, 1002).

Next, a command descriptor (CD) is obtained (1003). Then, information such as a command, data length, buffer address, etc. is set in the command descriptor (1004). Next, using the DMAC 403, data is transferred from (the main memory 201 of) the computer 101 to the buffer memory 416 (1005). Also,
The command descriptor ID (CD_ID) is registered in the transmission input FIFO 504A (1006).

Next, the message length is determined (1007
). If the message length exceeds 4K bytes, update the message length and message start address (10
08,1009). Then, the process returns to step 1003. If the message length does not exceed 4K bytes, end information is set in a command block (CB) used for exchanging information with the computer 101 (1010), and the command block is registered in the FIFO 405 (1011).

FIG. 11 shows an overview of the reception processing of the upper interface processor 401. It is determined whether the received data processed by the data transfer processing unit 501A is at the beginning of the message (1101). If it is the beginning, the message length (RM_LEN) and message beginning pointer (RM_ADR) are initialized (1102,
1103). If it is the beginning or after the above initialization is completed, the received data is stored in the computer 101 (the location pointed to by the message beginning pointer in the main memory 201) of the DMAC 4.
03 to transfer (1104). Next, the message length and message start address are updated (1105,
1106).

Next, it is determined whether this is the final data of the message (1107). If it is the final data, get the command block (1108), set the necessary items in the command block (1109), and send the command block to F.
Register in IFO 405 (1110). If the data is not the final data or the processing in steps 1108 to 1110 is bypassed, a buffer release request is set in the command descriptor (1111), and the reception output FIFO 503A is
Register the command descriptor ID in (1112
).

FIG. 12 shows the data transfer processing unit 501
An overview of the transmission process of A is shown below. Transmission input FIFO504A
Extract the ID of the command descriptor from (120
1).

Next, by looking at the command field F1 of the command descriptor, it is determined whether data is to be transmitted (1202). If the process is other than data transmission, the backend processor 509 is requested to perform the process (1206). For data transmission, create a header for the transmission buffer (1203), set necessary information in the command descriptor (1204), and send it to the transmission output FIFO 506A toward the lower data transfer processing unit 501B.
Register the command descriptor ID in (1205
).

[0072] Also, the back-end processor 509 is requested to perform timer-related processing (1206).

FIG. 13 shows the data transfer processing unit 501
An overview of A's reception processing is shown below. Receive input FIFO505A
Extract the ID of the command descriptor from (130
1).

Next, the type of packet is determined by looking at the receive buffer chained to the command descriptor (1302). If it is an AK packet, AK reception processing is performed using the command descriptor and reception buffer (1303). When receiving a data (DT) packet, the command descriptor and reception buffer are used to perform DT reception processing (1304), and the reception output FIFO 50 is sent to the host computer interface unit 204.
Register the command descriptor ID in 3A (13
05). Also, for AK return, the transmission output FIFO 506A is sent to the lower data transfer processing unit 501B.
Register the command descriptor ID in (1306
). Since the data transfer processing unit 501A does not process packets other than AK packets and DT packets, processing is requested to the back-end processor 509 (1307).

[0075] After processing the AK packet and DT packet,
Processing such as timer and queue operations is requested to the back-end processor 509 (1307).

FIG. 14 shows the data transfer processing unit 501
An overview of the transmission process of B is shown. Transmission input FIFO504B
Extract the ID of the command descriptor from (140
1) Create a header for the send buffer chained to the command descriptor (1402), set the necessary information in the command descriptor (1403), and
Register the ID of the command descriptor to the AC processor 413 in the transmission output FIFO 506B (140
4).

FIG. 15 shows the data transfer processing unit 501
An overview of the reception process of B is shown below. Receive input FIFO505B
Extract the ID of the command descriptor from (150
1).

By looking at the receive buffer chained to the command descriptor, it is determined whether the packet is data reception (1502). In the case of data reception, data reception processing is performed using the command descriptor and reception buffer (1503), and the ID of the command descriptor is registered in the reception output FIFO 503B for the upper data transfer processing unit 501A (1504). In cases other than data reception, the back-end processor 509 is requested to process it (1505).

FIG. 16 shows the backend processor 509
An outline of processing when the data transfer processing unit 501A receives a request is shown. Extract the command descriptor ID from the BEP input FIFO 508A (1601
).

Then, it is determined whether the request is for normal data transfer processing (1602).

[0081] If the request is not for normal data transfer processing,
Determine whether it is a buffer release request (1603), and if it is a release request, process it (1604), and if it is not a release request, execute transport abnormality processing (1605)
).

If the request is for normal data transfer processing, it is determined whether DT transmission is required (1606). If it is DT transmission,
The DT is registered in the response waiting queue (1607), and timer processing by DT transmission is performed (1608).

[0083] If it is not DT transmission, it is determined whether AK reception has occurred (1609). If it is an AK reception, the DT registered in the response waiting queue is released (1610), and the AK
Timer processing is performed upon reception (1611). If it is not an AK reception, it is a DT reception and that processing is performed (16
12).

FIG. 17 shows the backend processor 509
An overview of processing when the data transfer processing unit 501B receives a request is shown. Extract the command descriptor ID from the BEP input FIFO 508B (1701
), command field F1 of the command descriptor
to determine whether it is a buffer release request (1702
). If it is a buffer release request, execute the process (1
703) Do. If it is not a buffer release request, layer L
2. Performs abnormality processing for L3 (1704).

FIG. 18 shows an overview of the transmission activation process of the MAC processor 413. Extract the command descriptor ID from the transmission output FIFO 506B (1801)
, a descriptor in the chained transmission buffer is created from the command descriptor (1802).

Next, it is determined whether the transmission output FIFO 506B is empty (1803). If it is not empty, the send buffer is created in the chain (1804) and the process returns to step 1801 above. If it is empty, the communication controller 41
5 (1805), issues a transmission request (1806), and sets the first command descriptor address in the transmission completion wait pointer (1807).

FIG. 19 shows an overview of transmission completion processing by the MAC processor 413. When the communication controller 415 completes transmission, an interrupt is generated and the transmission completion processing flag is turned ON in the interrupt routine (1901).

In the transmission completion process, a transmission completion parameter is set in the command descriptor that is waiting for transmission completion (1902), the command descriptor is registered in the reception input FIFO 505B (1903), and the transmission completion processing flag is turned off. (1904).

FIG. 20 shows an overview of reception processing by the MAC processor 413. When the communication controller 415 receives data, an interrupt is generated and a reception processing flag is turned ON in the interrupt routine (2001).

In the receiving process, it is determined whether there is received data (2002). If there is no received data, turn off the reception processing flag and end the process (2008)
. If there is received data, it is determined whether a reception error has occurred (2003). If a reception error has occurred, the process moves to step 2007 below. If no reception error has occurred, get an empty command descriptor from the command descriptor pool (20
04), necessary information is set in the command descriptor and chained with the buffer (2005), and the ID of the command descriptor is registered in the reception input FIFO 505B (2006).

After processing one received data, update the receive buffer address for the next received data (20
07).

According to the first embodiment described above, the processing load within the communication control device 102 can be distributed among the upper interface processor 401, the protocol processing device 410, and the MAC processor 413. In addition, the bus load within the communication control device 102 is reduced to the inter-processor information transmission means 209-1, 209-2 between the respective processors, and the protocol processing unit buses 210-1, 210-2, 210-3, 2.
10-4 and data buses 208-1 and 208-2. Therefore, high-performance communication performance can be obtained.

(Second Embodiment) In the first embodiment, the protocol processing device 410 includes data transfer processing units 501A and 501B, which are hardware dedicated to protocol processing, and a back-end processor 509.
However, in the second embodiment, a microprocessor is used.

FIG. 21 is a block diagram of a protocol processing device 410 constructed using a microprocessor. That is, the protocol processing device 410 includes a high-speed microprocessor 2101 that executes protocol processing, a local memory 2102 for storing programs, a timer circuit 2103, FIFOs 2104 and 2105 for transmitting information with the upper interface processor 401, and an MA
It is composed of FIFOs 2106 and 2107 for communicating information with the C processor 413.

The protocol processing device 410 in FIG.
It is preferable to make this into one chip using SIC technology.

(Third Embodiment) In the first and second embodiments, processors were placed in the host computer interface section 204, protocol processing section 205, and line control section 206, but in the third embodiment, A processor is placed only within the communication control device 102.

FIG. 22 shows the separation of the data bus 2206 and the protocol processing unit bus 2301 when a processor is placed only in the communication control device 102.

Computer 101 and buffer memory section 2203
The data input/output path between them is the DMAC 2205 and the data bus 2206. A data input/output path between the network 103 and the buffer memory section 2203 is a communication controller 2204 and a data bus 2206.

On the other hand, a route for protocol processing between the protocol processing section 2201 and the buffer memory section 2203 is the protocol processing section bus 2301.

According to the configuration of the third embodiment, high communication performance can be obtained because no bus acquisition competition occurs between data input/output and protocol processing.

[0101] The third embodiment is suitable for cases where it is not possible hardware-wise to arrange a plurality of processors in the communication control device, or when the processing speed of the processor is sufficiently high.
This method is effective when the processor can sufficiently handle the network transmission speed.

[0102]

[Effects of the Invention] According to the communication control device of the present invention, there is no competition between bus acquisition for data input/output processing and bus acquisition for communication protocol processing, so these processes can be carried out even more in parallel. .

[0103] Furthermore, since communication protocol processing is shared among multiple processors, the parallelism of processing is further increased.

Furthermore, since the protocol processing unit bus is not used for inter-processor communication, the parallelism of processing is further increased in this respect as well.

As described above, it is possible to provide a communication control device that executes communication protocol processing at high speed and has a high throughput commensurate with the network transmission speed.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a communication control device of the present invention.

FIG. 2 is a configuration diagram showing an example of an information communication network system.

FIG. 3 is a conceptual diagram of a layered protocol in an information communication network.

FIG. 4 is a detailed block diagram of the communication control device of the present invention.

FIG. 5 is an internal block diagram of the protocol processing device shown in FIG. 4.

FIG. 6 is an expanded block diagram of the buffer memory access control section of FIG. 4;

FIG. 7 is a conceptual diagram of a command descriptor and a buffer.

FIG. 8 is a time chart showing the operation relationship of each processor during data transmission.

FIG. 9 is a time chart showing the relationship between the operations of each processor when receiving data.

FIG. 10 is a flowchart of transmission processing by the upper interface processor.

FIG. 11 is a flowchart of reception processing by a higher-level interface processor.

FIG. 12 is a transmission processing flowchart of the data transfer processing unit 501A.

FIG. 13 is a flowchart of the reception process of the data transfer processing unit 501A.

FIG. 14 is a transmission processing flowchart of the data transfer processing unit 501B.

FIG. 15 is a flowchart of the reception process of the data transfer processing unit 501B.

FIG. 16 is a flowchart of layer L4 processing of the back-end processor.

[Figure 17] Layers L2 and L3 of back-end processor
Processing flowchart.

FIG. 18 is a flowchart of the transmission activation process of the MAC processor.

FIG. 19 is a flowchart of transmission completion processing of the MAC processor.

FIG. 20 is a flowchart of reception processing of the MAC processor.

FIG. 21 is a block diagram of a protocol processing device according to a second embodiment of the present invention.

FIG. 22 is a block diagram of a communication control device according to a third embodiment of the present invention.

[Explanation of symbols]

101 Computer 102 Communication control device 103 Network 204 Upper computer interface section 207 Buffer memory section 205 Protocol processing section 206 Line control section 208-1, 208-2 Data bus 209-1, 2
09-2 Inter-processor information transmission means 210-1 to 2
10-4 Protocol processing section bus 401 Upper interface processor 406 Command memory 410 Protocol processing device 413 MAC processor 416 Buffer memory 420 Upper interface section bus 501A, 501B Data transfer processing unit 502
A, 502B Protocol processing circuit 503A, 503
B Reception output FIFO 504A, 504B Transmission input FIFO 506A Reception input FIFO 506B Transmission output FIFO 507A, 507B BEP output FIFO 508A,
508B BEP input FIFO 509 Back end processor 601 Bus selection circuit 602 Buffer memory port control circuit 701 Command descriptor 702 Buffer

Claims (5)

[Claims] [Claim 1] A host computer interface unit located between a computer and a communication line and controlling an interface with the computer, a line control unit that sends and receives data via the communication line, and executes communication protocol processing. In a communication control device that includes a protocol processing unit and a buffer memory unit that stores transmitted and received data, a protocol processing unit bus that connects the protocol processing unit and the buffer memory unit is separate from a data bus that connects the line control unit and the buffer memory unit. What is claimed is: 1. A communication control device characterized in that an access by a line control unit to a buffer memory unit and an access by a protocol processing unit to a buffer memory unit do not cause bus acquisition contention. [Claim 2] A host computer interface unit located between the computer and the communication line and controlling the interface with the computer, a line control unit that transmits and receives data via the communication line, and executes communication protocol processing. In a communication control device that includes a protocol processing unit and a buffer memory unit that stores transmitted and received data, a processor dedicated to each processing unit that executes communication protocol processing is placed in each of the upper computer interface unit, line control unit, and protocol processing unit. In addition to the data bus that connects the upper computer interface section and line control section with the buffer memory section, a protocol processing section bus is provided that connects each of the processors and the buffer memory section, and the upper computer interface section and line to the buffer memory section are connected to the upper computer interface section and the line control section. A communication control device characterized in that accesses for data input/output by a control unit and accesses for communication protocol processing by each processor to a buffer memory unit do not cause bus acquisition contention. 3. FIFOs for transmission and reception are provided between the processor of the host computer interface section and the processor of the protocol processing section, and between the processor of the protocol processing section and the processor of the line control section;
3. The communication control device according to claim 2, wherein interface information is exchanged between the processors via the communication control device. 4. A command memory is provided separately from a buffer memory for storing transmitted and received data, and a command descriptor for instructing the operation of each processor is defined at a location on the command memory indicated by the interface information. A communication control device according to claim 2 or 3. 5. Connecting the data bus on the upper computer interface side and the data bus on the line control unit side to the data bus on the buffer memory side via a bus selection circuit, and connecting the data bus on the buffer memory side and the protocol processing unit. A bus is connected to the buffer memory via a buffer memory port control circuit, and the bus selection circuit receives an access request for data input/output to the buffer memory of the upper computer interface section and an access request for data input/output to the buffer memory of the line control section. The buffer memory port control circuit arbitrates access requests for input/output, and the buffer memory port control circuit arbitrates access requests for data input/output to the buffer memory via the data bus on the buffer memory side and via the protocol processing unit bus. 5. The communication control device according to claim 2, wherein the communication control device arbitrates access requests for communication protocol processing to all buffer memories.