JP3360138B2 - Communication control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control device,
More specifically, the present invention relates to a communication control device that connects a computer and an information communication network.

[0002]

2. Description of the Related Art A conventional communication control device is disclosed in
There are known communication control devices described in Japanese Patent Application Laid-Open Nos. 2-60044, 62-60045 and 62-279754.

The communication control device described in Japanese Patent Application Laid-Open No. 62-60044 discloses a communication control apparatus for transmitting and receiving data in order to avoid a memory conflict when transmitting and receiving data and control information for transmission and reception are stored in the same memory. And a memory for control information for transmission and reception are separate memories.

The communication control device described in Japanese Patent Application Laid-Open No. 62-60045 avoids the occurrence of contention for access to the transmission / reception data memory in the communication control device described in Japanese Patent Application Laid-Open No. 62-60044. Therefore, as a memory for transmission / reception data, F having an input line and an output line separately
The IFO was used.

The communication control device described in Japanese Patent Application Laid-Open No. 62-279754 aims to speed up communication protocol processing,
In order to improve the throughput of the communication control device, communication protocol processing is executed by hardware such as a matrix control circuit, an input event state address conversion circuit, an input event FIFO memory, and a state register.

[0006]

In the above-mentioned conventional communication control device, a memory is divided, a FIFO is used, and hardware for processing a communication protocol is provided.

However, since the memory, the FIFO, and the hardware for processing the communication protocol are connected to the same internal bus, the transfer between the data transfer for input / output of transmission / reception data and the control information transfer for the protocol processing is performed. Contention for internal bus acquisition occurs. This means that the communication protocol processing is interrupted during input / output of transmission / reception data, and the processing does not proceed in parallel. That is, in the conventional communication control device,
There is a problem that the throughput of the communication control device as a whole does not improve so much due to contention for the internal bus.

SUMMARY OF THE INVENTION An object of the present invention is to provide a communication control apparatus capable of preventing contention for internal bus acquisition and obtaining a high throughput corresponding to an increase in network transmission speed.

[0009]

According to a first aspect of the present invention, there is provided a host computer interface unit located between a computer and a communication line for controlling an interface with the computer, and transmitting and receiving data via the communication line. and line control unit for performing, send
A buffer memory for storing received data,
Executes protocol processing on the data stored in the memory
In a communication control device including a protocol processing unit to perform, a protocol processing unit bus connecting the protocol processing unit and the buffer memory unit is provided separately from the data bus connecting the host computer interface unit and the line control unit and the buffer memory unit, host computer Intafe to the server Ffamemori part
And access over scan portion or line control unit, and access protocol processing portion of the buffer memory unit to provide a communication control device being characterized in that so as not to cause bus acquisition contention.

[0010] de In a second aspect, the present invention is located between the computer communication network, via the host computer interface unit for controlling the interface with the computer, a communication line
Storing a line control unit, the transmission and reception data for transmitting and receiving over data
Buffer memory section and the buffer memory section
That performs protocol processing on the data
In the communication control device comprising a processing unit, host computer interface unit, the line control unit, arranged processor dedicated processing units for executing each communication protocol processing of protocol processing section, the upper level computer interface unit and line control unit access for the buffer to the data bus connecting the memory portion is provided separately from the protocol processing unit bus connecting said respective processor and the buffer memory unit, the host computer interface unit and line control unit of the data input and output to and from the server Ffamemori unit If, to provide a communication control apparatus and the access for communication protocol processing of each processor to the buffer memory unit is characterized in that so as not to cause bus acquisition contention.

According to a third aspect of the present invention, in the above configuration, the transmission and reception between the processor of the host computer interface unit and the processor of the protocol processing unit and between the processor of the protocol processing unit and the processor of the line control unit are performed. A communication control device is provided, wherein a communication FIFO is provided, and interface information is exchanged between processors via these FIFOs.

According to a fourth aspect of the present invention, in the above configuration, a command memory is provided separately from a buffer memory for storing transmission / reception data, and an operation of each processor is stored in a location on the command memory indicated by interface information. There is provided a communication control device characterized by defining a command descriptor to be instructed.

[0013]

In the communication control device according to the first aspect, the data bus for data input / output and the protocol processing unit bus for communication protocol processing are provided separately, so that the access of the line control unit to the buffer memory unit can be reduced. Access of the protocol processing unit to the buffer memory unit does not cause bus contention.

In the communication control device according to the second aspect,
Processors are arranged in the host computer interface unit, protocol processing unit, and line control unit, and these processors are connected to a protocol processing unit bus different from the data bus for data input / output. The access for data input / output of the interface unit and the line control unit and the access for the communication protocol processing of each processor to the buffer memory unit do not cause a bus acquisition conflict.

In the communication control device according to the third aspect,
Since the inter-processor communication is performed using the FIFO without using the protocol processing unit bus, the overhead for the inter-processor communication is further reduced.

In the communication control device according to the fourth aspect,
Because a command memory is provided separately from the buffer memory,
No memory competition occurs between the data input / output processing and the communication protocol processing, and these processings can be further advanced in parallel.

[0017]

An embodiment of the present invention will be described below with reference to the drawings. Note that the present invention is not limited by this.

(First Embodiment) FIG. 2 is a configuration diagram showing an information communication network system 100. This information communication network system 100
Is an end system including a computer 101A and a communication control device 102A, and a computer 101B and a communication control device 10A.
2B and an end system including a computer 101C and a communication control device 102C are connected to a network 103. Computer 10
1A, 101B and 101C have the same configuration, respectively.
Hereinafter, the reference numeral is set to 101. Communication control device 102
A, 102B, and 102C have the same configuration, and the reference numeral is hereinafter referred to as 102.

FIG. 3 shows a layered protocol in the information communication network 100. Taking the configuration of the hierarchical protocol as an example of OSI, the physical layer L1, the data link layer L2 including the LLC sublayer and the MAC sublayer, the network layer L3, the transport layer L4, the session layer L5, and the presentation layer L6 , And an application layer L7. Physical layer L1
To the transport layer L4, and the communication control device 102, and the computer 101 covers three layers from the session layer L5 to the application layer L7.

FIG. 1 shows a computer 101 and a communication control device 10.
FIG. 2 is a block diagram showing an internal configuration of the second embodiment. Computer 101
Includes a main memory 201, a main processor 202, and a system bus 203.

The communication control unit 102 includes a host computer interface unit 204 for interfacing with the computer 101, a line control unit 206 for interfacing with the network 103, and a protocol processing unit 205 for executing communication protocol processing. And a buffer memory unit 207 for storing transmission / reception data.

The host computer interface unit 204 and the buffer memory unit 207 are connected by a data bus 208-1 for inputting / outputting transmission / reception data. The line control unit 206 and the buffer memory unit 207 are connected by a data bus 208-2 for inputting / outputting transmission / reception data.

The host computer interface unit 204 and the protocol processing unit 205 are connected by a protocol processing unit bus 210-1 for processing a communication protocol. In addition, the host computer interface unit 204 and the protocol processing unit 205 have an inter-processor information transmission unit 209-1 for inputting and outputting a transmission request, a reception notification, and the like (hereinafter, these are referred to as primitives).

Line control unit 206 and protocol processing unit 20
5 is connected by a protocol processing unit bus 210-2 for communication protocol processing. Line control unit 2
06 and the protocol processing unit 205 have inter-processor information transmission means 209-2 for inputting and outputting primitives.

The protocol processor 205 and the buffer memory 207 are connected by a protocol processor bus 210-3 for communication protocol processing.

FIG. 4 is a block diagram showing the communication control device 102 in further detail. The host computer interface unit 204 includes a host interface processor 401, a local memory 402, a command memory 406, a command memory port control circuit 407, and a DMAC 403.
, FIFOs 404 and 405, a higher-level interface bus 420, and a protocol processor bus 210-4. The DMAC 403 is the main memory 20 of the computer 101
1 and the buffer memory unit 207.
The FIFOs 404 and 405 are used to activate the communication control device 102 from the main processor 202 of the computer 101 and to notify the main processor 202 of the computer 101 of the end of the processing from the communication control device 102.

The line control unit 206 includes the communication controller 4
15, the MAC processor 413, and the local memory 4
14. The communication controller 415 sends and receives data to and from the transmission path of the network 103. The protocol processing unit 205 includes a protocol processing device 410.

The buffer memory unit 207 includes a buffer memory 416 and a buffer memory access control unit 417.

FIG. 5 is a block diagram showing the inside of the protocol processing device 410. Protocol processing device 410
Represents a data transfer processing unit 501A that performs processing of the transport layer L4 and a data link layer L2.
And a data transfer processing unit 501B for performing the processing of the network layer L3, and a back-end processor 509.

The data transfer processing unit 501A includes a protocol processing circuit 502A and a reception output FIFO 503A.
, A transmission input FIFO 504A and a reception input FIFO 5
05A, transmission output FIFO 506A, back-end processor (BEP) output FIFO 507A, and BEP
And an input FIFO 508A. Receive output FIFO5
03A and the transmission input FIFO 504A constitute the inter-processor information transmission means 209-1.

The data transfer processing unit 501B has the same configuration as the data transfer processing unit 501A. Receive input FIFO 505B and transmit output FIFO 506B
Constitute the inter-processor information transmission means 209-2.
The back-end processor 509 has a local memory 5
10 and a timer 511 are connected.

FIG. 6 is an expanded view of the buffer memory access control unit 417 of the buffer memory unit 207. The buffer memory access control unit 417 controls the bus selection circuit 6
01 and a buffer memory port control circuit 602.

The bus selection circuit 601 is connected to the data bus 208
-1, data bus 208-2, and data bus 208-
3 is connected. Buffer memory port control circuit 6
02 is connected to the data bus 208-3, the protocol processing unit bus 210-3, and the buffer memory 416.

The bus selection circuit 601 is connected to the data bus 208
-1 and an access request for inputting and outputting data to and from the buffer memory 416 via the data bus 208-2 are arbitrated.

The buffer memory port control circuit 602 includes:
Buffer memory 416 via data bus 208-3
Access request for data input / output to / from the buffer memory 416 via the protocol processing unit bus 210-3.
Arbitrates access requests for communication protocol processing to The communication controller 415 includes a bus interface 603, a bus arbiter 604, and a MAC control circuit 605.

FIG. 7 shows the upper interface processor 4.
FIG. 11 is a conceptual diagram of a command descriptor for storing commands instructing operations to the MAC processor 413 and the back-end processor 509 and information related thereto, and buffers for storing transmission data and reception data.
The command descriptor is defined on the command memory 406. The buffer is defined on the buffer memory 416.

The command descriptor has three entries E1, E2 and E3. The entry E1 is used for an interface between the upper interface processor 401 and the data transfer processing unit 501A. Entry E2
Is used for an interface between the data transfer processing unit 501A and the data transfer processing unit 501B. The entry E3 includes the data transfer processing unit 501B and the MAC
Used for an interface between the processors 413.

Each entry E1, E2, E3 has a command field F1, a connection identification field F2, a data length field F3, a buffer address field F
Consists of four. In the command field F1, a command indicating a primitive between layers is set. For example, commands indicating primitives such as a connection setting request, a connection establishment response, a data transmission request, and a connection release instruction are set. Connection identification field F
For 2, Transport class 4? Stores a connection identifier when a connection-type protocol such as is used. The data length in each layer L2, L3, L4 is stored in the data length field F3.
In the buffer address field F4, each layer L2,
The head address of the data in L3 and L4 is stored.

Next, an outline of the transmission operation and the reception operation of the communication control apparatus 102 will be described with reference to FIGS.

In the case of transmission, (the main processor 202 of) the computer 101 activates the higher-level interface processor 401 through the FIFO 404 (registration of activation in the FIFO 404).

The upper interface processor 401
The DMAC 403 is activated, and a command from the computer 101 (the main processor 202 thereof) is transferred to the command memory 406 for analysis. If the command is data transmission,
The DMAC 403 is started again.

The DMAC 403 transfers transmission data from (the main memory 201 of) the computer 101 to the buffer memory 416 via the data bus 419-1 and the buffer memory access control unit 417.

The upper interface processor 401
A command descriptor is obtained from the command memory 406, necessary information is written into the command descriptor, and its ID is registered in the transmission input FIFO 504A.

The protocol processing unit 410 receives the transmission input F
The ID is extracted from the IFO 504A, and the command memory 406 is accessed via the protocol processing unit buses 210-1 and 210-4 and the command memory port control circuit 407 based on the ID. The buffer memory 416 is accessed through the upper interface bus 420, the data bus 208-1, and the buffer memory access controller 417, and a frame header is created.

When the transmission protocol processing is completed, the protocol processing device 410
Is registered in the transmission output FIFO 506B.

The MAC processor 413 has a transmission output FI
The communication controller 415 is activated based on the ID registered in the FO 506B.

The communication controller 415 is connected to the data bus 2
The transmission data is extracted from the buffer memory 416 via 08-2 and the buffer memory access control unit 417, and is sent out onto the network 103.

In the case of reception, the communication controller 415
The frame on the network 103 is received, and the data bus 208-2 and the buffer memory access control unit 417 are received.
Is stored in the buffer memory 416. And
Activate the MAC processor 413.

The MAC processor 413 controls the buffer memory 4 via the protocol processing unit buses 210-2 and 210-3 and the buffer memory access control unit 417.
16 to perform frame processing. The command memory 406 is accessed via the protocol processing unit buses 210-2 and 210-4 and the command memory port control circuit 407 to create a command descriptor for frame reception. Further, the ID of the command descriptor is registered in the reception input FIFO 505B of the protocol processing device 410.

The protocol processing unit 410 accesses the buffer memory 416 via the protocol processing unit buses 210-2 and 210-3 and the buffer memory access control unit 417.
The command memory 406 is accessed via 0-2 and 210-4 and the command memory port control circuit 407 to execute protocol processing. Even during this protocol processing, the communication controller 415 can receive a frame on the network 103 and store it in the buffer memory 416 via the data bus 208-2 and the buffer memory access control unit 417. this is,
This is because the internal bus used is different, and no bus acquisition conflict occurs between the protocol processing and the frame input processing.

The protocol processing device 410 that has completed the protocol processing registers the ID of the command descriptor in the reception output FIFO 503A.

The upper interface processor 401
The command memory 406 via the upper interface section bus 420 and the command memory port control circuit 407
To access. Also, the DMAC 403 is started. Further, a reception notification to the computer 101 is registered in the FIFO 405. The DMAC 403 extracts the received data from the buffer memory 416 via the buffer memory access control unit 417 and the data bus 419-1, and transfers the data to (the main memory 201 of) the computer 101.

FIG. 8 is a transmission time chart showing the relationship between the operations of the processors at the time of data transmission. Calculator 1
01, the main processor 20
2 creates a command block and issues a data transmission request to the host computer interface unit 204 in the communication control device 102 (801).

Upon receiving the data transmission request, the upper interface processor 401 executes processing according to the command of the command block (this includes processing such as data copying using the DMAC 403 and division / assembly).
Further, the upper interface processor 401 converts the command into a command descriptor format for starting the data transfer processing unit 501A,
1A is started (802).

The data transfer processing unit 501A executes data transmission processing using the command descriptor 701, and activates the data transfer processing unit 501B while requesting the backend processor 509 to perform timer processing (803).

The back-end processor 509 executes the requested timer process (804). The data transfer processing unit 501B executes processing for data transmission (805). Using the communication controller 415 (806), the MAC processor 413 sends the transmission data to the transmission path of the network 103 (807).

Next, the MAC processor 413 performs post-processing (808). That is, the command descriptor is input to the data transfer processing unit 501B to release the transmission buffer and the command descriptor (809). The back-end processor 509 releases the transmission buffer and the command descriptor (81
0).

The AK packet from the other party is transmitted to the network 1
When the data is transmitted through the transmission path 03 (811), the reception processing is sequentially executed (812-815).

FIG. 9 is a reception time chart showing the relationship between the operation of each processor when receiving data. When data is transmitted on the transmission path of the network 103 (90
1) The MAC processor 413 is notified.

The MAC processor 413 performs a reception process such as associating the drive of the communication controller 415 and the command descriptor with the reception buffer (90).
2) Notify the data transfer processing unit 501B. The data transfer processing unit 501B performs a predetermined process (903) and notifies the data transfer processing unit 501A.

The data transfer processing unit 501A performs a predetermined process (904) and notifies the upper interface processor 401. Also, the back-end processor 5
09 to request timer-related processing. The upper interface processor 401 performs a predetermined process (905). The back-end processor 509 performs a predetermined process (9
06). After performing the predetermined processing (904), the data transfer processing unit 501A notifies the data transfer processing unit 501B.

The data transfer processing unit 501B has an AK
A process for packet transmission is performed (907), and the MAC processor 413 is notified. MAC processor 413
Processes the AK packet (908) and sends it out to the transmission path of the network system 103 (909).

On the other hand, the upper interface processor 40
When the receiving process (905) in the PC 1 is completed, the computer 101
The message is decrypted by the main processor 202 in (910). The buffer is released in the communication control device 102 (911, 912).

Next, the operation of each processor will be described with reference to FIGS.
0 will be described.

FIG. 10 shows an outline of the transmission processing of the upper interface processor 401. If the message requested to be transmitted from the computer 101 is long, it must be divided into a size that can be handled by the transport layer L4. Therefore, first, the message length and the message start address are stored (1001, 1002).

Next, a command descriptor (CD) is obtained (1003). Then, information such as a command, a data length, and a buffer address is set in the command descriptor (1004). Next, data is transferred from the computer 101 (the main memory 201) to the buffer memory 416 by using the DMAC 403 (1005). Also,
The command descriptor ID (CD_ID) is registered in the transmission input FIFO 504A (1006).

Next, the message length is determined (100
7). If the message length exceeds 4K bytes,
Update message length and message start address (1
008, 1009). Then, the process returns to step 1003. If the message length does not exceed 4 Kbytes, end information is set in a command block (CB) used for exchanging information with the computer 101 (1010), and the command block is registered in the FIFO 405 (1011).

FIG. 11 shows an outline of the reception processing of the upper interface processor 401. It is determined whether the data received by the data transfer processing unit 501A is the head of a message (1101). If it is the head, the message length (RM_LEN) and the message head pointer (RM_ADR) are initialized (1102,
1103). If it is the head or if the above initialization is completed, the received data is stored in the computer 101 (at the location pointed to by the message head pointer of the main memory 201) in the DMAC4.
03 is transferred (1104). Next, the message length and the message start address are updated (1105,
1106).

Next, it is determined whether the data is the last data of the message (1107). If it is the last data, a command block is obtained (1108), necessary items are set in the command block (1109), and the command block is set to F
It is registered in the IFO 405 (1110). If the data is not the final data or if the processing in steps 1108 to 1110 is the main bypass, a buffer release request is set in the command descriptor (1111), and the reception output FIFO 503A is set.
The ID of the command descriptor is registered in (111)
2).

FIG. 12 shows a data transfer processing unit 501.
The outline of the transmission process of A is shown. Transmission input FIFO 504A
From the command descriptor (120)
1).

Next, it is determined whether data transmission is to be performed by looking at the command field F1 of the command descriptor (1202). If the processing is other than data transmission, the processing is requested to the back-end processor 509 (1206). In the case of data transmission, a header of the transmission buffer is created (1203), necessary information is set in the command descriptor (1204), and the transmission output FIFO 506 is sent to the lower data transfer processing unit 501B.
A registers the ID of the command descriptor in A (120
5).

Further, a request related to the timer is requested to the back-end processor 509 (1206).

FIG. 13 shows a data transfer processing unit 501.
The outline of the reception process of A is shown. Receive input FIFO 505A
From the command descriptor (130)
1).

Next, the type of the packet is determined by looking at the reception buffer chained to the command descriptor (1302). If it is an AK packet, AK reception processing is performed using the command descriptor and the reception buffer (1303). If a data (DT) packet is received, DT reception processing is performed using the command descriptor and the reception buffer (1304), and the reception output FIFO 50 is sent to the host computer interface unit 204.
Register the command descriptor ID in 3A (13
05). In order to return the AK, the transmission output FIFO 506A is sent to the lower-order data transfer processing unit 501B.
Is registered in the command descriptor (130).
6). Since the data transfer processing unit 501A does not process any data other than the AK packet and the DT packet, the data transfer processing unit 501A requests the backend processor 509 to perform the processing (1307).

After processing the AK packet and the DT packet,
It requests the backend processor 509 to perform processing such as timer operation and queue operation (1307).

FIG. 14 shows a data transfer processing unit 501.
B shows an outline of the transmission process. Transmission input FIFO 504B
From the command descriptor (140
1), a header of the transmission buffer chained to the command descriptor is created (1402), and necessary information is set in the command descriptor (1403).
The ID of the command descriptor is registered in the transmission output FIFO 506B toward the AC processor 413 (140
4).

FIG. 15 shows a data transfer processing unit 501.
The outline of the reception process of B is shown. Receive input FIFO 505B
From the command descriptor (150
1).

By checking the reception buffer chained to the command descriptor, it is determined whether the packet is data reception (1502). In the case of data reception, data reception processing is performed by the command descriptor and the reception buffer (1503), and the ID of the command descriptor is registered in the reception output FIFO 503B toward the upper data transfer processing unit 501A (1504). In the case other than data reception, a request is made to the backend processor 509 for processing (1505).

FIG. 16 shows a backend processor 509.
Shows the outline of the processing when a request is received from the data transfer processing unit 501A. The ID of the command descriptor is extracted from the BEP input FIFO 508A (160
1).

Then, it is determined whether the request is a request for normal data transfer processing (1602).

If the request is not for normal data transfer processing,
It is determined whether the request is a buffer release request (1603). If the request is a release request, the process is performed (1604). If the request is not a release request, a transport error process is executed (160).
5).

If the request is for the data transfer normal processing, it is determined whether or not the transmission is a DT transmission (1606). For DT transmission,
The DT is registered in the response waiting queue (1607), and timer processing by DT transmission is performed (1608).

If it is not DT transmission, it is determined whether or not AK is received (1609). If AK is received, the DT registered in the response waiting queue is released (1610), and AK is received.
The timer processing by reception is performed (1611). If it is not AK reception, it is DT reception, so that processing is performed (16)
12).

FIG. 17 shows a backend processor 509.
Shows an outline of processing when a request is received from the data transfer processing unit 501B. The command descriptor ID is extracted from the BEP input FIFO 508B (170).
1), command field F of the command descriptor
1 to determine whether it is a buffer release request (170
2). If it is a buffer release request, the process is executed (1703). If it is not a buffer release request, abnormal processing of layers L2 and L3 is performed (1704).

FIG. 18 shows an outline of the transmission activation process of the MAC processor 413. The command descriptor ID is extracted from the transmission output FIFO 506B (180
1), a descriptor in the transmission buffer chained from the command descriptor is created (1802).

Next, it is determined whether or not the transmission output FIFO 506B is empty (1803). If it is not empty, a transmission buffer is built in the chain (1804), and the process returns to step 1801. If empty, the communication controller 41
5 (1805), issues a transmission request (1806), and sets the first command descriptor address in a transmission completion wait pointer (1807).

FIG. 19 shows an outline of the transmission completion processing of the MAC processor 413. When the transmission by the communication controller 415 is completed, an interrupt occurs, and the transmission completion processing flag is turned on in the interrupt routine (1901).

In the transmission completion processing, a transmission completion parameter is set in the command descriptor waiting for transmission completion (1902), the command descriptor is registered in the reception input FIFO 505B (1903), and the transmission completion processing flag is turned off. (1904).

FIG. 20 shows an outline of the reception process of the MAC processor 413. When the communication controller 415 receives the data, an interrupt occurs and the reception processing flag is turned on in the interrupt routine (2001).

In the receiving process, it is determined whether or not there is received data (2002). If there is no received data, the reception processing flag is turned off and the processing is terminated (200
8). If there is received data, it is determined whether a reception error has occurred (2003). If a reception error has occurred, the process proceeds to step 2007 below. If no reception error has occurred, an empty command descriptor is obtained from the command descriptor pool (2004), necessary information is set in the command descriptor and chained with the buffer (2005), and the ID of the command descriptor is input to the reception input FIFO 505B.
(2006).

After processing one piece of received data, the receiving buffer address is updated for the next received data (20).
07).

According to the first embodiment, the processing load in the communication control device 102 can be distributed to the upper interface processor 401, the protocol processing device 410, and the MAC processor 413. Further, the bus load in the communication control device 102 is determined by using the inter-processor information transmitting means 209-1 and 209-2 between the processors and the protocol processing unit buses 210-1, 210-2, 210-3 and 2
10-4 and the data buses 208-1 and 208-2. Therefore, high-performance communication performance can be obtained.

(Second Embodiment) In the first embodiment, the protocol processing device 410 includes data transfer processing units 501A and 501B, which are hardware dedicated to protocol processing, and a back-end processor 509.
However, in the second embodiment, it is configured using a microprocessor.

FIG. 21 is a block diagram of a protocol processing device 410 constituted by using a microprocessor.
That is, the protocol processing device 410 includes a high-speed microprocessor 2101 for executing protocol processing, a local memory 2102 for storing a program, a timer circuit 2103, FIFOs 2104 and 2105 for transmitting information to and from the upper interface processor 401;
It comprises FIFOs 2106 and 2107 for information transmission with the C processor 413.

The protocol processing device 410 shown in FIG.
Preferably, this is made into one chip using SIC technology.

(Embodiment 3) In the first and second embodiments, the processors are arranged in the host computer interface unit 204, the protocol processing unit 205, and the line control unit 206, respectively. The processor is arranged only in the communication control device 102.

FIG. 22 shows the separation of the data bus 2206 and the protocol processing unit bus 2301 when a processor is arranged only in the communication control unit 102.

Computer 101 and buffer memory unit 2203
Are the data input / output paths between the DMAC 2205 and the data bus 2206. A data input / output path between the network 103 and the buffer memory unit 2203 is a communication controller 2204 and a data bus 2206.

On the other hand, a path for protocol processing between the protocol processing unit 2201 and the buffer memory unit 2203 is a protocol processing unit bus 2301.

According to the configuration of the third embodiment, high contention communication performance can be obtained because no bus acquisition conflict occurs between data input / output and protocol processing.

In the third embodiment, when it is impossible to arrange a plurality of processors in the communication control device due to hardware, or when the processing speed of the processor is sufficiently high,
This is effective when the processor can sufficiently cope with the network transmission speed.

[0102]

According to the communication control apparatus of the present invention, there is no competition between the acquisition of a bus for data input / output processing and the acquisition of a bus for communication protocol processing, so that these processings can be further advanced in parallel. .

Further, since the communication protocol processing is shared by a plurality of processors, the processing parallelism is further enhanced.

Further, since the protocol processing unit bus is not used for communication between the processors, the parallelism of the processing is further enhanced in this respect.

As described above, it is possible to provide a communication control device which executes the communication protocol processing at high speed and has a high throughput corresponding to the network transmission speed.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a communication control device according to the present invention.

FIG. 2 is a configuration diagram showing an example of an information communication network system.

FIG. 3 is a conceptual diagram of a hierarchical protocol in an information communication network.

FIG. 4 is a detailed block diagram of a communication control device according to the present invention.

FIG. 5 is an internal block diagram of the protocol processing device shown in FIG. 4;

FIG. 6 is a block diagram in which a buffer memory access control unit of FIG. 4 is developed.

FIG. 7 is a conceptual diagram of a command descriptor and a buffer.

FIG. 8 is a time chart showing an operation relation of each processor at the time of data transmission.

FIG. 9 is a time chart showing an operation relation of each processor at the time of data reception.

FIG. 10 is a transmission processing flowchart of an upper interface processor.

FIG. 11 is a reception processing flowchart of an upper interface processor.

FIG. 12 is a transmission processing flowchart of a data transfer processing unit 501A.

FIG. 13 is a reception processing flowchart of the data transfer processing unit 501A.

FIG. 14 is a transmission processing flowchart of the data transfer processing unit 501B.

FIG. 15 is a reception processing flowchart of the data transfer processing unit 501B.

FIG. 16 is a layer L4 processing flowchart of a back-end processor.

FIG. 17 shows layers L2 and L3 of the back-end processor.
Processing flowchart.

FIG. 18 is a flowchart of transmission start processing of the MAC processor.

FIG. 19 is a transmission completion processing flowchart of a MAC processor.

FIG. 20 is a reception processing flowchart of a MAC processor.

FIG. 21 is a block diagram of a protocol processing device according to a second embodiment of the present invention.

FIG. 22 is a block diagram of a communication control device according to a third embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 101 computer 102 communication control device 103 network 204 host computer interface unit 207 buffer memory unit 205 protocol processing unit 206 line control unit 208-1, 208-2 data bus 209-1, 209-2 inter-processor information transmission means 210-1 210-4 Protocol processing unit bus 401 Upper interface processor 406 Command memory 410 Protocol processing device 413 MAC processor 416 Buffer memory 420 Upper interface unit bus 501A, 501B Data transfer processing unit 502A, 502B Protocol processing circuit 503A, 503B Receive output FIFO 504A, 504B Transmission input FIFO 506A Reception input FIFO 506B Transmission output FIFO 507A, 507B BEP output FIFO 508A, 508B BEP input FIFO 509 back-end processor 601 bus selection circuit 602 the buffer memory port control circuit 701 Command Descriptor 702 buffer

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Mika Mizutani 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside the Hitachi, Ltd.System Development Laboratory (72) Inventor Matsuaki Terada 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Shares (56) References JP-A-3-34661 (JP, A) JP-A-1-260555 (JP, A) JP-A-1-131945 (JP, A) JP-A-61 −232747 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 13/00 H04L 29/00-29/12 G06F 13/20-13/378

Claims (5)

(57) [Claims] 1. A located between the computer communication network, a host computer interface unit for controlling the interface with the computer, a line control unit for transmitting and receiving data via a communication line, a buffer memory for storing the received data Department and
Protocol for data stored in the buffer memory
In a communication control device including a protocol processing unit for executing a protocol process, a protocol processing unit bus connecting the protocol processing unit and the buffer memory unit separately from a data bus connecting the host computer interface unit and the line control unit to the buffer memory unit. the provided host computer interface unit to the bus Ffamemori part Wakashi
Ku is a communication control apparatus characterized by the access line control unit, and access protocol processing portion of the buffer memory is to not cause bus acquisition contention. Wherein located between the computer communication network, a host computer interface unit for controlling the interface with the computer, a line control unit for transmitting and receiving data via a communication line, a buffer memory for storing the received data Department and
Protocol for data stored in the buffer memory
In the communication control device including a protocol processing unit for executing le process, host computer interface unit, the line control unit, arranged processor dedicated processing units for executing communication protocol processing to each of the protocol processing section, the upper level computer interface unit and is provided separately from the protocol processing unit bus connecting said respective processor and the buffer memory unit and a data bus connecting the line control unit and the buffer memory unit, the data of the host computer interface unit and the line control unit to the bus Ffamemori unit communication control apparatus characterized by an access for input and output, and access for communication protocol processing of each processor to the buffer memory unit is to not cause bus acquisition contention. 3. A transmission and reception FIFO is provided between a processor of a host computer interface unit and a processor of a protocol processing unit and between a processor of a protocol processing unit and a processor of a line control unit.
3. The communication control device according to claim 2, wherein interface information is exchanged between processors via the interface. 4. A command memory is provided separately from a buffer memory for storing transmission / reception data, and a command descriptor for instructing an operation of each processor is defined at a location on the command memory indicated by the interface information. The communication control device according to claim 2 or 3. 5. A data bus on a buffer memory side via a bus selection circuit, wherein a data bus on a host computer interface section side and a data bus on a line control section side are connected to each other. The bus selection circuit connects the bus to the buffer memory via a buffer memory port control circuit. The buffer memory port control circuit performs arbitration of an access request for input / output, and an access request for inputting / outputting data to / from the buffer memory via a data bus on the buffer memory side and a protocol processing unit bus. Arbitration of access requests for communication protocol processing to all buffer memories The communication control device according to claim 2, wherein the communication control is performed.