JPH0423821B2 - - Google Patents
Info
- Publication number
- JPH0423821B2 JPH0423821B2 JP57075223A JP7522382A JPH0423821B2 JP H0423821 B2 JPH0423821 B2 JP H0423821B2 JP 57075223 A JP57075223 A JP 57075223A JP 7522382 A JP7522382 A JP 7522382A JP H0423821 B2 JPH0423821 B2 JP H0423821B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- alloy
- wafer
- semiconductor device
- compound semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- 239000004065 semiconductor Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 21
- 150000001875 compounds Chemical class 0.000 claims description 16
- 229910045601 alloy Inorganic materials 0.000 claims description 12
- 239000000956 alloy Substances 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 6
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 229910015363 Au—Sn Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910015365 Au—Si Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims 2
- 229910052751 metal Inorganic materials 0.000 description 23
- 239000002184 metal Substances 0.000 description 23
- 235000012431 wafers Nutrition 0.000 description 21
- 238000010438 heat treatment Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 238000007740 vapor deposition Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229910017401 Au—Ge Inorganic materials 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000005019 vapor deposition process Methods 0.000 description 3
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Lasers (AREA)
Description
【発明の詳細な説明】
本発明は−族化合物半導体に対するオーム
性電極を有する半導体装置の製造方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having an ohmic electrode for a - group compound semiconductor.
電極形成技術に要求される問題点の一つとして
ボンデイング性がある。通常このワイヤボンデイ
ングは熱圧着法により行なわれている。すなわち
純粋なAuとAuを用いて熱圧着すると非常に強固
な接合が得られている。従来より化合物半導体に
対するオーム性電極については、AuGe／Ni／
Au，Au−Ge−Ni／Au，Au−Sn／Au，Au−
Zn／Au等が使われていた。しかしこれらの二層
あるいは三層構造の電極は蒸着中あるいは電極形
成工程後のCVD法等を用いることによつて熱処
理工程を通ると半導体構成原子やオーム性接触形
成金属のAu層への拡散が抑制できなかつた。こ
のためAu表面の変成によりワイヤボンデイング
性を悪くするという欠点があつた。 One of the problems required for electrode formation technology is bondability. This wire bonding is usually performed by thermocompression bonding. In other words, when pure Au and Au are used for thermocompression bonding, an extremely strong bond is obtained. Conventionally, ohmic electrodes for compound semiconductors include AuGe/Ni/
Au, Au−Ge−Ni/Au, Au−Sn/Au, Au−
Zn/Au etc. were used. However, when these two-layer or three-layer electrodes undergo a heat treatment process during vapor deposition or after the electrode formation process, diffusion of semiconductor constituent atoms and ohmic contact forming metals into the Au layer is prevented. I couldn't control it. For this reason, there was a drawback that wire bonding properties were deteriorated due to modification of the Au surface.
このような欠点を避けるために、Au−Ge／
Ta／Auのような三層構造により解決する方法も
ある。（特開昭56−29365）この他Ta以外にＷ，
Ptを用いる方法もあるがそれぞれ密着性、エツ
チング性に問題がある。また上記高融点金属
（Ta，Ｗ，Pt等）はエレクトロンビーム蒸着法に
よらねばならず、半導体レーザ、発光ダイオード
のように50μm〜100μm厚のウエーハに蒸着する
時、次のような欠点を生じる。この問題点を第１
図を用いて説明する。この場合高融点金属蒸着源
１４の上方のウエーハホルダー１１にウエーハ１
２を固定しなければならない。ウエーハは薄くか
つ−族化合物半導体の強度は弱く固定のため
ウエーハにネジ１３などで力を加えて抑えると割
れたりして取扱い上の困難が生じる。なお、第１
図において１３はエレクトロンビーム、１５はビ
ームを発生するＷフイラメント、１６は水冷るつ
ぼである。 In order to avoid such drawbacks, Au-Ge/
Another solution is to use a three-layer structure such as Ta/Au. (Unexamined Japanese Patent Publication No. 56-29365) In addition to Ta, W,
There is also a method using Pt, but each method has problems with adhesion and etching properties. In addition, the above-mentioned high melting point metals (Ta, W, Pt, etc.) must be deposited by electron beam evaporation, and when deposited on 50 μm to 100 μm thick wafers such as semiconductor lasers and light emitting diodes, the following drawbacks occur: . This problem is the first
This will be explained using figures. In this case, the wafer 1 is placed on the wafer holder 11 above the high melting point metal vapor deposition source 14.
2 must be fixed. The wafer is thin and the strength of the - group compound semiconductor is weak and fixed, so if the wafer is held down by applying force with the screws 13 or the like, it will break, making handling difficult. In addition, the first
In the figure, 13 is an electron beam, 15 is a W filament that generates the beam, and 16 is a water-cooled crucible.
本発明の目的は化合物半導体の構成原子やオー
ム性接触形成金属が電極であるAu層へ拡散する
のを抑制した高信頼性のオーム性電極を提供する
ことである。しかもワイヤボンデイング強度が強
く、且当該電極形成のための蒸着工程で薄い化合
物半導体のウエーハを破損する恐れのない簡便な
方法で製作可能である。この製造上の利点は量産
品を対象とする本発明の半導体装置用のオーム性
電極の大きい利点である。 An object of the present invention is to provide a highly reliable ohmic electrode in which diffusion of constituent atoms of a compound semiconductor and metal forming an ohmic contact into an Au layer serving as an electrode is suppressed. In addition, it has strong wire bonding strength and can be manufactured by a simple method that does not cause damage to the thin compound semiconductor wafer during the vapor deposition process for forming the electrode. This manufacturing advantage is a major advantage of the ohmic electrode for semiconductor devices of the present invention intended for mass-produced products.
上記の目的を達成するために下記の構成を取
る。その骨子は、
(1) −族化合物半導体基体に対し、該基体と
の間にオーム性接触を構成し且Auを主体とす
る第１の金属層を設けること、
(2) 第１の金属層上にPdからなる第２の金属層
を設けることである。 In order to achieve the above purpose, the following configuration is adopted. The main points are: (1) providing a first metal layer mainly composed of Au and forming ohmic contact with the − group compound semiconductor substrate; (2) providing the first metal layer; A second metal layer made of Pd is provided thereon.
通常、半導体装置と他の部材との接続に有利に
せしむるためAu等よりなる第３の金属層が設け
られる。但し、Pd層をその目的のため十分に厚
くすれば必ずしも必要ではない。しかし、Pd層
の形成を通常の蒸着法に依る場合、余り厚いPd
層は形成しにくいのでこの方法は有利ではない。 Usually, a third metal layer made of Au or the like is provided for advantageous connection between the semiconductor device and other members. However, this is not necessarily necessary if the Pd layer is made thick enough for that purpose. However, when the Pd layer is formed using a normal vapor deposition method, the Pd layer is too thick.
This method is not advantageous since the layers are difficult to form.
本発明はPdより成る第２の金属層によつて化
合物半導体基体の構成原子（たとえばGaAsの場
合はGa）或いはオーム性接触形成金属（たとえ
ばZn）等が当該電極層に拡散することを抑制す
ることができ、十分に高信頼性を確保することが
できる。 The present invention suppresses the diffusion of constituent atoms of the compound semiconductor substrate (for example, Ga in the case of GaAs) or ohmic contact forming metals (for example, Zn) into the electrode layer by the second metal layer made of Pd. It is possible to ensure sufficiently high reliability.
本発明は化合物半導体基体表面に高濃度の不純
物層が形成されていない基体に適用して極めて有
用である。 The present invention is extremely useful when applied to a compound semiconductor substrate on which a highly concentrated impurity layer is not formed.
前記第１の金属層としては通常、−族化合
物半導体の導電性と一致する不純物元素を少なく
とも含有し且Auを主成分とする合金が用いられ
る。Ｐ導電形に対してはAu−Zn，Au−Be、Ｎ
導電形に対してはAu−Si，Au−Ge，Au−Ge−
Ni，Au−Sn等が代表的な例である。 As the first metal layer, an alloy containing at least an impurity element whose conductivity matches that of the - group compound semiconductor and whose main component is Au is usually used. For P conductivity type, Au-Zn, Au-Be, N
For conductive types, Au−Si, Au−Ge, Au−Ge−
Typical examples are Ni, Au-Sn, etc.
これら合金の不純物元素の含有量は、この合金
を溶融した場合、化合物半導体基体内に高濃度に
不純物をドープ可能な程度を目安とされる。 The content of impurity elements in these alloys is determined to be such that when the alloy is melted, the impurity can be doped at a high concentration into the compound semiconductor substrate.
例えばAu−Znの場合、Znは10〜20wt−％、
Au−Geの場合、Geは４〜12wt−％程度である。 For example, in the case of Au-Zn, Zn is 10 to 20 wt-%,
In the case of Au-Ge, Ge is about 4 to 12 wt-%.
第１の金属層は通常200nm〜300nmが採用され
る。膜厚の下限は溶融の後、少なくとも連続的な
膜が形成出来る程度となす。上限は蒸着の容易さ
等他の要因で決定して良い。 The first metal layer usually has a thickness of 200 nm to 300 nm. The lower limit of the film thickness is such that at least a continuous film can be formed after melting. The upper limit may be determined based on other factors such as ease of vapor deposition.
第２の金属層は50nm〜650nmが採用される。
前述したように第２の金属層（Pd層）は厚くて
も良く、この場合、第３の金属層を省略し得る。
しかし、Pdを650nm以上に厚く蒸着することは
不可能ではないが困難が伴う。 The second metal layer has a thickness of 50 nm to 650 nm.
As described above, the second metal layer (Pd layer) may be thick, and in this case, the third metal layer may be omitted.
However, although it is not impossible to deposit Pd thicker than 650 nm, it is difficult.
第３の金属層は通常Auを用い300nm以上とな
している。 The third metal layer is usually made of Au and has a thickness of 300 nm or more.
本発明は通常の抵抗線加熱法を利用することが
できる。第２図を用いてこの方法を説明する。蒸
着金属２２をフイラメント２１につるす。これを
ウエーハ２４の上方に配置すれば、ウエーハの固
定は必要なく、加熱用カーボン板２３の上に置く
だけで良い。 The present invention can utilize a conventional resistance wire heating method. This method will be explained using FIG. Vapor-deposited metal 22 is suspended from filament 21. If this is placed above the wafer 24, there is no need to fix the wafer, and it is sufficient to simply place it on the heating carbon plate 23.
Pdは(1)高融点金属であり拡散のバリアとして
機能する。(2)蒸着工程でウエーハの固定の必要の
ない抵抗線加熱法を用いることができる。本発明
の電極は特に−族化合物半導体素子の製造
上、蒸着工程で50〜100μmの厚みを扱う必要のあ
る場合特に有効である。 Pd (1) is a high melting point metal and functions as a diffusion barrier. (2) A resistance wire heating method that does not require fixing the wafer can be used in the vapor deposition process. The electrode of the present invention is particularly effective when it is necessary to handle a thickness of 50 to 100 μm in the vapor deposition process in the production of − group compound semiconductor devices.
以下、本発明を実施例によつて詳細に説明す
る。 Hereinafter, the present invention will be explained in detail with reference to Examples.
最初にオーム性電極の形成条件について説明し
次いでGaAs−GaAlAsレ−ザの製作工程の実際
について述べる。 First, the conditions for forming the ohmic electrode will be explained, and then the actual manufacturing process of the GaAs-GaAlAs laser will be described.
まずＮ型GaAsにAu−Ge−Ni合金（例えばAu
−12wt％ Ge−4wt％Ni）を抵抗線加熱法で
200nm〜300nm蒸着する。この蒸着中にウエーハ
は360℃〜380℃に加熱して蒸着アロイをする。次
にウエーハ温度を150℃〜250℃に下げてPd，Au
を連続蒸着する。Pdの厚みは50nm以上あれば充
分バリアとなつておりAuの表面へGe，Ga等の拡
散を抑えることができる。またその後熱処理工程
を必要とする場合はさらにその際の温度、時間に
合わせてPdを厚くしておけば良い。Auの厚みは
300nm以上であればワイヤボンデイングに支障は
ない。 First, N-type GaAs is coated with an Au-Ge-Ni alloy (for example, Au).
−12wt% Ge−4wt%Ni) by resistance wire heating method.
Deposit 200nm to 300nm. During this vapor deposition, the wafer is heated to 360°C to 380°C to deposit the alloy. Next, the wafer temperature was lowered to 150°C to 250°C and Pd, Au
Continuously evaporate. If the thickness of Pd is 50 nm or more, it acts as a sufficient barrier and can suppress the diffusion of Ge, Ga, etc. to the surface of Au. Furthermore, if a subsequent heat treatment step is required, the thickness of Pd may be further increased according to the temperature and time at that time. The thickness of Au is
If it is 300nm or more, there is no problem with wire bonding.
Ｎ型InPについても同様の工程が可能であるこ
とは本発明の精神から言つても明らかである。 It is clear from the spirit of the present invention that a similar process is possible for N-type InP.
次に実際の半導体レーザの作製時のウエーハ工
程について第３図１〜３を用いて述べる。第４図
は半導体レーザの斜視図である。 Next, the wafer process during the actual fabrication of a semiconductor laser will be described using FIGS. 1 to 3. FIG. 4 is a perspective view of the semiconductor laser.
(1) ｎ−GaAs（100）結晶にエピタキシヤル成長
法でGaAlAsを表面にし、レーザとしての機能
を持たせるために必要な結晶構造となるように
加工を終えたウエーハ３１にＰオーム性電極３
２を形成する。このときのウエーハ厚みは
450μmである。電極にはCr／Au二層膜を約１
〜1.3μm厚み被着する。ホトエツチング工程で
電極のエツチングを行ない、スクライブしろを
形成する（第３図１）。(1) A P-ohmic electrode 3 is attached to the wafer 31 which has been processed to have the crystal structure necessary to provide laser functionality by epitaxially growing GaAlAs on the n-GaAs (100) crystal surface.
form 2. The wafer thickness at this time is
It is 450μm. Approximately 1 Cr/Au double layer film is used for the electrode.
Deposit ~1.3μm thick. The electrode is etched in a photo-etching process to form a scribe margin (FIG. 3, 1).
(2) 続いてウエーハの裏面を研磨および歪とりエ
ツチングする。エツチング液はH2SO4−H2O2
−H2Ｏ系を用いる。ウエーハ厚みを最終的に
100〜120μmにする（第３図２）。これはレーザ
チツプのへき開が容易におこなえる厚さであ
る。同時に局部的に大きな圧力がかかるような
取扱いを行なうとウエーハを破損する厚みでも
ある。(2) Next, the back side of the wafer is polished and etched to remove distortion. Etching solution is H 2 SO 4 −H 2 O 2
-H2O system is used. Final wafer thickness
100 to 120 μm (Figure 3, 2). This is a thickness that allows the laser chip to be easily cleaved. At the same time, it is also thick enough to damage the wafer if it is handled in a way that places a large pressure locally on it.
(3) ウエーハに先に説明したAu−Ge−Ni／
Pd／Au三層膜を抵抗線加熱法によつて連続蒸
着する。蒸着中の真空度は３×10-6Torrであ
る。まずウエーハ温度を360℃に設定し、４分
間でAu−Ge−Ni３３を300nm蒸着する。この
間ｎ−GaAsとAu−Ge−Ni合金（たとえば、
Au84wt％、Ge12wt％、Ni4wt％）は蒸着中に
アロイ反応をおこし、良好なオーミツク接触を
形成する。次にウエーハ温度を200℃下げて、
Pd膜３４を200nm、Au３５を800nm連続蒸着
し、全電極膜厚を1.3μmにする（第３図３）。(3) Au−Ge−Ni/
A three-layer Pd/Au film is continuously deposited by resistance wire heating. The degree of vacuum during deposition was 3×10 -6 Torr. First, the wafer temperature was set to 360°C, and Au-Ge-Ni 33 was evaporated to a thickness of 300 nm in 4 minutes. During this period, n-GaAs and Au-Ge-Ni alloys (for example,
Au84wt%, Ge12wt%, Ni4wt%) cause an alloying reaction during vapor deposition and form good ohmic contact. Next, lower the wafer temperature by 200℃,
A Pd film 34 of 200 nm and Au 35 of 800 nm are continuously deposited to make the total electrode film thickness 1.3 μm (FIG. 3).
(4) ウエーハ工程の終つたチツプは400μm×
300μm×100μmtの寸法にへき開とスクライブ
により分割する（第４図）。最後にパツシベー
シヨン膜としてスパツタSiO2膜をチツプのへ
き開面へ被着して端面を保護する。このときス
パツタ時にチツプの温度は上昇するがＮオーム
性電極のボンダビリテイーは劣化しない。(4) Chips after wafer process are 400μm×
Divide into pieces of 300 μm x 100 μm by cleaving and scribing (Figure 4). Finally, a sputtered SiO 2 film is applied as a passivation film to the cleavage surface of the chip to protect the end face. At this time, the temperature of the chip increases during sputtering, but the bondability of the N-ohmic electrode does not deteriorate.
今の例は基板がGaAsの場合であるが、InP−
InGaAsP系などの半導体レーザの場合でもInP基
板に対して同様である。 In the current example, the substrate is GaAs, but InP−
The same applies to InP substrates for semiconductor lasers such as InGaAsP.
またオーム性接触形成金属層がAu−Ge，Au
−Sn合金等であつても同じである。 In addition, the ohmic contact forming metal layer is Au-Ge, Au
-The same applies to Sn alloys, etc.
さらに基板としてＰ型基板を用いるレーザの場
合はオーム性接触形成金属層がたとえばAu−Zn
合金によつて形成される点が異なるだけである。 Furthermore, in the case of a laser using a P-type substrate as the substrate, the ohmic contact forming metal layer may be, for example, Au-Zn.
The only difference is that it is formed by an alloy.
さらにPdはAuのエツチング液であるNH4Ｉ−
I2系のエツチング液でエツチング可能であり、電
極のパターンニングが必要な場合も問題ない。 Furthermore, Pd is an etching solution for Au, NH 4 I-
Etching is possible with an I2 - based etching solution, so there is no problem even if electrode patterning is required.
第１図はエレクトロンビーム蒸着法を説明する
模式図、第２図は抵抗線加熱蒸着法を説明する模
式図、第３図はレーザ装置の電極形成工程を示す
装置の断面図である、第４図はレーザ装置の斜視
図である。
３１……ウエーハ、３３……オーム性接触形成
の第１の金属層（Au−Ge−Ni等）、３４……Pd
よりなる第２の金属層、３５……第３の金属部
（例えばAu）。
FIG. 1 is a schematic diagram explaining the electron beam evaporation method, FIG. 2 is a schematic diagram explaining the resistance wire heating evaporation method, FIG. 3 is a cross-sectional view of the device showing the electrode forming process of the laser device, and FIG. The figure is a perspective view of the laser device. 31... Wafer, 33... First metal layer for forming ohmic contact (Au-Ge-Ni etc.), 34... Pd
a second metal layer consisting of 35 . . . a third metal portion (for example, Au);
Claims (1)
金とがアロイする温度で、該−族化合物半導
体からなる基板上に該合金を被着して該半導体と
該合金とからなるアロイ膜を形成する工程と、該
基板の温度を下げて該アロイ膜上にパラジウム膜
及び金膜を順次形成する工程とを有することを特
徴とする半導体装置の製造方法。 ２ 上記−族化合物半導体は、GaAs又は
InPであることを特徴とする特許請求の範囲第１
項記載の半導体装置の製造方法。 ３ 上記−族化合物半導体はｐ導電形であ
り、上記金を主成分とする合金はAu−Zn又はAu
−Beであることを特徴とする特許請求の範囲第
１項又は第２項記載の半導体装置の製造方法。 ４ 上記−族化合物半導体はｎ導電形であ
り、上記金を主成分とする合金はAu−Si，Au−
Ge，Au−Ge−Ni又はAu−Snであることを特徴
とする特許請求の範囲第１項又は第２項記載の半
導体装置の製造方法。 ５ 上記半導体装置は半導体レーザであることを
特徴とする特許請求の範囲第１項乃至第４項の何
れかに記載の半導体装置の製造方法。[Claims] 1. The semiconductor and the alloy are formed by depositing the alloy on a substrate made of the - group compound semiconductor at a temperature at which the - group compound semiconductor and the alloy containing gold as a main component are alloyed. 1. A method for manufacturing a semiconductor device, comprising: forming an alloy film; and lowering the temperature of the substrate to sequentially form a palladium film and a gold film on the alloy film. 2 The - group compound semiconductor mentioned above is GaAs or
Claim 1 characterized in that it is InP.
A method for manufacturing a semiconductor device according to section 1. 3 The above-mentioned − group compound semiconductor is of p-conductivity type, and the above-mentioned gold-based alloy is Au-Zn or Au.
-Be, the method for manufacturing a semiconductor device according to claim 1 or 2, wherein: -Be. 4 The above-mentioned - group compound semiconductor is of n conductivity type, and the above-mentioned gold-based alloy is Au-Si, Au-
3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the semiconductor device is Ge, Au-Ge-Ni or Au-Sn. 5. The method of manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is a semiconductor laser.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7522382A JPS58192370A (en) | 1982-05-07 | 1982-05-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7522382A JPS58192370A (en) | 1982-05-07 | 1982-05-07 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58192370A JPS58192370A (en) | 1983-11-09 |
| JPH0423821B2 true JPH0423821B2 (en) | 1992-04-23 |
Family
ID=13570008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7522382A Granted JPS58192370A (en) | 1982-05-07 | 1982-05-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58192370A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0460531A1 (en) * | 1990-06-07 | 1991-12-11 | Siemens Aktiengesellschaft | Contact metallisation on semiconductor material |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5092083A (en) * | 1973-12-12 | 1975-07-23 |
-
1982
- 1982-05-07 JP JP7522382A patent/JPS58192370A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5092083A (en) * | 1973-12-12 | 1975-07-23 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58192370A (en) | 1983-11-09 |
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