JP3363343B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device such as a light emitting diode array using a compound semiconductor and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device using a compound semiconductor such as gallium arsenide (GaAs), an electrode made of a material corresponding to each conductivity type has been used. For example, in p-type gallium arsenide, an electrode made of gold chromium (AuCr) or the like is used, and in n-type gallium arsenide, gold germanium (AuCr) is used.
An electrode made of Ge) / nickel (Ni), gold (Au) / gold germanium, gold germanium indium (AuGeIn), or the like is used. This is because the ohmic contact can be obtained by reducing the contact resistance with each conductive type semiconductor substrate or semiconductor layer.

However, when forming electrodes having different structures depending on the conductivity type on the same surface of a semiconductor substrate, vapor deposition of an electrode material, application and patterning of a mask material, and etching of the electrode material must be performed twice. Therefore, there is a problem that the manufacturing process becomes extremely complicated.

Further, it is known that an electrode may be formed of germanium (Ge) in order to obtain ohmic contact with a compound semiconductor substrate or compound semiconductor layer of each conductivity type. When heat treatment is performed by adding germanium, germanium of the electrode material and gallium of the semiconductor material are deposited on the surface of the electrode to soften the electrode surface, and part of the germanium or gallium is oxidized to form the bonding wire material. However, there is a problem in that the wettability of the wire becomes poor and a bonding failure of the bonding wire occurs.

The present invention has been invented in view of the above problems of the prior art, and has the problem of the conventional device in which different electrodes must be formed in semiconductor regions or semiconductor layers having different conductivity types. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same in which the problem of the conventional device that the bonding failure of the bonding wire occurs is solved.

[0006]

In order to achieve the above object, according to a semiconductor device of the present invention, gallium arsenide,
In a semiconductor device having an electrode in which a plurality of metal materials are sequentially stacked on a semiconductor substrate or semiconductor layer made of indium gallium arsenide or indium aluminum gallium arsenide, the electrode is chromium, gold germanium,
The structure was such that chromium and gold were sequentially laminated.

According to the semiconductor device of the present invention,
It is desirable that the film thickness of the upper chromium layer is 100 to 500 Å.

Further, according to the semiconductor device of the present invention, the film thickness of the lower layer chromium is 100 to 600 Å and the film thickness of the gold germanium is 700 Å or more,
It is desirable that the film thickness of the gold is 8000 Å or more, and the film thickness of the entire electrode is 11500 Å or more.

[0009]

Further, according to the method of manufacturing a semiconductor device of the present invention, a plurality of metal materials are sequentially laminated and annealed on a semiconductor substrate or semiconductor layer made of gallium arsenide, indium gallium arsenide, or indium aluminum gallium arsenide. In the method for manufacturing a semiconductor device according to claim 3, after sequentially stacking chromium, gold germanium, chromium, and gold on the semiconductor substrate or the semiconductor layer, 300 to 3
Anneal at a temperature of 50 ° C.

[0011]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a diagram showing an embodiment of a semiconductor device according to the present invention, in which 1 is a semiconductor substrate or a semiconductor layer, 2 is an electrode as a whole, 3 is a layer made of chromium,
4 is a layer made of gold germanium, 5 is a layer made of chromium, and 6 is a layer made of gold.

The semiconductor substrate or the semiconductor layer 1 is made of gallium arsenide (GaAs) or indium gallium arsenide (InG).
aAs) or a compound semiconductor such as indium aluminum gallium arsenide (InAlGaAs).
The substrate on which the semiconductor layer is formed is not limited to the compound semiconductor, but may be a silicon substrate, a sapphire substrate, or the like.

The electrode 2 is composed of a lower chromium layer 3, a gold germanium layer 4, an upper chromium layer 5 and a gold layer 6. The lower chromium layer 3 is provided to improve the adhesion between the semiconductor substrate or the semiconductor layer 1 and the electrode 2. The lower chromium layer 3 preferably has a film thickness of 100 Å or more, in order to reduce the contact resistance between the semiconductor substrate or the semiconductor layer 1 and the electrode 2, particularly the contact resistance between the n-type semiconductor layer. Moreover, it is desirable that it is less than 600Å. If the thickness is less than 100Å, the chromium layer becomes island-shaped and it is difficult to form it on the entire surface of the region. The lower chromium layer 3 is usually formed to have a thickness of about 300Å.

The gold germanium layer 4 is provided to make ohmic contact with the semiconductor substrate or the semiconductor layer 1. The gold germanium layer 4 is preferably as thin as possible at 700 Å or more. This gold germanium layer 4 is
It functions as an ohmic contact layer, and it becomes difficult to make ohmic contact when the film thickness is 700 Å or less. On the other hand, gold germanium is a very expensive alloy, and it is desirable that it be as thin as possible. Usually 10
It is formed to a thickness of about 00Å. It is germanium that fulfills the function of forming an ohmic contact with the compound semiconductor substrate or the compound semiconductor layer 1 as described above, but in the case of only germanium, an alloy with gold is used because of its low hardness and high melting point. . In this case, Au: 88 wt
% -Ge: 12 wt% or the like can be preferably used.

The upper chromium layer 5 is provided to prevent germanium of the lower layer and gallium of the semiconductor material from depositing on the surface of the electrode 2, and is 100 to 500 Å.
It is desirable to form it to a thickness of. When the film thickness of the upper chromium layer 5 is 100 Å or less, the chromium layer becomes island-shaped and is difficult to form on the entire surface of the region, and the effect of preventing the precipitation of germanium or gallium is not sufficient. Further, when the film thickness of the upper chromium layer 5 is 500 Å or more, the contact resistance with the semiconductor substrate or the semiconductor layer 1, especially the contact resistance with the n semiconductor, increases. This upper chrome layer 5
Is usually formed to a thickness of about 300Å.

The gold layer 6 is provided to reduce the wiring resistance of the entire electrode 2 and to bond a bonding wire, and is preferably formed to a thickness of 8000 Å or more. When the thickness of the gold layer 6 is 8000 Å or less, the wiring resistance of the entire electrode 2 becomes large. For example, when the gold layer 6 is used as a cathode electrode of a light emitting diode array, the light emission intensity of each light emitting element varies due to a voltage drop due to the wiring resistance. Occurs. Even if the gold layer 6 is thick, it is sufficient if it is formed to a thickness of about 50,000 Å. Normally, it is formed to a thickness of about 8500Å.

The semiconductor substrate or the substrate on which the semiconductor layer 1 is formed is placed in a high vacuum chamber maintained at 1 × 10 ^-6 Torr or less, and chromium, gold germanium, and gold are used as evaporation sources to form a lower chromium layer. Layer 3, gold germanium layer 4,
The upper chromium layer 5 and the gold layer 6 are sequentially deposited. In this case, as the evaporation method of the evaporation source, a resistance heating method, an electron beam heating method, a laser beam heating method, a high frequency heating method,
Any method such as flash evaporation may be used.

Next, in order to improve the adhesion of the metal layers 3 to 6 and to obtain ohmic contact, 300
Anneal at a temperature of ~ 350 ° C. When the temperature is 300 ° C. or lower, the diffusion of germanium is insufficient and ohmic contact between the semiconductor substrate or the semiconductor layer 1 and the electrode 2 cannot be obtained. When the temperature is 350 ° C. or higher, gallium as a semiconductor material or germanium as an electrode material It deposits on the surface of the electrode 2, softens the electrode 2, and oxidizes gallium or germanium to deteriorate the wettability of the constituent material of the bonding wire, thus lowering the bondability.

Finally, patterning into a predetermined electrode shape is completed by a photolithography method or a lift-off method.

-Experimental Example 1- On a semiconductor substrate 1 made of gallium arsenide, silicon (S
i) an n-type semiconductor layer containing 2 × 10 ¹⁸ atoms / cm ⁻³ and a p-type semiconductor layer containing 1 × 10 ¹⁹ atom · cm of zinc (Zn) are formed, and the n-type semiconductor layer and the p-type semiconductor are formed. The lower chromium layer 3, the gold germanium layer 4, and the gold layer 6 were formed in the respective layers to have a thickness of 600Å, 8500Å, and 8500Å, and the thickness of the upper chromium layer 5 was variously changed to measure the contact resistance. The contact area is 200 μm ² . The result is shown in FIG. As is clear from FIG. 2, when the thickness of the upper chromium layer 5 is 480Å, the contact resistance is almost 9Ω (n side).
When the film thickness of the upper chromium layer 5 was 500 Å or more, it was 4.5Ω on the p-side and was almost flat, but it was 28Ω on the n-side and the upper chromium was 5. It was found that when the film thickness of the layer 5 exceeds 500 Å, the contact resistance rapidly increases. Therefore, it is desirable that the film thickness of the upper chromium layer 5 is 500 Å or less.

-Experimental Example 2-Under the same conditions as in Experimental Example 1, an n-type semiconductor layer and a p-type semiconductor layer are formed, and a lower chromium layer 3, a gold germanium layer 4, and an upper chromium layer 5 are 300 Å and 1000 respectively.
The thickness of the gold layer 6 was changed to various values, and the thickness of the gold layer 6 was changed so that the total thickness of the electrode 2 was the value shown in FIG. 3, and the wiring resistance of the electrode 2 was measured. The electrode 2 has a line width of 20 μm and a length of 5.4 mm. This line width and length are typical values for forming a 600 dpi light emitting diode. The result is shown in FIG.

As is apparent from FIG. 3, when the thickness of the electrode 2 is 8000 Å, the wiring resistance is 67Ω and 1000
It was found that the value was 58Ω in the case of 0Å and 50Ω in the case of 11500Å. Therefore, when a 600-dpi light emitting diode is formed, the electrode 2 has a total film thickness of 11500Å
It turns out that the above is desirable.

-Experimental Example 3- An n-type semiconductor layer and a p-type semiconductor layer are formed under the same conditions as in Experimental Example 1, and a lower chromium layer, a gold germanium layer 4, an upper chromium layer 5 and a gold layer 6 are formed. 200 for each
Å, 1000 Å, 100 Å, and 10000 Å film thickness, annealing temperature 400 ℃ × 20 minutes, 3
50 ° C x 20 minutes, 315 ° C x 20 minutes, 300 ° C x 20
Min, 285 ° C. × 20 minutes, bonding was performed with a bonding wire made of a pure gold fine wire having a wire diameter of 25 μm, and a bondability test in which a tensile load was applied to this wire was performed.

As a result, when the annealing temperature was 400 ° C. × 20 minutes, the wire peeled off immediately after wire bonding, and when 350 ° C. × 20 minutes, the wire was cut from the bond portion with a load of 7 g. Bonding property is almost good, 10 at 315 ℃ x 20 minutes
The wire bondability was good when the wire was cut from the bond portion under a load of g. Therefore, it was found that the annealing is preferably performed at a temperature of 350 ° C. or lower.

[0025]

As described above, according to the semiconductor device of the present invention, the electrodes are chromium, gold germanium, and chromium on the semiconductor substrate or semiconductor layer made of gallium arsenide, indium gallium arsenide, or indium aluminum gallium arsenide. And a structure in which gold is sequentially laminated, the electrode has good ohmic contact with both the p-type semiconductor layer and the n-type semiconductor layer, the bonding strength of the bonding wire is improved, and the wiring resistance is small. It becomes an electrode.

Further, according to the method of manufacturing a semiconductor device of the present invention, chromium, gold germanium, chromium, and gold are deposited on the semiconductor substrate or semiconductor layer made of gallium arsenide, indium gallium arsenide, or indium aluminum gallium arsenide. Layered sequentially, 300-350
Since it is annealed at a temperature of ℃, it becomes an electrode that can obtain a good ohmic contact with both the p-type semiconductor layer and the n-type semiconductor layer, and the bonding strength of the bonding wire is improved, and the electrode has a low wiring resistance.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a diagram showing a relationship between a film thickness of an upper chromium layer and a contact resistance in a semiconductor device according to the present invention.

FIG. 3 is a diagram showing a relationship between a film thickness of a gold layer and a wiring resistance in a semiconductor device according to the present invention.

[Explanation of symbols]

1 ...... semiconductor substrate or semiconductor layer, 2 ... lower chromium layer, 3 gold germanium layer, 4 upper chromium layer, 5 gold layer

Claims (4)

(57) [Claims] 1. A gallium arsenide, indium gallium arsenide
Element or indium aluminum gallium arsenide
A semiconductor substrate or a semiconductor layer made of a semiconductor device having a sequentially stacked electrodes a plurality of metal materials, chromium the electrode, gold germanium, chromium, and a semiconductor device which is characterized in that the stacked sequentially gold . 2. The thickness of the upper chromium layer is 100 to 50.
The semiconductor device according to claim 1, wherein the semiconductor device is 0Å. 3. The thickness of the lower chromium layer is 100 to 60.
The thickness of the gold germanium is 700 Å or more, the thickness of the gold is 8000 Å or more, and the film thickness of the entire electrode is 11500 Å or more. The semiconductor device according to. 4. Gallium arsenide, indium gallium arsenide
Element or indium aluminum gallium arsenide
A plurality of metal materials on the semiconductor substrate or semiconductor layer
In a method of manufacturing a semiconductor device in which the layers are sequentially laminated and annealed
On the semiconductor substrate or semiconductor layer, chromium, gold
After sequentially stacking germanium, chromium, and gold, 30
Semiconductor characterized by being annealed at a temperature of 0 to 350 ° C.
Device manufacturing method .