JPH04235432A - Packet transmitting/receiving device - Google Patents

Abstract

PURPOSE:To increase the utilization rate of a transmission link to improve throughput at the receiving side in the packet transmission between communication nodes linked via a plural transmission link. CONSTITUTION:In a communication node 10a at the transmission side, the packets stored in transmission standby buffers 4a to 4d in prescribed transmission order are loaded on empty packets coming in via any of transmission links 1(a) to 1(d) in order of the empty packet coming in earlier. In a communication node 10b at the receiving side, receiving packets are stored in receiving buffers 3a to 3d in prescribed receiving order from the packet coming in earlier when any of the transmission links 1(a) to 1(d) has brought the packet for the own node.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a network such as a LAN in which a plurality of communication nodes each accommodating a terminal are connected by a plurality of transmission links, from one communication node to another for communication between terminals. The present invention relates to a packet transmitting device and a receiving device when transmitting packets.

0002

[Prior Art] FIG. 7 shows a LAN to which the present invention is applied.
It is a conceptual diagram showing a network such as. In the figure, 10a to 10b are communication nodes, respectively, and 1a to 10b are communication nodes, respectively.
1d are transmission links, respectively. Each communication node has
Each one houses a terminal. For example, communication node 10
When a terminal housed in a communicates with a terminal housed in a communication node 10b, packets are sent and received via a transmission link between the communication nodes 10a and 10b. be.

Conventionally, in the transmission and reception of such packets, the transmission of successive packets from a certain terminal accommodated in a certain communication node to a specific terminal accommodated in another communication node requires that the receiving terminal In order to guarantee the order in which packets are received, a method has been adopted in which the packet transfer path is fixed. In other words, in the sending side communication node, the transmission waiting buffer that temporarily stores transmission packets from the terminal, the transmission link connecting the sending side communication node and the receiving side communication node, and the receiving side communication In the node, a method was adopted in which the same receive buffer was used to temporarily store received packets before passing them to the terminal.

Alternatively, after assigning a sequential number to each consecutive packet sent from the transmitting communication node,
forward to the receiving communication node via any transmission link,
A method has been adopted in which the receiving communication node or terminal uses the sequential number to rearrange the order of received packets.

[0005]

[Problems to be Solved by the Invention] In the conventional method as described above, in the case of a method in which the packet transfer path is fixed, unless an empty packet arrives on the transmission link connected to the buffer waiting for transmission, the packet is It is impossible to send
Even if there is a link with a low usage rate among other transmission links, it is not possible to change the transmission link to a link with a low usage rate midway, so in the end, if you look at the multiple transmission links as a whole, the effectiveness There was a problem that it could not be used.

[0006] In addition, in the case of a method in which a sequential number is assigned to each successive packet to be sent out, and the order of received packets is managed using the sequential number, each received packet is classified by its source and ordered by the sequential number. There is a problem in that it is necessary to perform control, etc., and the processing delay caused by performing these operations makes it impossible to improve throughput.

An object of the present invention is to overcome the problems in the prior art, to make effective use of a plurality of transmission links connecting communication nodes, and to minimize processing delays that impede improvement in throughput. An object of the present invention is to provide a packet transmitting device and a receiving device that can reduce the number of packets and still guarantee the order of consecutively received packets on the receiving side.

[0008]

[Means for Solving the Problems] In order to achieve the above object, in the present invention, communication nodes are connected by a plurality of transmission links, and communication from a certain first communication node via the plurality of transmission links is provided. to transmit packets to other communication nodes.
In a packet transmitting device that transmits a packet from the first communication node to the plurality of transmission links, the packet is sent to each of the plurality of prioritized transmission waiting buffers and the plurality of transmission waiting buffers in a round robin manner. means for storing packets to be transmitted; detecting means for monitoring the plurality of transmission links and detecting the arrival of empty packets;
Switching means for switching and connecting the plurality of transmission links and the plurality of transmission waiting buffers in a non-block manner (even if one transmission link and one buffer are connected, other switch means) capable of connecting between the transmission link and other buffers.

[0009] Furthermore, the communication nodes are connected by a plurality of transmission links, and packets are transmitted from other communication nodes to a certain first communication node via the plurality of transmission links. The packet receiving device includes a detecting means for monitoring the plurality of transmission links and detecting the arrival of a packet addressed to the first communication node, a plurality of prioritized receiving buffers, and a round robin. and switch means for switching and connecting the plurality of transmission links and the plurality of reception buffers so that incoming packets are received and stored in each reception buffer according to the method.

0010

[Operation] In the packet transmitter, multiple packets to be transmitted are ranked in the multiple transmission waiting buffers from 1st to nth (where n is an arbitrary integer). , the packet with the first transmission order is sent to each of the plurality of transmission waiting buffers according to its transmission order from the first to the mth order (where m is an arbitrary integer) according to the order of the buffer. goes to the first sending buffer, the second sending packet goes to the second sending buffer, and in the same way, after the nth buffer, it returns to the first buffer. (When m>n) Packets to be transmitted are stored in each buffer in a round robin manner. Then, when the detection means detects the arrival of an empty packet while monitoring the plurality of transmission links, no matter which link among the plurality of transmission links the empty packet arrives early in time, , the switching means switches and connects the plurality of transmission links and the plurality of transmission waiting buffers so that a unit number of packets are taken out and loaded from the plurality of transmission waiting buffers according to their order. .

[0011] In the packet receiving device, a plurality of receiving buffers are arranged in order from the first to the nth place (where n is an arbitrary integer), and the arrival of a packet addressed to the first communication node is Once detected by the detection means, the packets are processed in the order of arrival in the plurality of reception buffers in the order of arrival, regardless of which link among the plurality of transmission links the packets arrive at. The packet that arrives first is sent to the first receiving buffer, the second packet is sent to the second receiving buffer, and so on. The switching means switches between the plurality of transmission links and the plurality of reception buffers so that each buffer receives and stores incoming packets in a round-robin manner.

[0012] According to the above method, the plurality of transmission links connecting the transmitting side communication node and the receiving side communication node each have approximately the same length and the same transmission speed, so that the packets at the receiving side are The receiving order is guaranteed to be the same as the sending order on the transmitting side, and all the transmission waiting buffers on the transmitting side can access all of the plurality of transmission links, so it is possible to improve the usage rate of the transmission links.

[0013]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram conceptually showing an embodiment of the present invention. In the figure, 1a to 1d are transmission links, 10a is a transmitting side communication node, 10b is a receiving side communication node, 2a to 2d are reception processing circuits that receive packets addressed to their own nodes, and 3a to 3d are respectively A reception buffer (first-in, first-out type buffer, FIFO) for storing packets received by the reception processing circuit; 31 is a non-block switch (any of the reception processing circuits 2a to 2d and any of the reception buffers 3a to 3d); 32 is a receiving buffer selection circuit, and 6 is a terminal.

[0014] 5a to 5d are transmission processing circuits for transmitting a transmission packet by placing the transmission packet on an empty packet on the transmission link, and 4a to 4d are transmission waiting buffers (first-in, first-out type) for temporarily storing packets transmitted from the terminal 7, respectively. buffer, FIFO), and 41 is a non-block switch (which can connect any of the transmission processing circuits 5a to 5d and any of the transmission buffers 4a to 4d, and only connects one set at a time. switch)
, 42 is a transmission waiting buffer selection circuit, and 7 is a terminal.

Continuous packets transmitted from the terminal 7 are sent to the transmission waiting buffers 4a, 4b, 4c, and 4d in the order of arrival by the transmission waiting buffer selection circuit 42, and then back to the transmission waiting buffer 4a. They are sequentially stored according to the so-called round robin method.

In the packet transmission process, in the communication node 10a, when the detection means (not shown) monitors the plurality of transmission links 1a to 1d and detects the arrival of an empty packet, the plurality of transmission links 1a to 1d are detected. No matter which link in the link, the empty packet that arrived earlier in time is ranked among the multiple transmission waiting buffers 4a to 4d (in this case, round robin of 4a, 4b, 4c, and 4d). A control section (not shown) switches and controls the non-block switch 41 so that packets are taken out in unit numbers and sequentially placed in one of the transmission processing circuits 5a to 5d according to the order according to the method.

In the packet reception process, when the communication node 10b monitors the plurality of transmission links 1a to 1d by means of a detection means (not shown) and detects the arrival of a packet addressed to the own node, it is determined that the communication node 10b detects the arrival of a packet addressed to the node. Link 1a-1
No matter which link in d the packet arrives at, it is ranked among the plurality of reception buffers 3a to 3d in the order of the packet arriving earlier in time (in this case, 3a, 3b,
A control unit (not shown) controls the non-block switch 31 so that each packet is sequentially fetched into each reception buffer via one of the reception processing circuits 2a to 2d according to the round robin method shown in FIGS. 3c and 3d. Switch and control. Next, the reception buffer selection circuit 32 selects the plurality of reception buffers 3a to 3d in their order (in this case, 3a, 3b,
3c and 3d), the terminal 6 is connected to the terminal 6, and the received packet is delivered.

[0018] By doing the above, communication node 1 on the sending side
At 0a, the packets stored in the transmission waiting buffers 4a to 4d in a predetermined transmission order are transferred to any link among the transmission links 1a to 1d from which an empty packet has arrived. Since the transmission packets are loaded and transmitted in order from the earliest available free packet, the utilization rate of the transmission links 1a to 1d can be increased.

[0019] Furthermore, in the communication node 10b on the receiving side, if there is a link among the transmission links 1a to 1d from which a packet addressed to the node has arrived, the received packet is transmitted in order from the earliest arriving packet in terms of time. Since the received packets can be stored in the receiving buffers 3a to 3d in a predetermined receiving order, the receiving order of the packets is guaranteed.

FIG. 2 is a block diagram showing details of the communication node 10a in FIG. 1. In FIG. 2, 13 is a packet transmission control section. The transmission processing circuit 5a includes an empty packet detection section 51a that analyzes packet headers to detect empty packets, a delay circuit 52a, and a packet sending circuit 53a.
The same applies to b to 5d.

The non-block switch 41 is, for example, a matrix switch type, and if the intersection point AA is closed under the control of the packet transmission control section 13, the packet transmission circuit 53a and the transmission waiting buffer 4a in the transmission processing circuit 5a are connected to each other. If the intersection DD is connected and the intersection DD is closed, the packet sending circuit 53d in the sending processing circuit 5d and the sending waiting buffer 4d are connected. Connection is possible between the sending circuit and any sending buffer.

[0022] The packet sending control unit 3 stores empty packet information (FIFO empty information) indicating whether packets to be transmitted in that order are stored in the transmission waiting buffers 4a to 4d, and empty packet detecting units 51a to 51d. information about which transmission link the empty packet arrived at,
It determines which intersection in the non-blocking switch 41 should be closed and outputs the switch connection information to close the corresponding intersection, and also selects a transmission waiting buffer to output the transmission packet and instructs to send the packet.

FIG. 3 is a block diagram showing details of the packet transmission control section 3 in FIG. 2. As shown in FIG. In FIG. 3, 31
is a connection switch selection and sending instruction table, 32 is a round robin shift register, OR is an OR circuit, A1 to A
4 are AND circuits. The connection switch selection/sending instruction table 31 uses the free packet arrival information and the outputs of the AND circuits A1 to A4 as input addresses, and the ROM outputs the switch connection information AA to DD, and also the free packet arrival information and the AND circuits A1 to A4. RO that outputs a packet transmission start instruction using the output of A4 as an input address.
It also serves as M.

Connection switch selection and sending instruction table 31
Each time a packet transmission start instruction is output from the round robin shift register 32 via the OR circuit
A shift pulse is input to , and the AND circuits A1 to A4 are sequentially opened.

FIG. 4 shows R that outputs switch connection information AA to DD using empty packet arrival information and the outputs of AND circuits A1 to A4 (FIFO empty information) as input addresses.
This is a truth value table showing an instruction table 31 as an OM. If 5a is input as free packet arrival information and 4a is input as FIFO empty/busy information, AA is output as switch connection information, and 5d is input as free packet arrival information.
However, it will be understood that if 4d is input as the FIFO empty/busy information, DD is output as the switch connection information.

FIG. 5 is a truth value table showing an instruction table 31 as a ROM that outputs a packet sending instruction using the empty packet arrival information and the outputs of the AND circuits A1 to A4 (FIFO empty information) as input addresses. . If 5a is input as free packet arrival information and 4a is input as FIFO empty/busy information, a sending instruction to buffer 4a is output, and 5d is input as free packet arrival information.
If 4d is input as FO empty information, buffer 4d
It will be understood that the sending instructions for the data are output.

FIG. 6 is a conceptual diagram showing the round robin shift register 32 in FIG. 3. 4a, 4b, 4
It will be understood that the output is generated while shifting in the order of c, 4d, 4a, . The above is shown in Figure 1.
The details of the communication node 10a on the receiving side will be explained by analogy, so further explanation will be omitted.

[0028]

[Effects of the Invention] As explained above, according to the present invention,
All transmission waiting buffers can access all transmission links, so even if an empty packet occurs on any link on multiple transmission links, the packet can be placed on top of all the empty packets and transmitted. Link usage can be increased.

Furthermore, since the packets are transmitted onto the transmission link in the order in which they are input into the packet transmission waiting buffer, the transmission order of the packets is guaranteed. Similarly, the receiving buffer can receive packets while guaranteeing the order in which they arrive.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the concept of an embodiment of the present invention.

FIG. 2 is a block diagram showing details of the communication node 10a in FIG. 1.

FIG. 3 is a block diagram showing details of a packet transmission control section in FIG. 2;

FIG. 4 is an explanatory diagram showing one function of the instruction table in FIG. 3;

FIG. 5 is an explanatory diagram showing other functions of the instruction table in FIG. 3;

FIG. 6 is a conceptual diagram of the round robin shift register in FIG. 3;

FIG. 7 is a conceptual diagram showing a network such as a LAN to which the present invention is applied.

[Explanation of symbols]

1a to 1d...transmission link, 2a to 2d...reception processing circuit,
3a to 3d...Reception buffer, 4a to 4d...Transmission waiting buffer, 5a to 5d...Transmission processing circuit, 6, 7...Terminal, 31
, 41...Non-block switch, 32...Receiving buffer selection circuit, 42...Transmission waiting buffer selection circuit, 10a...Communication node on the sending side, 10b...Communication node on the receiving side.

Claims (2)

[Claims] Claim 1: Communication nodes are connected by a plurality of transmission links, and in order to transmit a packet from a certain first communication node to another communication node via the plurality of transmission links, In a packet transmitting device that transmits packets from one communication node to the plurality of transmission links, the first
A plurality of transmission waiting buffers are arranged in order from the first place to the second place (where n is an arbitrary integer), and a plurality of packets to be sent are arranged from the first place to the second place (where n is an arbitrary integer). (where m is an arbitrary integer), the packet with the first transmission order is sent to each of the plurality of transmission waiting buffers according to the order of the buffers, and the packet with the first transmission order is sent to the first transmission waiting buffer,
The second packet in the transmission order goes to the second transmission waiting buffer, and in the same way, the packet in the nth rank returns to the first buffer (when m>n) in a round robin manner. means for storing packets to be transmitted in each buffer in a buffer, a detection means for monitoring the plurality of transmission links and detecting the arrival of an empty packet; and when the arrival of an empty packet is detected by the detection means, the No matter which link among the plurality of transmission links, a unit number of packets are taken out from the plurality of transmission waiting buffers according to the order of free packets that arrived earlier in time and are loaded onto the link. , and switch means for switching and connecting between the plurality of transmission links and the plurality of transmission waiting buffers. 2. Communication nodes are connected by a plurality of transmission links, and a packet is transmitted from another communication node to a certain first communication node via the plurality of transmission links. a detection means for monitoring the plurality of transmission links and detecting the arrival of a packet addressed to the first communication node; (an arbitrary integer) When the detection means detects the arrival of a packet addressed to a plurality of ranked receiving buffers and the first communication node,
Regardless of which link among the plurality of transmission links the packets arrive at, the packets arrive in the order of arrival earliest in time.
According to the order among the plurality of reception buffers, the first packet to arrive is sent to the first reception buffer, the second packet to the second reception buffer, and so on. between the plurality of transmission links and the plurality of reception buffers so that incoming packets are received and stored in each buffer in a round-robin manner so that the buffer returns to the first buffer after the first buffer. A packet transmitting device comprising: switch means for switching and connecting.