JPH04235415A - Phase synchronizing loop circuit - Google Patents

Abstract

PURPOSE:To obtain the phase synchronizing loop circuit that the synchronous establishment time is short by determining the phase difference in input signals. CONSTITUTION:An address counter C1 allocates the count value in the inside reference signal to the digital input signal as an address value. A phase difference detection circuit C2 detects this address value at the edge position for this digital input signal. The average value of the phase difference measured each time the phase difference measurement necessary for one decided phase jump is performed is determined. When this value exceeds the preliminarily set allowable jitter amount, the average value of the phase difference calculated in an arithmetic circuit C4 is outputted as correction phase difference. The address counter C1 is reset by comparing the counted address value with the value of this correction phase difference. Thus, the synchronization between the phase of the digital signal and the phase of the inside reference signal is promptly confirmed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital PLL circuit suitable for semiconductor integrated circuits.

0002

[Prior Art] Conventionally, this type of digital PLL circuit is
As shown in FIG. 4, a loop counter C11 generates an internal reference signal, and a phase comparison circuit C12 compares the input signal 2 with the reference signal 4 output from the loop counter C11.
and a filter circuit C13 which inputs the delay signal 5, lead signal 6 or synchronization signal 7 which is the output of the phase comparator circuit C12, counts each state of delay or lead as a number, and outputs an up signal 8 or a down signal 9. It has The phase comparator circuit C12 compares the phase of the reference signal 4 obtained by the loop counter C11 with the phase of the input signal 2, and if the input signal 2 is delayed with respect to the reference signal 4, the delayed signal 5 is
If they are ahead, a lead signal 6 is output to the filter circuit C13, and if they are the same, a synchronization signal is output to the filter circuit C13. The filter circuit C13 checks whether or not the delayed signal 5 or the advanced signal 6 continues by an arbitrary number set in the count number setting signal group 10, and if the delayed signal 5 continues by the arbitrary number. An up signal 8 is output, and when an arbitrary number of advance signals 6 are consecutive, a down signal 9 is output. By repeating the above operations, the reference signal 4 output from the loop counter C11 is synchronized with the input signal 2.

0003

[Problem to be Solved by the Invention] In such a conventional digital PLL circuit, a phase jump can only be made by one operating clock in one phase jump, so the disadvantage is that the larger the phase shift, the longer it takes to establish synchronization. There is. In addition, when the period of the operating clock is increased by 1/n to increase the resolution of synchronization correction, the phase difference does not change in terms of time, so the count number of the loop counter increases by n times, and the phase pull-in time increases by n. Double. Therefore, in order to increase the resolution, there is a drawback that it is necessary to consider the phase acquisition time. In addition, since the judgment is only made based on the state of delay, lead, or synchronization, even after the phase has been pulled within the allowable jitter amount, the phase continues to be pulled in more than necessary, and the PL
There is a drawback that the clock generated by the L circuit always fluctuates.

SUMMARY OF THE INVENTION The present invention aims to eliminate such drawbacks and provides a phase-locked loop circuit with short synchronization establishment time.

[0005]

[Means for Solving the Problems] The present invention provides a phase-locked loop circuit that compares the phase of a digital input signal with the phase of an internal reference signal to confirm synchronization. An address counter that allocates the address value to the digital input signal, a phase difference detection circuit that detects the address value of the address counter at the edge position of this digital input signal, and determines the number of phase difference measurements required for one phase jump. a first filter circuit that
An arithmetic circuit that calculates the average value of the phase difference measured by the phase difference detection circuit for each number of phase difference measurements determined by this measurement filter circuit, and a permissible jitter whose average phase difference obtained by this arithmetic circuit is set in advance. a second filter circuit that outputs the average value of the phase difference calculated by the arithmetic circuit as a corrected phase difference when the value exceeds the value of the address value counted by the address counter; and a correction circuit that compares the values of the corrected phase differences and resets the address counter.

[0006] Here, the first filter circuit, the arithmetic circuit, and the second filter circuit may be realized by a program of a CPU.

[0007]

[Operation] The count value of the internal reference signal is assigned to the digital input signal as an address value. This address value is detected at the edge position of this digital input signal. The average value of the phase difference measured for each number of phase difference measurements required for one determined phase jump is calculated, and when this value exceeds the preset allowable jitter amount, the calculation is performed by the calculation circuit. The average value of the calculated phase differences is output as a corrected phase difference. The counted address value and this corrected phase difference value are compared, and the address counter is reset. Thereby, synchronization between the phase of the digital input signal and the phase of the internal reference signal can be quickly confirmed.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram of a first embodiment of the present invention.

The address counter C1 is a counter that divides one period of the input signal by a preset value, and recognizes the edge position of the input signal.
In response to the lock signal from 6, the count state is changed so that the lead or lag state becomes the synchronous state, and phase pull-in is performed. This address counter C1 inputs an operation clock 3 and a lock signal 14, and outputs an address 4 to a phase difference detection circuit C2 and a correction circuit C6. The phase difference detection circuit C2 inputs the address 4, the input signal 2, and the clear signal 8, and outputs the phase difference 5 to the arithmetic circuit C4. The measurement filter circuit C3 inputs the operation clock 3, the input signal 2, and the phase difference measurement number setting signal group 6, and sends the average signal 7 to the calculation circuit C4.
The clear signal 8 is output to the phase difference detection circuit C2 and the arithmetic circuit C4, and the correction range signal 9 is output to the jitter filter circuit C5 and the correction circuit C6. Arithmetic circuit C4
inputs phase difference 5, average signal 7 and clear signal 8,
The average phase difference of 10 is output to the jitter filter circuit C5. The jitter filter circuit C5 inputs the average phase difference 10, the allowable jitter amount setting signal group 11, and the correction range signal 9, and outputs the correction signal 12 and the correction phase difference 13 to the correction circuit C6. When the corrected phase difference 13 inputted from the jitter filter circuit C5 exceeds the range indicated by the correction range signal 9, the correction circuit C6 outputs a lock signal based on the corrected phase difference 13 and the address 4, and outputs a lock signal to the address counter C1. This is a circuit that performs pull-in, and inputs an address 4, a correction range signal 9, a correction signal 12, and a correction phase difference 13, and outputs a lock signal 14.
is output to address counter C1. Reset 1 is input to all blocks C1 to C6.

That is, as shown in FIG. 1, this embodiment includes an address counter C1 which divides the count value of an internal reference signal as an address value for a digital input signal;
A phase difference detection circuit C that detects the address value of the address counter C1 at the edge position of this digital input signal.
2, and a measurement filter circuit C, which is a first filter circuit that determines the number of phase difference measurements required for one phase jump.
3, an arithmetic circuit C4 that calculates the average value of the phase differences measured by the phase difference detection circuit C2 for each number of phase difference measurements determined by the measurement filter circuit C3, and an average phase difference obtained by the arithmetic circuit C4. a jitter filter circuit C5, which is a second filter circuit that outputs the average value of the phase difference calculated by the calculation circuit C4 as a corrected phase difference when the value exceeds a preset allowable amount of jitter, and the address counter. A correction circuit C6 is provided which compares the address value counted by C1 with the corrected phase difference value of the second filter circuit and resets the address counter C1. Here, the first filter circuit, the arithmetic circuit, and the second filter circuit may be realized by a program of a CPU.

The operation of this first embodiment will be explained with reference to the time chart shown in FIG.

It is assumed that the number of phase difference measurements of the measurement filter circuit C3 is set to "3" by the phase difference measurement number setting signal group 6, and the jitter filter circuit C5 is set by the allowable jitter amount setting signal group 11. Let the allowable amount of jitter be two address values for both the delay and lead. Also,
The address value by address counter C1 is 100 from "0" to "99", and the reference address value for synchronization is "
0". Therefore, the allowable jitter amount is ±2% (2/1
00).

First, after a power-on reset, the address counter C1 starts running on its own. At the first edge position (for example, rising edge) of the input signal 2, the phase difference detection circuit C2 holds the address value "3" of the address 4 output from the address counter C1, and is added to the arithmetic circuit C4. Similarly, the address value "5" is added at the second edge, and the address value "5" is added at the third edge. After the third address value addition, an average value is determined according to the average signal 7, and a phase difference of "4" (rounded off after the decimal point) is output from the average phase difference 10. At the rising edge of the correction range signal 9, the jitter filter circuit C5 holds the value "4" of the average phase difference 10, and outputs "1" to the correction signal 12 since the jitter amount is outside the allowable jitter amount ±2. Correction signal 1
2 and the correction range signal 9 are "1", the correction circuit C6 compares the address value from the address 4 and "4" from the correction phase difference 13, and when they match, the lock signal 14 is output. outputs "0" to the address counter C1 (address value 0). The address value obtained at the fourth edge of input signal 2 becomes "1". After the fifth period of the input signal 2, it becomes stable and becomes a periodic state as long as the address value is within the allowable jitter amount ±2.

[0014] If the deviation between the average phase difference and the phase difference immediately before a phase jump becomes large due to large fluctuations in the phase difference, and synchronization cannot be achieved with one phase jump, the next correction is made using the address value after the first correction. Find the phase difference and perform a phase jump. Repeat the above steps to establish synchronization.

In a conventional digital PLL circuit, it takes 3 {filter setting value} x (5 {number of counts during phase difference}) to pull down to ±2% of the allowable jitter amount under the same conditions as in this embodiment.
-2 {allowable jitter amount}) x T {1 cycle of input signal} = 9
Although T time was required, in this embodiment, it can be retracted in a time of (3 {measurement filter setting value}+1)×T=4T. Furthermore, since the calculation formula requires only the set value of the measurement filter, time can be reduced.

Furthermore, since conventional digital PLL circuits make judgments based on the delayed, advanced, or synchronous state, even after the phase has been pulled within the allowable jitter amount, the phase continues to be pulled in more than necessary, causing the clock generated by the PLL circuit to However, in this embodiment circuit, the determination is made based on the phase difference, so the jitter filter circuit can provide an allowable amount of jitter and improve the stability of the clock generated by the PLL circuit.

[0017] Furthermore, in the conventional digital PLL circuit,
When the period of the operating clock is increased by 1/n times in order to increase the resolution of synchronization correction, the phase difference does not change in terms of time, so the number of operating clocks increases by n times, and the phase pull-in time increases by n times. Therefore, in order to increase the resolution, it was necessary to consider the phase pull-in time, but in this example circuit, the number of counts in the phase difference is not relevant in calculations, so the resolution of synchronization correction can be improved regardless of the phase pull-in time. can.

FIG. 3 is a functional block diagram of a second embodiment of the present invention.

Address counter C1 inputs operation clock 3 and lock signal 14, and outputs address 4 to phase difference detection circuit C2 and correction circuit C6. The phase difference detection circuit C2 inputs the address 4, the input signal 2, and the clear signal 8, and outputs the phase difference 5 to the CPU interface C7. The correction circuit C6 inputs the address 4, the correction range signal 9, the correction signal 12, and the correction phase difference 13, and outputs the lock signal 1.
4 is output to address counter C1. The CPU interface C7 inputs the input signal 2, the operating clock 3, and the phase difference 5, outputs the clear signal 8 to the phase difference detection circuit C2, and outputs the correction range signal 9, the correction signal 12, and the correction phase difference 1.
3 is output to the correction circuit C6. It also inputs and outputs arbitrary signals to and from the CPU. Reset 1 resets all blocks C1, C2,
It is input to C6 and C7.

Next, the operation of this second embodiment will be explained.

Address counter C1, phase difference detection circuit C
2 and the correction circuit C6 operate in the same manner as in the first embodiment. Further, the CPU interface C7 is a block configured so that the operations of the three circuits of the first embodiment, the measurement filter circuit C3, the arithmetic circuit C4, and the jitter filter circuit C5, can all be controlled by a CPU program.

The contents of the program and the signal transmission and reception of the CPU interface C7 will be explained. CPU interface C7
Then, the phase detection circuit C2 continues to output the phase difference 5 held by the edge position (for example, rising edge) of the input signal 2 to the CPU at arbitrary intervals. In the program, the input phase difference is averaged for each number of measurements, and each time it is determined whether it is within the allowable jitter amount. If it is within the range, the average phase difference is set to "0", and if it is outside the range, it is set to "0". The average phase difference is C
Output to PU interface C7. The CPU interface C7 outputs the average phase difference input from the CPU from the correction phase difference 13, and only when the average phase difference is other than "0", outputs the correction signal 12 to correct it and establish synchronization.

Since it can be controlled by a program through the CPU, it is possible to perform not only correction based on the average phase difference but also correction based on a complex algorithm.

Furthermore, by changing the number of measurements and the allowable amount of jitter depending on the synchronization state, the effect of improving the characteristics can be obtained. For example, in the initial state where the frequency fluctuation of the input signal is large, if the number of measurements and the amount of allowable jitter are large, the stability of the clock generated by the PLL circuit will be high, but if the number of measurements and the amount of allowable jitter are small, the clock generated by the PLL circuit will be stability decreases. Furthermore, during synchronization, if the number of measurements and the amount of allowable jitter are reduced, the response to sudden changes will be faster, but if the number of measurements and the amount of allowable jitter are large, the response to sudden changes will be slow.

[0025]

As described above, the present invention has the effect of shortening the time required to establish synchronization by determining the phase difference between input signals.

Furthermore, since the phase difference is phase-jumped at once, the resolution can be improved regardless of the time required to establish synchronization.

Furthermore, since the jitter filter circuit determines that the synchronization is within the allowable amount of jitter, it is possible to eliminate unnecessary phase pull-in and use a CPU interface with high stability of the clock generated by the PLL circuit to support programming. This has the effect of allowing the use of complex algorithms to determine the corrected phase difference.

Furthermore, since the number of phase measurements and the allowable amount of jitter can be changed by a program according to the synchronization state, it is possible to expect an improvement in characteristics.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of a conventional example.

[Explanation of symbols]

C1 Address counter C2 Phase difference detection circuit C3 Measurement filter circuit C4 Arithmetic circuit C5 Jitter filter circuit C6 Correction circuit C7 CPU interface C11 Loop counter C12 Phase comparison circuit C13 Filter circuit

Claims (2)

[Claims] Claim 1: In a phase-locked loop circuit that compares the phase of a digital input signal and the phase of an internal reference signal to confirm synchronization, an address that allocates the count value of the internal reference signal as an address value to the digital input signal. a counter, a phase difference detection circuit that detects the address value of the address counter at the edge position of the digital input signal, and a first filter circuit that determines the number of phase difference measurements required for one phase jump; An arithmetic circuit that calculates the average value of the phase difference measured by the phase difference detection circuit for each number of phase difference measurements determined by this measurement filter circuit, and a permissible jitter whose average phase difference obtained by this arithmetic circuit is set in advance. a second filter circuit that outputs the average value of the phase difference calculated by the arithmetic circuit as a corrected phase difference when the value exceeds the value of the address value counted by the address counter; A phase-locked loop circuit comprising: a correction circuit that compares values of corrected phase differences and resets the address counter. 2. The phase-locked loop circuit according to claim 1, wherein the first filter circuit, the arithmetic operation circuit, and the second filter circuit are implemented by a CPU program.