JPH0423519A - Decoding circuit for bipolar signal - Google Patents

Abstract

PURPOSE:To improve the reliability of the decoding circuit for a bipolar signal by decoding without erasing a data regardless of the existence of an error signal. CONSTITUTION:A code decoding means 5 detects a 'BOOV' pattern which converts a series of four '0' signals to a code from the outputs of both a signal shifting means 3 and a bipolar rule infraction signal detecting means 4 and decodes it by erasing only the 'B'. Moreover, an error signal detecting means 6 detects the error signal both from the output of the logical sum of the positive and negative electrode side signal of the bipolar rule signal and from the intermediate output of the code decoding means 5. Therefore, it is possible to decode without erasing the data regardless of the existence of the error signal. Thus, the reliability of the decoding circuit for the bipolar signal is improved.

Description

[Detailed description of the invention] [Summary] When "0" is consecutive four or more times, "l" is inserted and 4
Regarding the bipolar signal decoding circuit that prohibits continuous "0", the purpose of preventing the original data from being erased due to an error signal during decoding in the decoding circuit is to provide a four consecutive "0" prohibition signal including the error signal. input signal holding means for holding a positive side signal and a negative side signal of the four consecutive "o" prohibition signals including the error signal; , bipolar law identification means for outputting a bipolar law signal, a positive side signal and a negative side signal that violate the bipolar law, and a polarity display signal of the bipolar law signal from the output of the input signal holding means, and shifting the bipolar law signal. 1- By doing so, the signal shift means 1 to monitor whether the bipolar law signal is a "Boo" pattern or not, and the positive polarity side signal and negative polarity side signal that violate the bipolar law and the polarity display signal are inputted. Then, the logical sum output of the positive side signal and the negative side signal that violates the bipolar rule, and the error signal are removed and “BOO
From the bipolar rule violation signal detection means that outputs a polarity display signal indicating the presence or absence of the pattern "B" as "1" and "0", and the re-output of the signal shifting means and the bipolar rule violation signal detection means, “B” which is code converted from 4 consecutive “0” signals
code decoding means that detects the OOV" pattern and performs decoding to erase the added °゛B"signal; and error signal detection that detects an error signal from the above-mentioned OR output and intermediate output of the code decoding means. means, and is configured to be able to decode data without erasing it, regardless of the presence or absence of an error signal.

[Industrial Field of Application] The present invention relates to a bipolar signal decoding circuit that inserts a specific pattern to prohibit four consecutive "0's" when "0's" occur four or more times in a row.

[Conventional technology]

When converting an analog signal such as a video into an original bipolar signal that does not return to zero, and detecting and decoding four consecutive degrees of "0" from the positive and negative signals that are parts of the original bipolar signal, the process shown in Figure 6 is performed. As shown in the explanatory diagram of the 4 consecutive "0's" prohibition code, the "'ooo" signal, which is 4 consecutive "0's", is converted into a specific signal pattern, that is, "1001" or "0001".
and insert it into the positive side signal or the negative side signal. This particular signal pattern insertion method is
``1001'' is stipulated in the prohibited code rules, and ``1001'' is ``B''.
OOV", and '0001°' is written as "ooov".

In this case, "B" is "do" according to the bipolar rule, and "V"
” means a bipolar rule violation signal.

A to D in FIG. 6 show four ways of inserting 4 consecutive "0" prohibition codes, (a), (d), (rumor, (j)
is “1” and 0 before being divided into positive side signal and negative side signal
”, and (b) and (e)
, (h), (k) are positive side signals, (C), (i)
, (ri is the negative side signal. For example, as in the X area of FIG. 6A, the signal (a) is 4 consecutive "0" and 4 consecutive "
If the signal "1" immediately before "0" is on the positive side, ""BoOOVo" is inserted into the part of four consecutive "0"s on the negative side. Also, as in the YOU area in FIG. 6A, the signal ( a) is 4 consecutive "0" and 4 consecutive "
If the 0" prohibition code °゛vo" and the immediately preceding signal "B1" have the same polarity, "B20" is placed in the 4 consecutive "0°" portions on the positive side.
0V2''. The same applies to B, C, and D in FIG. 6 below.

FIG. 4 is a diagram showing a circuit configuration of a conventional embodiment, and FIG.
A continuous “0” prohibition decoding circuit is shown. Further, FIG. 5 is a time chart of a circuit of a conventional embodiment. In FIG. 4, 31 is a -D flip-flop circuit (hereinafter -DFF).
32 is a second DFF, and 33 is a -JK flip-flop circuit (hereinafter referred to as -JKFF). Further, 34 to 36 constitute selection circuits, 34 and 35 are the -AND and second AND of the three-signal AND operation circuit, and 36 is 108 of the three-signal OR operation circuit. Similarly 37-3
9 constitutes a selection circuit, 37 and 38 a third AND and a fourth AND, and 39 a second OR. Note that 40 is the third DFF
, 41 is the fourth DFF, 42 is the fifth DFF, 43 is the sixth DFF
FF, 44 is the seventh DFF. Furthermore, 45 is a NAND of a three-signal NAND circuit, 46 is a fifth AND, and 47 is a seventh DFF. In addition, in FIG. 5, (a) to (0)
are the signals at the respective positions in FIG.

In FIG. 5, signal (a) is the original bipolar signal with non-return to zero, and 1 and 0 are 1000011.010000.
These are signals arranged in the order of 00001100011... Signal (C) and signal (d) are obtained by dividing signal (a) into a positive side signal and a negative side signal, and signal (C) is 100
0V, O]000000B, 0OV30100EO...
・And the signal (d) is 000001001000
V200001000010 - . . . Assume that there is a signal (C) and that an error signal "E" is inserted at timing 0 of the clock (b). The signal (C) is input to the second DFF31, and the signal (d) is input to the second DFF31.
F32, each is hit by clock (b), and the operation of shifting one clock at a time is repeated, and the fifth
The fifth AND 46 operates to send out the non-return-to-zero decoded signal (0) shown in the figure.

First, the signal (C) is clocked (
The Q output, which is struck at the timing of (■) in b) and shifted by one clock, is added to the first 0R36 and the third AND37. Similarly, the signal (d) is also applied to the second DFF 32, and the Q output shifted by one clock is applied to the second AND 35 and the fourth AND 38. The Q outputs of the -th DFF 31 and the second DFF 32 are determined by the toggle state of the Q outputs of different polarities output from the -JKFF 33 and the *Q ratio output "1pa" or "0". -AND34 → 1st 〇R36
Or, select whether to pass through the second AND35 → -〇R36, or the third AND37 → the 20th R3, the 29th R39AN
A selection is made as to whether to pass from D38 to No. 20R39. For example, if the output of No. 10R36 is "0'' at timing (b) of clock (b), the signal (e
) is "1" and the signal (f) is "o", and in this case, the output (g) of the first 0R36 is only the signal "B1", and the output (h) of the second 0R39 is the signal "vI".
9, "v2", "v3'" and an error signal "E".

That is, "B", ° "V", " of the signal (C) and signal (d)
E'' is separated into two: a bipolar law signal ((2) "B") and a bipolar law violation signal (b) "V'" and "E".

Next, the output (g) of the first 0R36 is shifted by one crotch in each of the third DFF 40 to the sixth DFF 43 connected in series, and the Q output (g) of the same polarity as the signal (g) is output from the third DFF 40. i), the fourth DFF41 outputs *Q ratio output j) of inverted polarity, and the fifth DFF42 outputs *Q ratio output j) of inverted polarity.
The Q ratio output j) is output from the sixth DFF 43, and the Q output (ri) is output from the sixth DFF43.
), (I becomes a bipolar law signal having only "B".

On the other hand, the NAND 45 contains a signal (
h) is shifted by one clock in the seventh DFF 44, and the obtained Q output (m) and the above-mentioned signals (j) and (k) are added. Furthermore, as shown in signals (j) to signals (m) in FIG.
*Q ratio output j) and (k) from 42 are “1” of positive polarity signal.
”, so the NAND45 converts “V” and “E”
The detection signal (m) is inverted and becomes "0". Therefore, the output of the fifth AND46 is "B", "V"' and "E".
is erased and becomes "0", resulting in a non-zero return decoded signal (0).

In addition, the fifth AND46 takes the AND of the signal (1) and the signal (n) and inserts "ν" according to the 4 consecutive "0" prohibition sign rule.
” and “B”, but at the same time, the data at the timing [phase] of the clock (b) is also erased by the error signal “E”.

[Problem to be solved by the invention]

Therefore, in the 4 consecutive "O" prohibition decoding circuit, the error signal "E" is mixed into the input signal and the bipolar pulse "B" is generated.
If "BOOE" has the same polarity as "BOOE", there is a problem that a normal signal may be erased by mistake due to the error pulse "E".

The present invention aims to prevent original data from being erased due to an error signal during decoding in a decoding circuit.

[Means to solve the problem]

The present invention inputs a 4-consecutive "0" prohibition signal including an error signal and decodes it into a 4-consecutive "0" signal from which the error signal is removed.
An input signal holding means 1 holds the positive side signal and the negative side signal of the prohibition signal, and from the output of the input signal holding means 1, a bipolar law signal, a positive side signal and a negative side signal violating the bipolar rule, and the bipolar law The bipolar law identification means 2 outputs a signal polarity indicating signal, and by shifting the bipolar law signal, the bipolar law signal becomes "BO
Signal shift means 3 for monitoring whether or not the pattern is O”
Then, the above-mentioned positive side signal, negative side signal and polarity display signal that violate the bipolar rule are input, and the OR output of the positive side signal and the negative side signal that violates the bipolar rule and the error signal are removed and "Boo a bipolar rule violation signal detection means 4 that outputs a polarity display signal indicating the presence or absence of "B" in the "pattern" as "1" and "0"; and the signal shifting means 3.
and code decoding means 5 which detects a "BOOV" pattern resulting from code conversion of four consecutive "0" signals from the re-output of the bipolar rule violation signal detection means 4, and performs decoding to erase this added "B" signal. , the above logic phase output and code decoding means 5
An error signal detecting means 6 for detecting an error signal from the intermediate output of is provided, and the structure is such that data can be decoded without erasing regardless of the presence or absence of an error signal.

[For production]

In the present invention, as shown in FIG. 1, the input signal holder]
``The positive side signal and the negative side signal of the prohibition signal are input to the bipolar rule identification means 2, and are separated into a bipolar rule signal, a positive side signal and a negative side signal that violate the bipolar rule, and a polarity display signal of the bipolar rule signal. Shifting the bipolar law signal to the signal shifting means 3 and monitoring whether the bipolar law signal has a "BOO"pattern;
In addition, the bipolar rule violation signal detection means 4 removes the OR output of the positive side signal and the negative side signal of the bipolar rule signal and the error signal from the above-mentioned positive side signal and negative side signal of the bipolar rule violation and the polarity display signal. And “B”
A polarity display signal indicating the presence or absence of "°B"' in the "OO" pattern is output as 1" and "0".

Therefore, the code decoding means 5 receives four consecutive "
It becomes possible to detect the "BOOV" pattern obtained by converting the code of the "0" signal and perform decoding that erases only the "B".
Further, the error signal detection means 6 can detect an error signal from the above-mentioned logical sum output and the intermediate output of the code decoding means 5.

[Embodiment] FIG. 2 is a diagram showing a circuit configuration of an embodiment of the present invention.
A four-consecutive "0-pa prohibition decoding circuit is shown. FIG. 3 is a time chart of a circuit according to an embodiment of the present invention. In FIG.
11 and 12 are circuits corresponding to the input signal holding means 1;
11 is a -th DFF, and 12 is a second DFF. 13-1
6 is a circuit corresponding to the bipolar rule identification means 2; 13;
are AND circuits 13a, 13. 14 and 15 are -AND and second AND, and 16 is -JKFF. 17 to 19 are circuits corresponding to the signal shift means 3, and 17 is a third DFF.
, 18 is the fourth DFF, and 19 is the fifth DFF. Also 2
0 to 22 are circuits corresponding to the bipolar rule violation signal detection means 4, 20 is the first 0R121 is the second JKFF, 22
is a second selector having an AND circuit 22a22b and an OR circuit 22c. Furthermore, 23 and 24 are code/decoding means 5.
23 is a circuit corresponding to NAND, 24 is a third AN
D, and 25 is the fourth A corresponding to the error signal detection means 6.
It is ND. 26 is a sixth DFF, 27 is a 3-bit shift register, and 28 is a seventh DFF. In FIG. 3, (a) to (1) are signals at respective positions in FIG. 2.

In Fig. 3, signal (a) is the original bipolar signal with non-return to zero, and ■ and O are 1.000011010000.
The signals are arranged in the order of 00001100011..., and the signal (C) is 1000V, 01000000B300V
The positive side signal becomes 30100EO..., and the signal (d
) is 0O0001001000V, 0O0010000
10... is the negative side signal. Note that the signal (C) contains an error signal “E” at the timing @ of the clock (b).
” is inserted. This signal (C) is 10FFII
and the signal (d) is input to the second DFF 12,
By repeating the operation of shifting l clocks by clock (b), the non-zero return decoded signal shown in FIG. 5 is output from the sixth DFF 26, and the error signal (1) is output from the seventh DFF 28. .

First, the signal (C) is clocked (
The Q output of the hold signal that is hit and held at the timing of (2) in b) and shifted by one clock is applied to the AND circuit 13a and the -AND 14 of the first selector 13. Similarly, the signal (d) is also held in the second DFF 12, and the Q output of the held signal that has been clock shifted from 1 to
Add to circuit 13b and second AND15.

The Q outputs from the -th DFFll and the second DFF 12 are toggled between the Q outputs of different polarities output from the -JKFF 16 and the *Q ratio output "1" or "0". Selection of output from the OR circuit 13c via the AND circuit 13a of the first selector 13, or selection of output from the OR circuit 13c via the AND circuit 13b, and selection of passing through the -AND 14 or the second AND 15 will be done. Now the output of the first selector 13 is “1”
is input to the -JKFF16, and when the signal (e) output from the -JKFF16 at the timing (b) of clock (b) is "1" and the signal (g) is "0", the first selector 13 output ((A) is the signal “B3” (hereinafter “B
”), and the output (h) of the -th AND14 is a violation of the bipolar rule on the positive side with “V,” and “v3′ (hereinafter referred to as odd number “V”) and an error signal “E”. Similarly, the output (i) of the second ANDL5 is v2
” (hereinafter referred to as an even number “V”), which is a bipolar law violation signal on the negative side. That is, the first selector 13 and the −AN
At DI4 and second AND15, signal (C) and signal (cl
) is identified and output as three: "B", odd numbers "V'" and "E", and even number "v".

Next, the bipolar law signal (
g) is shifted by one crotch each in the third DFF17 to fifth DFF19 in three stages in series, and the first FF17
*Q ratio output j) with inverted polarity from the fourth DFI 218, *Q ratio output k) with inverted polarity from the fourth DFI 218, and similarly, the fifth DFF1
From 9, Q output (ri) is output. Note that this signal (j),
At (k) and (ri), it is monitored whether the first three signals among the four consecutive "0"s are a "BOO" pattern.

On the other hand, the first 0R20 receives a signal (h
) and (1), the bipolar rule violation signal (m
) is output. Also, since the bipolar law violation signal (h) on the positive side is input to the J input of the second JKFF21, and the bipolar rule violation signal (i) on the negative side is input to the input, the Q input of the second JKFF21 An alternating signal (n) of "1" and "0" is output from the output according to the polarity of the input signal, and the *Q ratio output of the second JKFF21 is the signal (n).
An inverted alternating signal (0) is output. Note that 4 consecutive “0”
According to the forbidden sign rule, the signal "V" always appears alternately positive and negative, so for example, the error signal "E" in the positive side signal (h)
” will no longer be recognized and recognized as a bipolar rule violation signal,
As shown in FIG. 5(0) in the conventional example, it is no longer possible to erase data due to 'BOOR'.

When the Q output (rl) of the second JKFF21 is "1", it means that an odd number "V" has been input, so the signal "B" that is erased when the specific pattern "BOOV" is input next is This is a bipolar signal on the negative side. Similarly,
When the *Q ratio output of the second JKFF 21 is "1", the signal "B" to be erased is a positive-side bipolar signal. In other words, the polarity of the preceding signal "V" and the polarity of the signal "B" erased by 'BOOV' are always opposite polarities. Therefore, the polarity display signal of the second selector 22 that violates the bipolar rule (
p) is “1”, the third DFF17 and the fourth DFF18
The signal "B" to be erased held in the signal "B" becomes a signal of opposite polarity to the preceding signal "V".

Furthermore, the NAND 23 has a shift signal (, i
) and (k), the logical sum signal (m) of the bipolar rule violation signal, and the polarity display signal (P) are input, and the NAND 23 calculates the negative AND of the four signals, and the bipolar rule of the logical sum is obtained. The violation signal (m) is inverted and the error signal “
Outputs the intermediate signal (q) that violates the bipolar rule with the error signal "E" removed.The intermediate signal (q) with the error signal "E" removed is output.
q) is input to the third AND24 together with the shift signal (I!,) from the fifth DFF19, and the signal "B" and the signal "V" are input to the third AND24.
The same non-zero return signal (r) as the original signal (a) with
The data is then decoded into a sixth DFF 26 and output. Furthermore, in the fourth AND25, the logical sum (
m) and the intermediate signal (q), and the signal “°V” is obtained.
Detection is performed to separate the error signal "El+" from the inside, and for example, the positive side signal (C) is
After adjusting the phase by 3 pit shifts so that the phase is equivalent to that of , it is held in the seventh DFF 28 and output.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, data is not erased due to an error signal, and the reliability of a bipolar signal decoding circuit can be improved.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle configuration of the present invention, Fig. 2 is a diagram showing the circuit configuration of an embodiment of the invention, Fig. 3 is a time chart of the circuit of an embodiment of the invention, and Fig. 4 is a diagram showing the circuit configuration of an embodiment of the invention. FIG. 5 is a diagram showing a circuit configuration of a conventional embodiment, FIG. 5 is a time chart of the circuit of a conventional embodiment, and FIG. 6 is an explanatory diagram of a four-consecutive "0" prohibition code. In the figure, (2) is a human signal holding means, 2 is a bipolar law discrimination means, 3 is a signal shift means, 4 is a signal detection means, 5 is a code decoding means, and 6 is an error signal detection means.

Claims (1)

[Claims] In a device that inputs a 4-consecutive "0" prohibition signal including an error signal and decodes it into a 4-consecutive "0" signal from which the error signal has been removed, the 4-consecutive "0" prohibition signal including the error signal is decoded. An input signal holding means (1) that holds a positive side signal and a negative side signal of a signal; and a bipolar law signal, a positive side signal and a negative side signal that violate the bipolar rule, and bipolar law identification means (2) for outputting a polarity indicating signal of the bipolar law signal; and signal shifting means for monitoring whether or not the bipolar law signal has a "BOO" pattern by shifting the bipolar law signal. (3), input the positive side signal and negative side signal that violate the bipolar rule, and the polarity display signal, and remove the OR output of the positive side signal and the negative side signal that violate the bipolar rule, and the error signal. And the presence or absence of “B” in the “BOO” pattern is “1”
bipolar law violation signal detection means (4) that outputs a polarity display signal represented by "0" and "0"; and the signal shift means (3)
) and the bipolar law violation signal detection means (4), a code decoding unit detects a “BOOV” pattern obtained by converting the code of four consecutive “0” signals, and performs decoding to erase this added “B” signal. means (5), and error signal detection means (6) for detecting an error signal from the above-mentioned OR output and the intermediate output of the code/decoding means (5), and detects the data regardless of the presence or absence of the error signal. A bipolar signal decoding circuit characterized in that it can be decoded without erasing it.