JPH02113380A - Pattern data generating circuit - Google Patents

Abstract

PURPOSE:To generate pattern data of optional bit length by providing a register file where linear pattern data is stored by using a plural-word register and performing the operation for writing to a shift circuit and the shift operation of the shift circuit cyclically. CONSTITUTION:The shift circuit 2 stored with the contents of registers selected by a decoder 7 as to linear pattern data stored in successive registers of the register file 1 shifts and outputs pattern data according to a shift clock and a counter 1 counts up by one at the same time in synchronism with the shift clock. Then a comparator 6 compares the value of a counter with the value in a pattern bit length register 3 and stores the contents of a next register in the shift circuit 2 when the counter value is coincident or when a carry to a higher-order bit field from a lower bit field for counting the number of bits in one word of the counter is generated. Consequently, pattern data of optional bit length which is long enough to extend over plural words can be generated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a pattern data generation circuit that cyclically generates one-dimensional pattern data.

Conventional technology FIG. 3 shows this conventional pattern data generation circuit.
0 is a register that holds a fixed pattern. A data expansion circuit 11 expands the contents of a specific bit of the register 10 into one word.

14 is a shift circuit that circularly shifts the contents of register 1 to the left and right. Reference numeral 17 is a bit address register indicating the bit address of the transfer destination.

16 is a first latch circuit. Reference numeral 16 denotes a second latch circuit that stores one word of data of the corresponding transfer destination. A decoder 19 decodes the contents of the bit address register 17 and outputs a mask selection signal effective during bit-by-bit transfer.

21 is for the bit selected by the decoder 19: the first . This is an arithmetic unit that performs calculations between the second latch circuits 15 and 16, and outputs data from the second latch circuit 16 as is for unselected bits. 22 is a third latch circuit that stores the output of the arithmetic unit 21.

In the conventional pattern data generation circuit configured as described above, when transferring data in units of words such as coloring, the contents of register 1 are used as they are as the data to be transferred. When transferring bit-by-bit data such as line segment generation, the contents of a specific bit in register 1 are expanded to one word by data expansion circuit 2 as the transfer source data, and only the pit position specified by the bit address register is used. Perform calculations. When one transfer is completed, the contents of register 1 are circularly shifted by shift circuit 3 to generate pattern data.

Problems to be Solved by the Invention However, in the above configuration, the bit length of the pattern data used for line segment generation and line crushing is fixed to the bit length of register 1, so that a pattern longer than one word can be created. The problem was that it was not possible to generate data or pattern data shorter than one word.

In view of this, an object of the present invention is to provide a pattern data generation circuit that generates pattern data of arbitrary bit length used in line segment generation and filling.

Means for Solving the Problems The present invention provides a register file that stores one-dimensional pattern data using multiple word registers when it cannot be stored in one word, and a register file that stores one-word data read from the register file. a shift circuit that sequentially shifts and outputs pattern data from specific bits according to a clock;
A register that stores the bit length of one-dimensional pattern data, a counter that adds 1 in synchronization with the shift operation of the shift circuit, and one word in the register file is selected by the upper bit field of the contents of the counter. a decoding circuit; a comparator that compares the contents of the counter with the contents of the register and outputs a match signal if they match;
When the above comparator outputs a match signal or when a carry occurs from the lower bit field to the upper bit field indicating the bit position within one word of the counter, the signal selected by the decoding circuit in the register file is This pattern data generation circuit is characterized in that it successively writes the contents of a register, and cyclically performs a write operation to the shift circuit and a shift operation of the shift circuit.

Effect of the present invention With the above-described configuration, among the one-dimensional pattern data stored in consecutive registers of the register file,
The contents of the register selected by the decoder are stored in the shift circuit. The shift circuit shifts and outputs pattern data according to the shift clock, and at the same time adds 1 to the counter based on the shift clock. Compare the value of the counter and the value of the pattern bit length register using a comparator,
If they match, the data is stored in the shift circuit from the register selected by the register file decoder. Also,
Counting the number of bits in one word of a counter When a carry occurs from a lower bit field to an upper bit field - The contents of the next consecutive register in the register file are stored in the shift circuit. By cyclically performing the above operations, it is possible to generate pattern data of any bit length spanning multiple words.

Embodiment FIG. 1 shows a block diagram of a pattern data generation circuit in an embodiment of the present invention. In Figure 1,
1 is a register file, 2 is a shift register, 3 is a pattern bit length register, 4 is an adder 1, 5 is a register that stores the output of the adder 1, and e is a comparator that compares register 6 and pattern bit length register 3. , 7 is a first decoder that decodes the upper contents of register 5, 8 is a control circuit, 9 is a system bus, 11 is a data expansion circuit similar to the conventional example, and 15 is a first latch circuit similar to the conventional example. , 16
1 is a second latch circuit similar to the conventional example, 17 is a bit address register similar to the conventional example, 19 is a second decoder similar to the conventional example, 21 is an arithmetic unit similar to the conventional example, and 22 is the same as the conventional example. A similar third decoder.

The operation of the pattern data generation circuit of this embodiment configured as described above will be explained below.

Prior to pattern data generation, one-dimensional pattern data is sequentially written word by word into consecutive registers of the register file 1 through the system bus 9. Further, the bit length of the one-dimensional pattern data stored in the register file 1 is written into the pattern bit length register 3. Next, the contents of the register 5 are reset by activating the reset signal. Furthermore, when the contents of the register 6 are reset, the first decoder performs decoding to select the first register of the register file 1.

Furthermore, by activating the reset signal, the contents of the first register of the register file 1 are stored in the shift register 2. The shift clock generated by the control circuit 8 (
Thereafter, the contents of shift register 2 are shifted by 5CLK). At the same time, 5CLK is input to the register 6, and the output of the 1 adder 4 is stored.

First, the bit length of the one-dimensional pattern data is shown in Figure 3 (I
Let's consider the case of 1 word or less as shown in L). By repeating the above operation, the contents of register 6 are sequentially changed to 1
It is added up. The contents of register 5 and the contents of pattern bit length register 3 are compared by comparator 6, and if they match, a match signal is output. By outputting the match signal, the contents of the register 6 are reset, and the first register of the register file 1 is selected by the first decoder 7, and its contents are stored in the shift register 2. Thereafter, by repeating the above operations, fixed one-dimensional pattern data is cyclically output from the shift register 2 in MSB order.

Next, the bit length of one-dimensional pattern data, Figure 3 (b
), let us consider the case where the length is longer than one word. 5
By the shift operation of the shift register 2 by CLK and the update by the 1 adder 4 of the register 5, all bits of one word of the shift register 2 are shifted out. In this case, 1
A carry from a lower to a higher bit indicating a bit position within one word of the adder 4 occurs. This carry causes the first decoder 7 to decode the upper bits of the register 5, select consecutive registers in the register file 1, and store their contents in the shift register 2. By repeating the above operations, the contents of consecutive registers in the register file 1 are sequentially stored in the shift register 2 and shifted out. At the end, when the contents of the register 5 and the contents of the pattern bit length register 3 match, a match signal is sent from the comparator 6, similar to the operation when the bit length of the one-dimensional pattern data is within 1 word. By outputting , the contents of the register 6 are reset, and the contents of the first register of the register file 1 are stored in the shift register 2. Thereafter, by repeating the above operations, fixed one-dimensional pattern data is cyclically output from the shift register 2 in MSB order.

As described above, the bit data stored in the register file 1 and cyclically shifted and outputted from the next one-dimensional pattern data starting from the MSB of the shift register 2 is expanded into raw word data by the data expansion circuit 11. The output of the data expansion circuit 11 is stored in the first latch circuit. Also,
The contents of the third latch circuit are stored in the second latch circuit 2. A desired operation is performed on the contents of the first latch circuit 15 and the second latch circuit 16 by the arithmetic unit 21. The contents of the bit address register 17 indicating the write pit position of the third latch circuit 22 are decoded by the second decoder 19 and used as mask data of the operation result of the arithmetic unit 21. The output of the arithmetic unit 21 at the valid position of this mask data is written into the third launch circuit 22.

Through the above operations, line segments are generated in which the one-dimensional pattern data of arbitrary bit length stored in the distaff file 1 is used in the third latch circuit 22 cyclically as a line type pattern.

Note that the shift clock (SCLK) generated by the control circuit 8
), one-dimensional pattern data can be easily expanded.

As described in detail, according to the present invention, it is possible to rapidly generate one-dimensional pattern data of arbitrary bit length for use in line segment generation and fill-in by using a register with a fixed bit length. Its practical effects are great.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a pattern data generation circuit according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of pattern data of the same embodiment, and FIG. 3 is a block diagram of a conventional pattern data generation circuit. 1...Register file, 2...Shift register, 3...Pattern bit length register, 4...1 adder, 6... register,
6...Comparator, 7...First decoder, 8...Control circuit, 9...System bus, 1o...・Register, 11... Data expansion circuit, 16, 16.22... 1st. Second. Third latch circuit, 17... pit address register, 19... decoder, 21...
・Arithmetic unit. Name of agent: Patent attorney Shigetaka Awano and one other person Figure (lll) (b) Figure

Claims (1)

[Claims] If one-dimensional pattern data cannot be stored in one word, create a register file that stores multiple words in consecutive registers, and store the one-word data read from the register file and sequentially read the pattern data from a specific bit position according to the clock. A shift circuit that outputs a shift,
A register that stores the bit length of one-dimensional pattern data, a counter that adds 1 in synchronization with the shift operation of the shift circuit, and one word in the register file is selected by the upper bit field of the contents of the counter. a decoding circuit; a comparator that compares the contents of the counter with the contents of the register; and outputs a match signal if they match; When a carry occurs from the lower bit field to the upper bit field to be counted, the contents of the next register selected by the decoding circuit in the register file are read, and the write operation to the shift circuit and the above shift are performed. A pattern data generation circuit characterized in that a circuit shift operation is performed cyclically.