JPH04233671A - Device and method for recognizing pattern - Google Patents

Abstract

PURPOSE:To enable a high-speed processing by executing pattern matching between a divided reference pattern and a data within time for fetching the data of one frame even at a correlator having throughput smaller than the reference pattern, cumulatively adding the dividing number for each reference coordinate and calculating a matching number at all the reference patterns. CONSTITUTION:The reference pattern is generated from image information binarizing signals for one frame inputted from an image pickup device 1, and this reference pattern is divided into patterns in the equal size and stored in a memory 4. While inputting the signals for one frame from the above-mentioned image pickup device 1, the signal is exchanged for each coordinate for the unit of the divided pattern, the pattern matching number is calculated for the unit of the divided pattern for each coordinate and the number is cumulated to the matching number stored in a matching number cumulating memory 8 so as to calculate the pattern matching number at all the reference patterns.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern recognition device capable of shortening processing time when performing pattern matching processing, and in particular to a pattern recognition device that can shorten processing time when performing pattern matching processing.
The present invention relates to a pattern recognition device and method suitable for use in bonding devices for semiconductor components of large-scale integrated circuits (LSI) and large-scale integrated circuits (LSI).

0002

2. Description of the Related Art Conventionally, a pattern matching processing method using this type of pattern recognition device will be explained with reference to FIGS. 6(A) to 6(C). For example, as shown in FIG. A pattern consisting of a total of 16 digitized pixels is stored in advance as a reference pattern in memory. In this pattern, for example, the shaded area is represented by "1" as black information, and the other white information is represented as "0". When pattern matching is performed between this reference pattern and the data shown in FIG. 6(B), a matching number of 12/16 as shown in FIG. 6(C) is obtained.

[0003] As a pattern recognition device that performs such pattern matching processing, one disclosed in Japanese Patent Laid-Open No. 55-34800 is known. This pattern recognition device first performs a coarse search using coarse pixels sampled from the entire screen corresponding to one frame using a sampling clock of several clocks (for example, every 4 clocks) with respect to a reference clock, and performs a coarse pattern matching process. The aim is to miniaturize and speed up the device by performing a fine search using pixels corresponding to the reference clock.

[0004] In this pattern recognition device, all data for one frame of image information (hereinafter also referred to as data) captured by an imaging device such as a camera is transferred using a normal video signal transfer method. The digitization processing unit binarizes the binarized digital data, and the two-dimensional expansion control unit converts the binarized digital data into two-dimensional data so that it becomes an area including 256 pixels x 256 pixels as shown in FIG. 3(A). A reference pattern of a predetermined size is formed from this developed pattern and stored in a memory.

[0005] This standard pattern has a total of 64 (hereinafter referred to as rows) x 64 (hereinafter referred to as columns), or a total of 4,096
Formed by a reference area of pixels. By sampling this reference area in the vertical and horizontal directions every 4 clocks with respect to the reference clock, it is possible to generate a 16×16 superpixel, that is, a superpixel area consisting of 256 pixels. This superpixel is shown in Figure 3 (
When divided into four as shown in A), four 8×8, ie, 64 superpixel regions are generated. Furthermore, one of these 64 pixels, ie, 1/64, is composed of a 4×4 16-pixel area.

[0006] Such a reference pattern is stored in advance in the memory, but when performing pattern matching between this reference pattern and data for one frame captured by an imaging device, the size of this reference pattern and the There is a problem that correlators of equal size cannot be prepared. This is due to constraints such as the processing speed of the IC within the image processing device and the complexity of the circuit configuration, resulting in an increase in the size of the device.

Therefore, in the conventional pattern recognition device, the reference pattern is divided into multiple patterns corresponding to the size that can be processed by the correlator, that is, in the above example, four 8×8 patterns, and the divided patterns are captured from the imaging device. A method is used to compare the data with the available data. The data captured by this imaging device is one frame of serial data that has been two-dimensionally developed by a two-dimensional development control unit in the same way as a normal video signal, and has been developed into multiple rows and columns, so for example, , in the case where the reference pattern is divided into four parts with 8 rows and 8 columns, the coordinates of this divided pattern are first set as (0, 0) [
(0,0) means 0th row and 0th column. ], (0,1)
, (1,0), (1,1), this divided reference pattern and the data captured for one frame are first pattern matched with the pattern at coordinates (0,0), and then Stores the number of pattern matching matches in memory. Next, re-import one frame of data that is the same as the previous data, and the coordinates of the divided pattern (0
, 1) and write the matching number into memory. This is repeated to perform pattern matching with one frame of data having the same coordinates (1, 0) and (1, 1) on the line swept to the next row, and the number of matches is written in the memory. Then, by cumulatively adding up the matching numbers for each coordinate, a control means (not shown) determines whether the entire reference pattern and the data are equal to or greater than a predetermined matching number, which is a Q value.

Therefore, in the conventional apparatus, the same number of data as the number of divisions of the reference pattern is taken in. The detected point with the largest number of matches is determined to be the one for which pattern matching has been obtained, and then image processing is performed by performing a fine search in the vicinity of this detected point.

[0009]

[Problems to be Solved by the Invention] However, in pattern matching processing by a conventional pattern recognition device,
Divide the reference pattern into blocks of equal size that can be processed by the correlator, import the number of data equivalent to the divided reference pattern, calculate the number of pattern matches for the divided reference pattern, and cumulatively add it. death,
Since the number of pattern matchings for all reference patterns is calculated, there is a drawback that a large amount of processing time is required in proportion to the number of divisions of this reference pattern.

[0010] In recent years, in devices such as bonding devices that require processing performance in a short time, conventional pattern matching requires imaging for the time required to capture the same frame image as many times as the number of divisions of the reference pattern. Since the device has to wait, there is a drawback that processing time is required and high-speed processing is not possible.

The present invention was developed in view of the above-mentioned drawbacks of the prior art, and even when a correlator has a processing capacity for a size smaller than that of a reference pattern, it is difficult to perform rough pattern matching processing. Pattern matching is performed between the reference pattern divided within the time to capture one frame of data and one frame's worth of data, and the number of divisions for each reference coordinate is cumulatively added to determine the number of pattern matches with all reference patterns. It is an object of the present invention to provide a pattern recognition device and method capable of calculating and achieving high-speed processing.

0012

[Means for Solving the Problems] The present invention samples one frame worth of image signals inputted from an imaging device using a reference sampling clock, and extracts a pattern within a predefined area from binarized image information. a first storage means for storing a reference pattern; a reference pattern selection control section that divides the reference pattern stored in the first storage means into patterns of equal size and controls selection of the divided patterns; , a two-dimensional expansion control unit that expands the binarized image information in two-dimensional directions, a coordinate output unit that specifies an address of the image information to be expanded by the two-dimensional expansion control unit, and the two-dimensional expansion control. a correlator that performs pattern matching between the image information input from the unit at a predetermined timing and the pattern selected by the reference pattern selection control unit; and an adding unit that adds the number of pattern matchings obtained by the correlator; and second storage means for accumulating and storing the values output from the addition means.

[0013] Furthermore, the present invention stores a pattern within a predefined area from the binarized image information obtained by sampling one frame of an image signal inputted from an imaging device using a reference sampling clock as a reference pattern. a reference pattern selection control section that divides the reference pattern stored in the first storage means into patterns of equal size and controls the selection of the divided patterns; a two-dimensional expansion control unit that expands the converted image information in two-dimensional directions; a coordinate output unit that specifies the address of the image information to be expanded by the two-dimensional expansion control unit; a correlator that performs pattern matching between the image information inputted at the timing and the pattern selected by the reference pattern selection control section; an adding means for adding up the number of pattern matchings obtained by the correlator; a reference pattern that is input to the correlator while one frame of image information is input from the imaging device to the correlator; is replaced for each coordinate in the divided pattern unit, the number of pattern matchings in the divided pattern unit is determined for each coordinate, and the number is accumulated to the number of pattern matchings stored in the second storage means to obtain the total number of pattern matches. The number of pattern matchings in the reference pattern is calculated.

[0014] According to the present invention, a pattern within a predefined area is used as a reference pattern from the binarized image information obtained by sampling an image signal for one frame inputted from an imaging device using a reference sampling clock. The reference pattern stored in the first storage means is divided into patterns of equal size by a reference pattern selection control section, and the binarized image information is divided into patterns of equal size by a two-dimensional development control section. When pattern matching is performed by selecting image information expanded in the dimensional direction and input at a predetermined timing and a pattern divided by the reference pattern selection control section, while one frame is input from the imaging device, The reference pattern is exchanged for each coordinate in the divided pattern unit, and the number of pattern matchings in the divided pattern unit is calculated for each coordinate, and that number is used as the second
The number of pattern matchings for all reference patterns is calculated by accumulating the number of pattern matchings stored in the storage means.

[0015]

[Embodiment] Next, an embodiment of the pattern recognition apparatus according to the present invention will be described. FIG. 1 is a block diagram showing the circuit configuration of a pattern recognition device according to the present invention, FIG. 2 is a block diagram showing the configuration of the two-dimensional expansion control section shown in FIG. 1, and FIG.
A) and FIG. 3(B) are diagrams showing a state in which one frame of data has been flattened by the two-dimensional expansion control unit, and diagrams showing the timing of data transfer to the correlator, FIGS. 4 and 5.
FIG. 2 is an explanatory diagram illustrating a pattern matching method according to the present invention. It should be noted that devices having the same configuration as conventional devices will be described using the same reference numerals.

In FIG. 1, an imaging device 1 is mounted on an XY table that is movable in at least the X and Y directions, and is composed of a television camera, a lens, an illumination light, and the like. This imaging device 1 images semiconductor components such as lead frames and pads on IC chips that are positioned and placed on a transport mechanism (not shown) disposed below to provide image information (hereinafter referred to as
Also called data. ) to the binarization processing unit 2. The binarization processing unit 2 samples the transfer data output from the imaging device 1 using the reference sampling clock generated by the timing generation unit 10, performs binarization processing, and sends the two-dimensional expansion control unit 3 to the binarization processing. Output data. In this binarization process, for example, the lead of the lead frame is represented by "1" as black information, and the other parts are represented as "0" as white information.

The two-dimensional expansion control section 3 expands one frame of data sequentially input from the binarization processing section 2 in a two-dimensional direction. The two-dimensional expansion control unit 3 is composed of a line memory 101, a selector 201, etc. as shown in FIG. 101' and 101'' are the respective line memories of multiple lines L to which the line memories 101 are sequentially connected.
It is configured from 0 to Ln. 201, 201'
, 201'' is a selector that selects data from the line memories 101, 101', 101''.
The configuration is such that a plurality of pieces of data designated by the horizontal sampling interval Px can be selected from among the horizontal data for one line outputted respectively. 3
01 is the sampling interval in the vertical direction shown in the figure from among the data for multiple lines (L lines) whose sampling interval is defined by each horizontal PX selected by the selectors 201, 201', 201''. This is a selector configured to select a plurality of data specified by Py. Image data of m rows by n columns (m×n pixels) is obtained by this selector 301.

[0018] Also, a memory 4 for storing the reference pattern
is a rewritable memory (RAM) that selects a pattern within a predefined area from the input pattern r transferred from the two-dimensional expansion control unit 3, generates a reference pattern, and stores it. .

This reference pattern is used by the two-dimensional expansion control section 3.
256, which is the image area for one frame developed by
It is composed of a plane development section of pixels x 256 pixels, and a reference area of 64 x 64 pixels, that is, a total of 4,096 pixels, is generated as a reference pattern from this developed pattern. By sampling this reference pattern in the vertical and horizontal directions every 4 clocks with respect to the reference clock, it is possible to generate a superpixel area consisting of 16×16 pixels, that is, 256 pixels. By configuring this superpixel into four parts, four superpixel areas each consisting of 8×8, ie, 64 pixels, are generated. These four 8×8 superpixels constitute a reference pattern. 1/6 of this 8x8 superpixel, one of the 64 pixels
4 is composed of a 4×4 16 pixel area. Therefore, in this superpixel reference pattern, the minimum unit of 1/64 pixels is composed of 4×4 16 pixels, that is, coarse pixels having a clock count of 4×4 with respect to the reference clock.

The reference pattern selection control section 6 is controlled by a timing generation section 10 that generates a reference clock, horizontal and vertical synchronization signals, etc., and stores the reference pattern in the memory 4 based on the coordinate data of the image information captured by the imaging device 1. The coordinates of the data to be stored as a pattern are output as address signals, and when performing pattern matching, the coordinates of the reference pattern, for example, each coordinate (0,0
) [(0,0) means 0th row and 0th column. ], (0,
1), (1,0), and (1,1) are exchanged. Further, in this embodiment, the generation of the reference pattern to be stored in the memory 4 is performed at startup, but it may be performed, for example, at the time of self-teaching in which conditions are set in advance in a wire bonding device, etc. However, it is not necessary to always generate the reference pattern from the data of the two-dimensional expansion control section 3.

The coordinate output section 7 is controlled by the timing generation section 10 and generates target coordinates for pattern matching to be compared with each coordinate of the reference pattern.
As shown in FIG. 2, the line memory 1 of the two-dimensional expansion control section 3
01, 101', 101'' from L0 to Ln, respectively, from among the horizontal sampling interval Px and the selectors 201, 201.
It outputs an address signal that specifies the vertical sampling interval Py from among multiple lines (L lines) of data whose sampling interval is defined by each horizontal PX selected from ', 201''. A pattern c corresponding to each coordinate of the reference pattern is input to the correlator 5 by the output of the coordinate output section 7.

The matching number cumulative memory 8 is a memory for cumulatively adding the matching number at each coordinate to the address designated by the coordinate output unit 7. The data output from the matching number accumulation memory 8 is output to the adder 9 via the selector 11. The adder 9 calculates the maximum number of pattern matchings m×n output from the correlator 5.
and the number of matches accumulated in the matching number accumulation memory 8.

The selector 11 is configured so that, in addition to one input from the matching number accumulation memory 8, an input of 0 is initially made from a control means such as a microcomputer (not shown). This is, for example, the input pattern c to be compared with the reference pattern coordinates (0,0)
In the first case, the maximum matching number m×n is not stored in the matching number accumulation memory 8, so it is output as 0, and the output of the adder 9 is the same as that from the correlator 5. This is to output the maximum matching number m×n which is the output and store it in the matching number accumulation memory 8.

The timing generating section 10 generates a reference clock, a reference sampling clock, horizontal and vertical synchronization signals, etc., and also controls the two-dimensional development control section 3, reference pattern selection control section 6, etc. shown in FIG. Perform timing control. Further, condition settings and various controls for the entire apparatus are performed by a control means (CPU) including a microcomputer, etc. (not shown).

Next, the operation of the pattern recognition device according to this embodiment will be explained. ■1 input from the imaging device 1
A frame worth of data is sampled using a reference sampling clock of a timing generation section 10 to obtain a binarized image by a binarization processing section 2, which is then developed in a two-dimensional direction by a two-dimensional development control section 3. A reference pattern consisting of 16×16 super pixels is generated from the expanded binary data and stored in the memory 4 at an address specified by the reference pattern selection control section 6. Furthermore, a setting is made by a control means (not shown) so that 0 is output from the selector 11 only at the beginning.

■Next, the size of the reference pattern is set to 16×1.
6 super pixels, the interval of coordinates in the X direction for calculating the number of pattern matching is Px, the Y direction is Py, one sampling clock is a unit coordinate in the horizontal direction, and the number of sampling clocks for one line in the horizontal direction is in the vertical direction. data expanded two-dimensionally by the two-dimensional expansion control unit 3 first corresponds to unit coordinates 0
The data c for the row is selected by S0 of the selector 201 and output to the selector 301, and then the data c of the first row stored in L1 of the line memory 101 is selected by the selector 2.
01 S1 and output to the selector 301,
This operation is Ln of the line memory 101, selector 20
It is repeated until Sn of 1. Then, from among the selected row direction data, the selector 301 selects the data at intervals in the Y direction specified by the above PY and outputs them to the correlator 5.

Then, the divided reference pattern 8
Coordinates consisting of 8×8 corresponding to ×8 superpixel (
0,0), but in Figure 3(B)
As shown in , it is sampled every 2 clocks, so
At this timing, data corresponding to the 8×8 superpixel reference pattern is sequentially transferred to the correlator 5. That is, coordinates (0,0) and coordinates (0,1) on the same line
Since the data corresponding to the 8×8 superpixel located in is generated every reference clock and held for two clocks, the timing at which this data is transferred to the correlator 5 is sampled every two clocks.

At this time, at the timing of the first clock, pattern matching is performed with the upper left reference pattern divided from the entire reference pattern shown in FIG.
Pattern matching with the upper right reference pattern from among the reference patterns in FIG. 4 is performed at the timing of the clock.

Next, when sweeping downward to the next row shown in FIG. 3(B), the same column coordinates and coordinates (0, 0
), coordinates (1, 1), which is the same data as the 8x8 superpixel sampled during two clocks at coordinates (0,
0) and coordinates (1, 1) are transferred to the correlator 5, and in the same manner as described above, this data c and the divided reference pattern at the lower left of the reference pattern and the lower right Pattern matching is sequentially performed for each clock with the divided reference pattern.

Here, the position of the center coordinates of the entire target pattern corresponding to the center of the entire reference pattern has a relationship as shown in FIG. 5(A), and when this relationship is viewed for the entire pattern, it is as shown in FIG. As shown, when the target pattern is located at the center of a nine-divided block, matching with the reference pattern is performed at the coordinate points shown in FIG. 5(A).

■ Through such pattern matching processing, the correlator 5 calculates each pattern, that is, the coordinates (0,
By pattern matching processing from coordinates (0) to coordinates (1, 1), the number of matches for each pattern is output and input to the adder 9. The output of the adder 9 is configured to be fed back into the matching number accumulation memory 8, so the output from the adder 9 is a value obtained by accumulating the number of matches for each center coordinate of each target pattern. be done. Therefore, the output from the adder 9 provides the total matching number.

■ Out of the matching numbers obtained by the adder 9, the detection point where the maximum matching number is obtained is determined by a control means (not shown) to be the one that has been matched with the reference pattern, and is set as the detection point. .

(2) Next, after performing a search up to the detection point obtained by the rough search, a fine search is performed in the vicinity of the detection point.

As described above, according to the pattern matching process according to this embodiment, by replacing the reference pattern in units of 8×8 superpixel blocks,
A pattern matching operation can be performed on the entire target area with only one frame of input, and pattern matching can be performed by rough search in a processing time of one frame of target input data.

In this embodiment, the reference pattern is divided into 8×8 patterns, but it is needless to say that the reference pattern is not limited to these values and can be selected as appropriate.

The pattern recognition device according to the present invention can realize a pattern matching operation at high speed, so when it is applied to a position detection device in a wire bonder, which is a semiconductor manufacturing device, for example, It is possible to improve productivity, and it is possible to shorten the processing time for detecting the amount of deviation of the positioning device.

[0037]

[Effects of the Invention] As explained above, according to the present invention,
Even if a correlator has a processing capacity that is smaller than the size of the reference pattern, coarse pattern matching processing can be performed to match the reference pattern divided within the time it takes to capture one frame of data and the pattern of one frame of data. Matching is performed, and the number of pattern matches in pattern units divided for each coordinate is cumulatively added to calculate the number of pattern matches with all reference patterns, thereby achieving high-speed processing. Therefore, according to the present invention, since processing can be performed in the input time of one frame, there is no need for a special memory to store data for one frame, and the circuit configuration etc. can be easily configured. be able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of a pattern recognition device according to the present invention.

FIG. 2 is a block diagram showing the configuration of a two-dimensional expansion control section shown in FIG. 1;

FIG. 3(A) and FIG. 3(B) are diagrams showing a state in which one frame of data is expanded into a plane by a two-dimensional expansion control unit, and a diagram showing the timing of data transfer to a correlator. be.

FIG. 4 is an explanatory diagram illustrating a pattern matching method according to the present invention.

FIGS. 5A and 5B are explanatory diagrams illustrating a pattern matching method according to the present invention.

FIG. 6(A) to FIG. 6(C) are explanatory diagrams illustrating a pattern matching method according to the present invention.

[Explanation of sign]

1 Imaging device 2 Binarization processing section 3 Two-dimensional expansion control section 4 Memory (memory for storing reference pattern) 5
Correlator 6 Reference pattern selection control section 7 Coordinate output section 8 Matching number cumulative memory 9 Adder 10 Timing generation section 11 Selector

Claims (3)

[Claims] Claim 1: A first method for storing a pattern within a predefined area as a reference pattern from binarized image information obtained by sampling an image signal for one frame inputted from an imaging device using a reference sampling clock. a storage means; a reference pattern selection control section that divides the reference pattern stored in the first storage means into patterns of equal size and controls selection of the divided patterns;
a two-dimensional expansion control section that expands the binarized image information in two-dimensional directions; a coordinate output section that specifies an address of the image information that is expanded by the two-dimensional expansion control section; and the two-dimensional expansion control section. a correlator that performs pattern matching between the image information input at a predetermined timing from the reference pattern selection control section and the pattern selected by the reference pattern selection control section; A pattern recognition device comprising: second storage means for accumulating and storing values output from the addition means. 2. A first method for storing a pattern within a predefined area as a reference pattern from binarized image information obtained by sampling an image signal for one frame inputted from an imaging device using a reference sampling clock; a storage means, a reference pattern selection control section that divides the reference pattern stored in the first storage means into patterns of equal size and controls selection of the divided patterns; and the binarized image. a two-dimensional expansion control unit that expands information in two-dimensional directions; a coordinate output unit that specifies the address of image information to be expanded by the two-dimensional expansion control unit; a correlator that performs pattern matching between the image information and the pattern selected by the reference pattern selection control section; an adding means that adds up the number of pattern matchings obtained by the correlator; and a value output from the adding means. The second part that accumulates and stores
and a storage means for storing a reference pattern to be input to the correlator for each coordinate in units of the divided patterns while the image information input to the correlator is input for one frame from the imaging device. The number of pattern matchings in each divided pattern unit is calculated for each coordinate, and the number is accumulated in the number of pattern matchings stored in the second storage means to calculate the number of pattern matchings in all reference patterns. A pattern recognition device characterized by: 3. A first storage means that uses a pattern within a predefined area as a reference pattern from image information obtained by sampling one frame worth of image signal inputted from the imaging device using a reference sampling clock and converting it into a binary image. The reference pattern stored in the first storage means is divided into patterns of equal size by a reference pattern selection control section, and the binarized image information is divided into patterns of equal size by a two-dimensional expansion control section. When pattern matching is performed by selecting the image information developed and input at a predetermined timing and the divided pattern by the reference pattern selection control section, the reference pattern is is exchanged for each coordinate in each divided pattern unit to obtain the number of pattern matchings in each divided pattern unit for each coordinate, and this number is accumulated to the number of pattern matchings stored in the second storage means to obtain all standards. A pattern recognition method characterized by calculating the number of pattern matchings in a pattern.