JPH0423326Y2 - - Google Patents

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Publication number
JPH0423326Y2
JPH0423326Y2 JP1983017824U JP1782483U JPH0423326Y2 JP H0423326 Y2 JPH0423326 Y2 JP H0423326Y2 JP 1983017824 U JP1983017824 U JP 1983017824U JP 1782483 U JP1782483 U JP 1782483U JP H0423326 Y2 JPH0423326 Y2 JP H0423326Y2
Authority
JP
Japan
Prior art keywords
semiconductor element
pin
lowermost
stopper pin
transport path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1983017824U
Other languages
Japanese (ja)
Other versions
JPS59125836U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1782483U priority Critical patent/JPS59125836U/en
Publication of JPS59125836U publication Critical patent/JPS59125836U/en
Application granted granted Critical
Publication of JPH0423326Y2 publication Critical patent/JPH0423326Y2/ja
Granted legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【考案の詳細な説明】 本考案は半導体素子の搬送装置に関するもので
ある。
[Detailed Description of the Invention] The present invention relates to a semiconductor device transport device.

従来IC、LSI等を試験するため測定部に搬送す
るのに、第1図に断面図をもつて示すように、縦
形搬送装置では半導体素子の自重を利用して一個
ずつ順次搬送する装置が用いられている。すなわ
ち第1図で1は搬送路、2は最下段半導体素子、
2′は直近上段半導体素子、3はストツパピン、
4は押えピンである。この縦形搬送装置ではスト
ツパピン3で最下段半導体素子2を保持し、この
状態で半導体素子多数が搬送路1内に積み重ねら
れている。この状態で次工程の測定部での半導体
素子の測定が終了し測定部が空席になると、押え
ピン4により直近上段半導体素子2′を押圧固定
し、ストツパピン3を引込めて最下段半導体素子
2を落下させ次工程の測定部に進ませる。最下段
半導体素子2が落下して次工程に進むと、またス
トツパピン3を搬送路1内に突出させ、押えピン
4を引込めて直近上段半導体素子2′をストツパ
ピン3まで落下させ一個ずつ次の部位に進ませ
る。順次同様の工程を繰り返して自動的に半導体
素子を搬送させる。
Conventionally, to transport ICs, LSIs, etc. to the measuring section for testing, a vertical transport device is used to transport semiconductor devices one by one using their own weight, as shown in the cross-sectional view in Figure 1. It is being That is, in FIG. 1, 1 is a transport path, 2 is a lowermost semiconductor element,
2' is the nearest upper semiconductor element, 3 is the stopper pin,
4 is a presser pin. In this vertical transport device, the lowermost semiconductor element 2 is held by a stopper pin 3, and in this state a large number of semiconductor elements are stacked in the transport path 1. In this state, when the measurement of the semiconductor device in the measurement section in the next step is completed and the measurement section becomes vacant, the presser pin 4 presses and fixes the semiconductor device 2' in the uppermost step, and the stopper pin 3 is retracted to remove the semiconductor device 2' in the lowermost step. and then proceed to the measurement section for the next process. When the lowest stage semiconductor device 2 falls and proceeds to the next process, the stopper pin 3 is again projected into the conveyance path 1, the presser pin 4 is retracted, and the nearest upper stage semiconductor device 2' is dropped to the stopper pin 3, and the next step is carried out one by one. Proceed to the part. Semiconductor elements are automatically transported by repeating the same steps one after another.

しかしながらこの種の搬送装置に使用される半
導体素子は樹脂でモールドされているのが一般的
である。しかもこの樹脂モールドは上形と下形と
に分離できる金形で挾みつけて樹脂を封入固化す
るため、金形の合わせ部分すなわち半導体素子の
中心部21,22にバリが生じ易く滑らかでなく
なつている。そのため前述した従来の縦形搬送装
置に適用してこの半導体素子を多数連続的に重ね
ると、直近上段半導体素子2′と最下段半導体素
子2との中心部21のバリがからみ合い、直近上
段半導体素子2′押えピン4にて押圧固定し、ス
トツパピン3を引込めても最下段半導体素子2は
下方に落下せず、いわゆる「詰り」現象が生じて
自動工程が中断するという不具合を生ずる。この
「詰り」現象が生じた場合には手動により搬送装
置に衝撃を与えて落下させなければならず、その
ための要員を配置する必要があり、更に工程中断
による時間の浪費があり、コストアツプを来たす
とともに工程不調の原因ともなる。
However, semiconductor elements used in this type of transport device are generally molded with resin. Moreover, since this resin mold is sandwiched between molds that can be separated into an upper mold and a lower mold and the resin is sealed and solidified, burrs are likely to form in the mating parts of the molds, that is, the center parts 21 and 22 of the semiconductor element, making them less smooth. ing. Therefore, when a large number of these semiconductor devices are stacked one on top of the other in succession using the conventional vertical conveyance device described above, the burrs in the center portions 21 of the nearest upper semiconductor device 2' and the lowest semiconductor device 2 become entangled, and the nearest upper semiconductor device Even when the semiconductor element 2' is pressed and fixed by the presser pin 4 and the stopper pin 3 is retracted, the lowermost semiconductor element 2 does not fall downward, resulting in a so-called "clog" phenomenon and the automatic process being interrupted. When this "clog" phenomenon occurs, it is necessary to manually impact the conveyor to cause it to fall, which requires the deployment of personnel, and furthermore, the process is interrupted, wasting time and increasing costs. It also causes process failure.

従来の縦形搬送装置で「詰り」による生ずる
「詰り」回数と中断時間とを測定したところ次の
ようなデータが得られた。このデータは1日の稼
働時間のうち「詰り」の回数と、工程中断後処置
復旧して再スタートするまでに要した時間を積算
したものである。
When we measured the number of "clogs" and interruption times caused by "clogs" in a conventional vertical conveyor, we obtained the following data. This data is the sum of the number of "clogs" in one day's operating hours and the time required to restore and restart the process after interruption.

日付 「詰り」回数 中断時間(分) a 186 41 b 130 27 c 168 28 d 175 26 e 134 24 平均 159 29 すなわち上記データによると平均2.6分に1回
「詰り」が生じることになり、また全稼働時間の
うち6.9%は非稼働時間となり、稼働率、能率の
低下に加えて要員配置を必要とする欠点があつ
た。
Date Number of "clogs" Interruption time (minutes) a 186 41 b 130 27 c 168 28 d 175 26 e 134 24 Average 159 29 In other words, according to the above data, a "clog" occurs once every 2.6 minutes on average, and all 6.9% of the operating time was non-operating time, which resulted in a decrease in operating rate and efficiency, as well as the need to allocate personnel.

本考案はかかる欠点に鑑みなされたもので「詰
り」が生じにくく中断時間も大幅に縮減できる搬
送装置を提供することを目的とするものである。
The present invention was devised in view of these drawbacks, and it is an object of the present invention to provide a conveying device that is less likely to cause clogging and can significantly reduce interruption time.

以下図面により詳細に説明する。第2図は本考
案にかかわる搬送装置の一実施例を示す断面図で
ある。引出符号1ないし4および21,22は第
1図と同一であるが、ストツパピン3の先端部に
テーパ部31を設けている点と、押えピン4の下
部に分離ピン5を設けた点が従来の装置と異な
る。この分離ピン5は押えピン4と連動して動
き、押えピン4が直近上段半導体素子2′を押圧
固定するとき、最下段半導体素子2と直近上段半
導体素子2′とが接する部分に突出挿入されるよ
うに配置されている。このように分離ピン5が最
下段半導体素子2と直近上段半導体素子2′との
間に突出挿入されると、最下段半導体素子2は若
干下に押し下げられる状態になるが、半導体素子
の外形は樹脂モールドの関係で半導体素子の中心
部21,22から端部に向つて若干テーパ状をな
し、このテーパとストツパピン3の先端に設けた
テーパ部31とが逃げ部となつて直近上段半導体
素子2′と最下段半導体素子2とを完全に分離で
きる。またストツパピン3にテーパ部がない場合
でも、搬送路1の半導体素子2の後方部に逃げ部
を作つておけば、同様に完全分離ができる。この
状態で次工程の測定部での半導体素子の測定工程
が終了し他に移送され空席ができたときにストツ
パピン3を引込めて最下段半導体素子2を落下さ
せ次工程の測定部に送るとともに後は今までと同
様にストツパピン3を搬送路1内に挿入して押え
ピン4および分離ピン5を引込めると半導体素子
が一個ずつ落下し、順次同様の工程を練り返す。
This will be explained in detail below with reference to the drawings. FIG. 2 is a sectional view showing an embodiment of the conveying device according to the present invention. The drawer symbols 1 to 4 and 21, 22 are the same as in FIG. 1, but the difference is that a tapered part 31 is provided at the tip of the stopper pin 3, and a separation pin 5 is provided at the bottom of the presser pin 4. The device is different. This separation pin 5 moves in conjunction with the holding pin 4, and when the holding pin 4 presses and fixes the immediately upper semiconductor element 2', it is inserted into the part where the lowermost semiconductor element 2 and the immediately upper semiconductor element 2' contact each other. It is arranged so that When the separation pin 5 is protruded and inserted between the lowermost semiconductor element 2 and the immediately upper semiconductor element 2', the lowermost semiconductor element 2 is pushed down slightly, but the external shape of the semiconductor element is Due to the resin molding, the semiconductor element has a slight taper shape from the center parts 21 and 22 toward the ends, and this taper and the taper part 31 provided at the tip of the stopper pin 3 form a relief part to close the upper semiconductor element 2. ' and the lowermost semiconductor element 2 can be completely separated. Further, even if the stopper pin 3 does not have a tapered portion, complete separation can be achieved in the same way if a relief portion is provided at the rear portion of the semiconductor element 2 in the transport path 1. In this state, when the measurement process of the semiconductor element in the measurement section of the next process is completed and the semiconductor element is transferred to another place and a vacant seat becomes available, the stopper pin 3 is retracted to drop the lowest semiconductor element 2 and send it to the measurement section of the next process. After that, as before, when the stopper pin 3 is inserted into the conveyance path 1 and the presser pin 4 and separation pin 5 are retracted, the semiconductor elements fall one by one, and the same process is repeated one after another.

すなわち本考案によれば押えピン3に併設した
分離ピン5とストツパピン3の先端部に設けたテ
ーパ部31との比較的簡単な追加構成で、しかも
分離ピン5は押えピン4と連動するため工程数を
増加することなく、効果面においては半導体素子
間のからみを完全に分離することができ、工程中
断により生ずる時間の空費を大幅に節減できる。
That is, according to the present invention, the separation pin 5 attached to the presser pin 3 and the tapered part 31 provided at the tip of the stopper pin 3 are relatively simple additional configurations, and since the separation pin 5 is interlocked with the presser pin 4, the process is simplified. Effectively, it is possible to completely separate the entanglements between semiconductor elements without increasing the number of semiconductor elements, and the wasted time caused by process interruptions can be greatly reduced.

前述の従来装置での「詰り」の回数と、工程中
断から処置復旧に要した中断時間とのデータと同
様の方法で本実施例による装置を測定したデータ
を次に示す。
The following is data obtained by measuring the apparatus according to this embodiment using the same method as the data on the number of "clogs" and the interruption time required for treatment recovery after process interruption in the conventional apparatus described above.

日付 「詰り」回数 中断時間(秒) a 11 33 b 13 56 c 6 18 d 13 52 e 6 13 f 8 19 平均 9.5 32 すなわち本考案による装置によれば「詰り」の
現象を皆無とすることはできないが従来に比べて
空費時間は大幅に減少し「詰り」は44分に1回、
稼働率の低下は僅か0.1%にとどまつている。「詰
り」回数の減少に比して中断時間が大幅に減少し
ているのはたとえ「詰り」現象が生じても即座に
半導体素子が分離落下し、直ちに復旧されたこと
を表しており、この面からも効果が著しいことが
わかる。
Date Number of "clogs" Interruption time (seconds) a 11 33 b 13 56 c 6 18 d 13 52 e 6 13 f 8 19 Average 9.5 32 In other words, according to the device according to the present invention, it is possible to eliminate the phenomenon of "clogs". Although it is not possible, wasted time has been significantly reduced compared to the past, and "clogs" occur once every 44 minutes.
The decline in occupancy rate was only 0.1%. The fact that the interruption time has significantly decreased compared to the decrease in the number of "clogs" indicates that even if a "clog" phenomenon occurs, the semiconductor element immediately separates and falls and is immediately restored. It can be seen from the surface that the effect is remarkable.

なお、上記実施例ではストツパピン3の先端部
をテーパ状にした例で説明したが、テーパ状にし
なくても本考案の目的は達成することができる。
また上記実施例では縦形の搬送装置で説明したが
傾斜した搬送路を持つ搬送装置においても同様の
効果が得られることはいうまでもない。
In the above embodiment, the tip of the stopper pin 3 is tapered, but the object of the present invention can be achieved even if the stopper pin 3 is not tapered.
Furthermore, although the above embodiments have been described using a vertical conveyance device, it goes without saying that similar effects can be obtained with a conveyance device having an inclined conveyance path.

以上説明したように本考案によれば、半導体素
子を搬送する装置において樹脂モールドによるバ
リ等があつてもラインを中断させることなく順次
次工程に搬送することができるので、空費時間を
大幅に節減し稼働率も向上させることとなり半導
体素子のコストを引き下げると共に安定した品質
の製品を得られるものである。
As explained above, according to the present invention, even if there is a burr caused by the resin mold in the equipment that transports semiconductor elements, the equipment can be transported to the next process without interrupting the line, so wasted time can be greatly reduced. This results in savings and improved operating efficiency, lowering the cost of semiconductor devices and making it possible to obtain products with stable quality.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の縦形搬送装置の断面図、第2図
は本考案の一実施例である縦形搬送装置の断面図
である。 1……搬送路、2……最下段半導体素子、2′
……直近上段半導体素子、3……ストツパピン、
4……押えピン、5……分離ピン、21,22…
…中心部、31……テーパ部。
FIG. 1 is a sectional view of a conventional vertical conveyance device, and FIG. 2 is a sectional view of a vertical conveyance device which is an embodiment of the present invention. 1... Conveyance path, 2... Lowermost semiconductor element, 2'
...immediate upper semiconductor element, 3...stopper pin,
4... Presser pin, 5... Separation pin, 21, 22...
...center part, 31...tapered part.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体素子を連続的に自然落下させる搬送路1
と、該搬送路1内の最下段半導体素子2を係止さ
せるストツパピン3と、該ストツパピン3により
係止された前記最下段半導体素子2の上部に重な
る直近上段半導体素子2′を押圧する押えピン4
と、該押えピン4と連動して前記搬送路1内に突
出する分離ピン5とからなり、前記搬送路1には
前記最下段半導体素子2の部分に逃げ部を設ける
と共に、前記分離ピン5は前記押えピン4の先端
より突出し前記押えピン4が前記直近半導体素子
2′を押圧するとき前記最下段半導体素子2と前
記直近半導体素子2′とを分離して突出挿入され
る位置に配置されることを特徴とする搬送装置。
Conveyance path 1 that allows semiconductor devices to continuously fall naturally
, a stopper pin 3 for locking the lowermost semiconductor element 2 in the transport path 1, and a presser pin for pressing the immediately upper semiconductor element 2' overlapping the upper part of the lowermost semiconductor element 2 locked by the stopper pin 3. 4
and a separation pin 5 that protrudes into the transport path 1 in conjunction with the holding pin 4. The transport path 1 is provided with an escape portion in the portion of the lowermost semiconductor element 2, and the separation pin 5 is arranged at a position that protrudes from the tip of the holding pin 4 and is inserted so as to separate the lowermost semiconductor element 2 and the nearest semiconductor element 2' when the holding pin 4 presses the nearest semiconductor element 2'. A conveying device characterized by:
JP1782483U 1983-02-09 1983-02-09 Conveyance device Granted JPS59125836U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1782483U JPS59125836U (en) 1983-02-09 1983-02-09 Conveyance device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1782483U JPS59125836U (en) 1983-02-09 1983-02-09 Conveyance device

Publications (2)

Publication Number Publication Date
JPS59125836U JPS59125836U (en) 1984-08-24
JPH0423326Y2 true JPH0423326Y2 (en) 1992-05-29

Family

ID=30149050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1782483U Granted JPS59125836U (en) 1983-02-09 1983-02-09 Conveyance device

Country Status (1)

Country Link
JP (1) JPS59125836U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8405282B2 (en) 2010-05-28 2013-03-26 Nihon Dempa Kogyo Co., Ltd. Piezoelectric devices exhibiting enhanced resistance to physical impacts and moisture incursion

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5640262A (en) * 1979-09-11 1981-04-16 Nec Corp Supply mechanism of integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5640262A (en) * 1979-09-11 1981-04-16 Nec Corp Supply mechanism of integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8405282B2 (en) 2010-05-28 2013-03-26 Nihon Dempa Kogyo Co., Ltd. Piezoelectric devices exhibiting enhanced resistance to physical impacts and moisture incursion

Also Published As

Publication number Publication date
JPS59125836U (en) 1984-08-24

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